llvm/lib/Target/VE/VETargetTransformInfo.h

   1 //===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file a TargetTransformInfo::Concept conforming object specific to the
  10 /// VE target machine. It uses the target's detailed information to
  11 /// provide more precise answers to certain TTI queries, while letting the
  12 /// target independent and default TTI implementations handle the rest.
  13 ///
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
  17 #define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
  18
  19 #include "VE.h"
  20 #include "VETargetMachine.h"
  21 #include "llvm/Analysis/TargetTransformInfo.h"
  22 #include "llvm/CodeGen/BasicTTIImpl.h"
  23
  24 namespace llvm {
  25
  26 class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
  27   using BaseT = BasicTTIImplBase<VETTIImpl>;
  28   friend BaseT;
  29
  30   const VESubtarget *ST;
  31   const VETargetLowering *TLI;
  32
  33   const VESubtarget *getST() const { return ST; }
  34   const VETargetLowering *getTLI() const { return TLI; }
  35
  36   bool enableVPU() const { return getST()->enableVPU(); }
  37
  38 public:
  39   explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
  40       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
  41         TLI(ST->getTargetLowering()) {}
  42
  43   unsigned getNumberOfRegisters(unsigned ClassID) const {
  44     bool VectorRegs = (ClassID == 1);
  45     if (VectorRegs) {
  46       // TODO report vregs once vector isel is stable.
  47       return 0;
  48     }
  49
  50     return 64;
  51   }
  52
  53   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
  54     switch (K) {
  55     case TargetTransformInfo::RGK_Scalar:
  56       return TypeSize::getFixed(64);
  57     case TargetTransformInfo::RGK_FixedWidthVector:
  58       // TODO report vregs once vector isel is stable.
  59       return TypeSize::getFixed(0);
  60     case TargetTransformInfo::RGK_ScalableVector:
  61       return TypeSize::getScalable(0);
  62     }
  63
  64     llvm_unreachable("Unsupported register kind");
  65   }
  66
  67   /// \returns How the target needs this vector-predicated operation to be
  68   /// transformed.
  69   TargetTransformInfo::VPLegalization
  70   getVPLegalizationStrategy(const VPIntrinsic &PI) const {
  71     using VPLegalization = TargetTransformInfo::VPLegalization;
  72     return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
  73   }
  74
  75   unsigned getMinVectorRegisterBitWidth() const {
  76     // TODO report vregs once vector isel is stable.
  77     return 0;
  78   }
  79
  80   bool shouldBuildRelLookupTables() const {
  81     // NEC nld doesn't support relative lookup tables.  It shows following
  82     // errors.  So, we disable it at the moment.
  83     //   /opt/nec/ve/bin/nld: src/CMakeFiles/cxxabi_shared.dir/cxa_demangle.cpp
  84     //   .o(.rodata+0x17b4): reloc against `.L.str.376': error 2
  85     //   /opt/nec/ve/bin/nld: final link failed: Nonrepresentable section on
  86     //   output
  87     return false;
  88   }
  89 };
  90
  91 } // namespace llvm
  92
  93 #endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H