llvm/lib/Target/WebAssembly/WebAssembly.td

   1 //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This is a target description file for the WebAssembly architecture,
  11 /// which is also known as "wasm".
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // Target-independent interfaces which we are implementing
  17 //===----------------------------------------------------------------------===//
  18
  19 include "llvm/Target/Target.td"
  20
  21 //===----------------------------------------------------------------------===//
  22 // WebAssembly Subtarget features.
  23 //===----------------------------------------------------------------------===//
  24
  25 def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
  26                                       "Enable 128-bit SIMD">;
  27
  28 def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
  29                                       "Enable Atomics">;
  30
  31 def FeatureNontrappingFPToInt :
  32       SubtargetFeature<"nontrapping-fptoint",
  33                        "HasNontrappingFPToInt", "true",
  34                        "Enable non-trapping float-to-int conversion operators">;
  35
  36 def FeatureSignExt :
  37       SubtargetFeature<"sign-ext",
  38                        "HasSignExt", "true",
  39                        "Enable sign extension operators">;
  40
  41 def FeatureTailCall :
  42       SubtargetFeature<"tail-call",
  43                        "HasTailCall", "true",
  44                        "Enable tail call instructions">;
  45
  46 def FeatureExceptionHandling :
  47       SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
  48                        "Enable Wasm exception handling">;
  49
  50 def FeatureBulkMemory :
  51       SubtargetFeature<"bulk-memory", "HasBulkMemory", "true",
  52                        "Enable bulk memory operations">;
  53
  54 def FeatureMultivalue :
  55       SubtargetFeature<"multivalue",
  56                        "HasMultivalue", "true",
  57                        "Enable multivalue blocks, instructions, and functions">;
  58
  59 def FeatureMutableGlobals :
  60       SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true",
  61                        "Enable mutable globals">;
  62
  63 def FeatureReferenceTypes :
  64       SubtargetFeature<"reference-types", "HasReferenceTypes", "true",
  65                        "Enable reference types">;
  66
  67 //===----------------------------------------------------------------------===//
  68 // Architectures.
  69 //===----------------------------------------------------------------------===//
  70
  71 //===----------------------------------------------------------------------===//
  72 // Register File Description
  73 //===----------------------------------------------------------------------===//
  74
  75 include "WebAssemblyRegisterInfo.td"
  76
  77 //===----------------------------------------------------------------------===//
  78 // Instruction Descriptions
  79 //===----------------------------------------------------------------------===//
  80
  81 include "WebAssemblyInstrInfo.td"
  82
  83 def WebAssemblyInstrInfo : InstrInfo;
  84
  85 //===----------------------------------------------------------------------===//
  86 // WebAssembly Processors supported.
  87 //===----------------------------------------------------------------------===//
  88
  89 // Minimal Viable Product.
  90 def : ProcessorModel<"mvp", NoSchedModel, []>;
  91
  92 // Generic processor: latest stable version.
  93 def : ProcessorModel<"generic", NoSchedModel, []>;
  94
  95 // Latest and greatest experimental version of WebAssembly. Bugs included!
  96 def : ProcessorModel<"bleeding-edge", NoSchedModel,
  97                       [FeatureSIMD128, FeatureAtomics,
  98                        FeatureNontrappingFPToInt, FeatureSignExt,
  99                        FeatureMutableGlobals, FeatureBulkMemory,
 100                        FeatureTailCall]>;
 101
 102 //===----------------------------------------------------------------------===//
 103 // Target Declaration
 104 //===----------------------------------------------------------------------===//
 105
 106 def WebAssemblyAsmParser : AsmParser {
 107   // The physical register names are not in the binary format or asm text
 108   let ShouldEmitMatchRegisterName = 0;
 109 }
 110
 111 def WebAssemblyAsmWriter : AsmWriter {
 112   string AsmWriterClassName  = "InstPrinter";
 113   int PassSubtarget = 0;
 114   int Variant = 0;
 115   bit isMCAsmWriter = 1;
 116 }
 117
 118 def WebAssembly : Target {
 119   let InstructionSet = WebAssemblyInstrInfo;
 120   let AssemblyParsers  = [WebAssemblyAsmParser];
 121   let AssemblyWriters = [WebAssemblyAsmWriter];
 122 }