llvm/lib/Target/X86/X86InstrAMX.td

   1 //===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes the instructions that make up the Intel AMX instruction
  10 // set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // AMX instructions
  16
  17 let Predicates = [HasAMXTILE, In64BitMode] in {
  18   let SchedRW = [WriteSystem] in {
  19     let hasSideEffects = 1,
  20         Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
  21     def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
  22                        "ldtilecfg\t$src",
  23                        [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS;
  24     let hasSideEffects = 1 in
  25     def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
  26                        "sttilecfg\t$src",
  27                        [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD;
  28     let mayLoad = 1 in
  29     def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
  30                       (ins sibmem:$src),
  31                       "tileloadd\t{$src, $dst|$dst, $src}", []>,
  32                       VEX, T8XD;
  33     let mayLoad = 1 in
  34     def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
  35                         (ins sibmem:$src),
  36                         "tileloaddt1\t{$src, $dst|$dst, $src}", []>,
  37                         VEX, T8PD;
  38     let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
  39     def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
  40                         "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS;
  41     let mayStore = 1 in
  42     def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
  43                        (ins sibmem:$dst, TILE:$src),
  44                        "tilestored\t{$src, $dst|$dst, $src}", []>,
  45                        VEX, T8XS;
  46     def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
  47                      "tilezero\t$dst", []>,
  48                      VEX, T8XD;
  49
  50     // Pseduo instruction for RA.
  51     def PLDTILECFGV : PseudoI<(outs), (ins opaquemem:$src),
  52                               [(int_x86_ldtilecfg_internal addr:$src)]>;
  53     def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
  54                                                      GR16:$src2,
  55                                                      opaquemem:$src3), []>;
  56     def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
  57                                                        GR16:$src2,
  58                                                        opaquemem:$src3), []>;
  59     def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
  60                                             GR16:$src2, opaquemem:$src3,
  61                                             TILE:$src4), []>;
  62     let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
  63       def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
  64                                 [(set TILE:$dst, (int_x86_tilezero_internal
  65                                   GR16:$src1, GR16:$src2))]>;
  66
  67     let usesCustomInserter = 1 in {
  68       // Pseudo instructions, using immediates instead of tile registers.
  69       // To be translated to the actual instructions in X86ISelLowering.cpp
  70       def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
  71       def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
  72                                           sibmem:$src2), []>;
  73       def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>;
  74       def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
  75                               [(int_x86_tilezero timm:$src)]>;
  76     }
  77   } // SchedRW
  78 } // HasAMXTILE
  79
  80 let Predicates = [HasAMXINT8, In64BitMode] in {
  81   let SchedRW = [WriteSystem] in {
  82     let Constraints = "$src1 = $dst" in {
  83       def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
  84                       (ins TILE:$src1, TILE:$src2, TILE:$src3),
  85                       "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
  86                       VEX_4V, T8XD;
  87       def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
  88                       (ins TILE:$src1, TILE:$src2, TILE:$src3),
  89                       "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
  90                       VEX_4V, T8XS;
  91       def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
  92                       (ins TILE:$src1, TILE:$src2, TILE:$src3),
  93                       "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
  94                       VEX_4V, T8PD;
  95       def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
  96                       (ins TILE:$src1, TILE:$src2, TILE:$src3),
  97                       "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
  98                       VEX_4V, T8PS;
  99     }
 100
 101     // Pseduo instruction for RA.
 102     let Constraints = "$src4 = $dst" in {
 103       def PTDPBSSDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
 104                               GR16:$src2, GR16:$src3, TILE:$src4,
 105                               TILE:$src5, TILE:$src6),
 106                               [(set TILE: $dst,
 107                               (int_x86_tdpbssd_internal GR16:$src1, GR16:$src2,
 108                               GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
 109       def PTDPBSUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
 110                               GR16:$src2, GR16:$src3, TILE:$src4,
 111                               TILE:$src5, TILE:$src6),
 112                               [(set TILE: $dst,
 113                               (int_x86_tdpbsud_internal GR16:$src1, GR16:$src2,
 114                                GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
 115       def PTDPBUSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
 116                               GR16:$src2, GR16:$src3, TILE:$src4,
 117                               TILE:$src5, TILE:$src6),
 118                               [(set TILE: $dst,
 119                               (int_x86_tdpbusd_internal GR16:$src1, GR16:$src2,
 120                               GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
 121       def PTDPBUUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
 122                               GR16:$src2, GR16:$src3, TILE:$src4,
 123                               TILE:$src5, TILE:$src6),
 124                               [(set TILE: $dst,
 125                               (int_x86_tdpbuud_internal GR16:$src1, GR16:$src2,
 126                               GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
 127     }
 128
 129     let usesCustomInserter = 1 in {
 130       // Pseudo instructions, using immediates instead of tile registers.
 131       // To be translated to the actual instructions in X86ISelLowering.cpp
 132       def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,
 133                              u8imm:$src2, u8imm:$src3),
 134                              [(int_x86_tdpbssd timm:$src1,
 135                                timm:$src2, timm:$src3)]>;
 136       def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1,
 137                              u8imm:$src2, u8imm:$src3),
 138                              [(int_x86_tdpbsud timm:$src1,
 139                                timm:$src2, timm:$src3)]>;
 140       def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1,
 141                              u8imm:$src2, u8imm:$src3),
 142                              [(int_x86_tdpbusd timm:$src1,
 143                                timm:$src2, timm:$src3)]>;
 144       def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1,
 145                              u8imm:$src2, u8imm:$src3),
 146                              [(int_x86_tdpbuud timm:$src1,
 147                                timm:$src2, timm:$src3)]>;
 148     }
 149   }
 150 } // HasAMXTILE
 151
 152 let Predicates = [HasAMXBF16, In64BitMode] in {
 153   let SchedRW = [WriteSystem] in {
 154     let Constraints = "$src1 = $dst" in
 155     def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
 156                       (ins TILE:$src1, TILE:$src2, TILE:$src3),
 157                       "tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
 158                       []>, VEX_4V, T8XS;
 159
 160     // Pseduo instruction for RA.
 161     let Constraints = "$src4 = $dst" in
 162       def PTDPBF16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
 163                                  GR16:$src2, GR16:$src3, TILE:$src4,
 164                                  TILE:$src5, TILE:$src6),
 165                                  [(set TILE: $dst,
 166                                   (int_x86_tdpbf16ps_internal GR16:$src1,
 167                                    GR16:$src2, GR16:$src3, TILE:$src4,
 168                                    TILE:$src5, TILE:$src6))]>;
 169
 170     let usesCustomInserter = 1 in {
 171       // Pseudo instructions, using immediates instead of tile registers.
 172       // To be translated to the actual instructions in X86ISelLowering.cpp
 173       def PTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1,
 174                                u8imm:$src2, u8imm:$src3),
 175                                [(int_x86_tdpbf16ps timm:$src1,
 176                                  timm:$src2, timm:$src3)]>;
 177     }
 178   }
 179 } // HasAMXTILE, HasAMXBF16