llvm/lib/Target/X86/X86SchedBroadwell.td

   1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Broadwell to support instruction
  10 // scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def BroadwellModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and BW can decode 4
  16   // instructions per cycle.
  17   let IssueWidth = 4;
  18   let MicroOpBufferSize = 192; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 16;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = BroadwellModel in {
  31
  32 // Broadwell can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def BWPort0 : ProcResource<1>;
  41 def BWPort1 : ProcResource<1>;
  42 def BWPort2 : ProcResource<1>;
  43 def BWPort3 : ProcResource<1>;
  44 def BWPort4 : ProcResource<1>;
  45 def BWPort5 : ProcResource<1>;
  46 def BWPort6 : ProcResource<1>;
  47 def BWPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def BWPort01  : ProcResGroup<[BWPort0, BWPort1]>;
  51 def BWPort23  : ProcResGroup<[BWPort2, BWPort3]>;
  52 def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
  53 def BWPort04  : ProcResGroup<[BWPort0, BWPort4]>;
  54 def BWPort05  : ProcResGroup<[BWPort0, BWPort5]>;
  55 def BWPort06  : ProcResGroup<[BWPort0, BWPort6]>;
  56 def BWPort15  : ProcResGroup<[BWPort1, BWPort5]>;
  57 def BWPort16  : ProcResGroup<[BWPort1, BWPort6]>;
  58 def BWPort56  : ProcResGroup<[BWPort5, BWPort6]>;
  59 def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
  60 def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
  61 def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
  62
  63 // 60 Entry Unified Scheduler
  64 def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
  65                               BWPort5, BWPort6, BWPort7]> {
  66   let BufferSize=60;
  67 }
  68
  69 // Integer division issued on port 0.
  70 def BWDivider : ProcResource<1>;
  71 // FP division and sqrt on port 0.
  72 def BWFPDivider : ProcResource<1>;
  73
  74 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available
  79 // until 5/5/6 cycles after the memory operand.
  80 def : ReadAdvance<ReadAfterVecLd, 5>;
  81 def : ReadAdvance<ReadAfterVecXLd, 5>;
  82 def : ReadAdvance<ReadAfterVecYLd, 6>;
  83
  84 def : ReadAdvance<ReadInt2Fpu, 0>;
  85
  86 // Many SchedWrites are defined in pairs with and without a folded load.
  87 // Instructions with folded loads are usually micro-fused, so they only appear
  88 // as two micro-ops when queued in the reservation station.
  89 // This multiclass defines the resource usage for variants with and without
  90 // folded loads.
  91 multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
  92                           list<ProcResourceKind> ExePorts,
  93                           int Lat, list<int> Res = [1], int UOps = 1,
  94                           int LoadLat = 5> {
  95   // Register variant is using a single cycle on ExePort.
  96   def : WriteRes<SchedRW, ExePorts> {
  97     let Latency = Lat;
  98     let ResourceCycles = Res;
  99     let NumMicroOps = UOps;
 100   }
 101
 102   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 103   // the latency (default = 5).
 104   def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
 105     let Latency = !add(Lat, LoadLat);
 106     let ResourceCycles = !listconcat([1], Res);
 107     let NumMicroOps = !add(UOps, 1);
 108   }
 109 }
 110
 111 // A folded store needs a cycle on port 4 for the store data, and an extra port
 112 // 2/3/7 cycle to recompute the address.
 113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
 114
 115 // Arithmetic.
 116 defm : BWWriteResPair<WriteALU,    [BWPort0156], 1>; // Simple integer ALU op.
 117 defm : BWWriteResPair<WriteADC,    [BWPort06], 1>; // Integer ALU + flags op.
 118
 119 // Integer multiplication.
 120 defm : BWWriteResPair<WriteIMul8,     [BWPort1],   3>;
 121 defm : BWWriteResPair<WriteIMul16,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>;
 122 defm : X86WriteRes<WriteIMul16Imm,    [BWPort1,BWPort0156], 4, [1,1], 2>;
 123 defm : X86WriteRes<WriteIMul16ImmLd,  [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>;
 124 defm : BWWriteResPair<WriteIMul16Reg, [BWPort1],   3>;
 125 defm : BWWriteResPair<WriteIMul32,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
 126 defm : BWWriteResPair<WriteMULX32,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
 127 defm : BWWriteResPair<WriteIMul32Imm, [BWPort1],   3>;
 128 defm : BWWriteResPair<WriteIMul32Reg, [BWPort1],   3>;
 129 defm : BWWriteResPair<WriteIMul64,    [BWPort1,BWPort5], 4, [1,1], 2>;
 130 defm : BWWriteResPair<WriteMULX64,    [BWPort1,BWPort5], 4, [1,1], 2>;
 131 defm : BWWriteResPair<WriteIMul64Imm, [BWPort1],   3>;
 132 defm : BWWriteResPair<WriteIMul64Reg, [BWPort1],   3>;
 133 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 134
 135 // TODO: Why isn't the BWDivider used consistently?
 136 defm : X86WriteRes<WriteDiv8,      [BWPort0, BWDivider], 25, [1, 10], 1>;
 137 defm : X86WriteRes<WriteDiv16,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 138 defm : X86WriteRes<WriteDiv32,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 139 defm : X86WriteRes<WriteDiv64,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 140 defm : X86WriteRes<WriteDiv8Ld,    [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 141 defm : X86WriteRes<WriteDiv16Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 142 defm : X86WriteRes<WriteDiv32Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 143 defm : X86WriteRes<WriteDiv64Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 144
 145 defm : X86WriteRes<WriteIDiv8,     [BWPort0, BWDivider], 25, [1,10], 1>;
 146 defm : X86WriteRes<WriteIDiv16,    [BWPort0, BWDivider], 25, [1,10], 1>;
 147 defm : X86WriteRes<WriteIDiv32,    [BWPort0, BWDivider], 25, [1,10], 1>;
 148 defm : X86WriteRes<WriteIDiv64,    [BWPort0, BWDivider], 25, [1,10], 1>;
 149 defm : X86WriteRes<WriteIDiv8Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 150 defm : X86WriteRes<WriteIDiv16Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 151 defm : X86WriteRes<WriteIDiv32Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 152 defm : X86WriteRes<WriteIDiv64Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 153
 154 defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>;
 155 defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>;
 156 defm : X86WriteRes<WriteBSWAP32,   [BWPort15], 1, [1], 1>;
 157 defm : X86WriteRes<WriteBSWAP64,   [BWPort06, BWPort15], 2, [1, 1], 2>;
 158 defm : X86WriteRes<WriteXCHG,      [BWPort0156], 2, [3], 3>;
 159
 160 defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 161
 162 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
 163
 164 defm : BWWriteResPair<WriteCMOV,  [BWPort06], 1>; // Conditional move.
 165 defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move.
 166
 167 def  : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
 168 def  : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
 169   let Latency = 2;
 170   let NumMicroOps = 3;
 171 }
 172
 173 defm : X86WriteRes<WriteLAHFSAHF,        [BWPort06], 1, [1], 1>;
 174 defm : X86WriteRes<WriteBitTest,         [BWPort06], 1, [1], 1>; // Bit Test instrs
 175 defm : X86WriteRes<WriteBitTestImmLd,    [BWPort06,BWPort23], 6, [1,1], 2>;
 176 defm : X86WriteRes<WriteBitTestRegLd,    [BWPort0156,BWPort23], 6, [1,1], 2>;
 177 defm : X86WriteRes<WriteBitTestSet,      [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
 178 defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>;
 179 defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>;
 180
 181 // Bit counts.
 182 defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
 183 defm : BWWriteResPair<WriteBSR, [BWPort1], 3>;
 184 defm : BWWriteResPair<WriteLZCNT,          [BWPort1], 3>;
 185 defm : BWWriteResPair<WriteTZCNT,          [BWPort1], 3>;
 186 defm : BWWriteResPair<WritePOPCNT,         [BWPort1], 3>;
 187
 188 // Integer shifts and rotates.
 189 defm : BWWriteResPair<WriteShift,    [BWPort06],  1>;
 190 defm : BWWriteResPair<WriteShiftCL,  [BWPort06,BWPort0156],  3, [2,1], 3>;
 191 defm : BWWriteResPair<WriteRotate,   [BWPort06],  1, [1], 1>;
 192 defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156],  3, [2,1], 3>;
 193
 194 // SHLD/SHRD.
 195 defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;
 196 defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>;
 197 defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>;
 198 defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>;
 199
 200 // BMI1 BEXTR/BLS, BMI2 BZHI
 201 defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
 202 defm : BWWriteResPair<WriteBLS,   [BWPort15], 1>;
 203 defm : BWWriteResPair<WriteBZHI,  [BWPort15], 1>;
 204
 205 // Loads, stores, and moves, not folded with other operations.
 206 defm : X86WriteRes<WriteLoad,    [BWPort23], 5, [1], 1>;
 207 defm : X86WriteRes<WriteStore,   [BWPort237, BWPort4], 1, [1,1], 1>;
 208 defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>;
 209 defm : X86WriteRes<WriteMove,    [BWPort0156], 1, [1], 1>;
 210
 211 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
 212 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
 213 defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
 214
 215 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 216 // These can often bypass execution ports completely.
 217 def : WriteRes<WriteZero,  []>;
 218
 219 // Treat misc copies as a move.
 220 def : InstRW<[WriteMove], (instrs COPY)>;
 221
 222 // Branches don't produce values, so they have no latency, but they still
 223 // consume resources. Indirect branches can fold loads.
 224 defm : BWWriteResPair<WriteJump,  [BWPort06],   1>;
 225
 226 // Floating point. This covers both scalar and vector operations.
 227 defm : X86WriteRes<WriteFLD0,          [BWPort01], 1, [1], 1>;
 228 defm : X86WriteRes<WriteFLD1,          [BWPort01], 1, [2], 2>;
 229 defm : X86WriteRes<WriteFLDC,          [BWPort01], 1, [2], 2>;
 230 defm : X86WriteRes<WriteFLoad,         [BWPort23], 5, [1], 1>;
 231 defm : X86WriteRes<WriteFLoadX,        [BWPort23], 5, [1], 1>;
 232 defm : X86WriteRes<WriteFLoadY,        [BWPort23], 6, [1], 1>;
 233 defm : X86WriteRes<WriteFMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 234 defm : X86WriteRes<WriteFMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 235 defm : X86WriteRes<WriteFStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 236 defm : X86WriteRes<WriteFStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 237 defm : X86WriteRes<WriteFStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 238 defm : X86WriteRes<WriteFStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 239 defm : X86WriteRes<WriteFStoreNTX,     [BWPort237,BWPort4], 1, [1,1], 2>;
 240 defm : X86WriteRes<WriteFStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 241
 242 defm : X86WriteRes<WriteFMaskedStore32,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 243 defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 244 defm : X86WriteRes<WriteFMaskedStore64,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 245 defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 246
 247 defm : X86WriteRes<WriteFMove,         [BWPort5], 1, [1], 1>;
 248 defm : X86WriteRes<WriteFMoveX,        [BWPort5], 1, [1], 1>;
 249 defm : X86WriteRes<WriteFMoveY,        [BWPort5], 1, [1], 1>;
 250
 251 defm : BWWriteResPair<WriteFAdd,    [BWPort1],  3, [1], 1, 5>; // Floating point add/sub.
 252 defm : BWWriteResPair<WriteFAddX,   [BWPort1],  3, [1], 1, 5>; // Floating point add/sub (XMM).
 253 defm : BWWriteResPair<WriteFAddY,   [BWPort1],  3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
 254 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 255 defm : BWWriteResPair<WriteFAdd64,  [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub.
 256 defm : BWWriteResPair<WriteFAdd64X, [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub (XMM).
 257 defm : BWWriteResPair<WriteFAdd64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
 258 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 259
 260 defm : BWWriteResPair<WriteFCmp,    [BWPort1],  3, [1], 1, 5>; // Floating point compare.
 261 defm : BWWriteResPair<WriteFCmpX,   [BWPort1],  3, [1], 1, 5>; // Floating point compare (XMM).
 262 defm : BWWriteResPair<WriteFCmpY,   [BWPort1],  3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
 263 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 264 defm : BWWriteResPair<WriteFCmp64,  [BWPort1],  3, [1], 1, 5>; // Floating point double compare.
 265 defm : BWWriteResPair<WriteFCmp64X, [BWPort1],  3, [1], 1, 5>; // Floating point double compare (XMM).
 266 defm : BWWriteResPair<WriteFCmp64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
 267 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 268
 269 defm : BWWriteResPair<WriteFCom,    [BWPort1],  3>; // Floating point compare to flags (X87).
 270 defm : BWWriteResPair<WriteFComX,   [BWPort1],  3>; // Floating point compare to flags (SSE).
 271
 272 defm : BWWriteResPair<WriteFMul,    [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
 273 defm : BWWriteResPair<WriteFMulX,   [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
 274 defm : BWWriteResPair<WriteFMulY,   [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
 275 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 276 defm : BWWriteResPair<WriteFMul64,  [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication.
 277 defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
 278 defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
 279 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 280
 281 //defm : BWWriteResPair<WriteFDiv,     [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 282 defm : BWWriteResPair<WriteFDivX,    [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
 283 defm : BWWriteResPair<WriteFDivY,    [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
 284 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 285 //defm : BWWriteResPair<WriteFDiv64,   [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division.
 286 defm : BWWriteResPair<WriteFDiv64X,  [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
 287 defm : BWWriteResPair<WriteFDiv64Y,  [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
 288 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 289
 290 defm : X86WriteRes<WriteFSqrt,       [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root.
 291 defm : X86WriteRes<WriteFSqrtLd,     [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>;
 292 defm : BWWriteResPair<WriteFSqrtX,   [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM).
 293 defm : BWWriteResPair<WriteFSqrtY,   [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
 294 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 295 defm : X86WriteRes<WriteFSqrt64,     [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root.
 296 defm : X86WriteRes<WriteFSqrt64Ld,   [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>;
 297 defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM).
 298 defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
 299 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 300 defm : BWWriteResPair<WriteFSqrt80,  [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root.
 301
 302 defm : BWWriteResPair<WriteFRcp,   [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate.
 303 defm : BWWriteResPair<WriteFRcpX,  [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate (XMM).
 304 defm : BWWriteResPair<WriteFRcpY,  [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM).
 305 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 306
 307 defm : BWWriteResPair<WriteFRsqrt, [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate.
 308 defm : BWWriteResPair<WriteFRsqrtX,[BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM).
 309 defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM).
 310 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 311
 312 defm : BWWriteResPair<WriteFMA,    [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add.
 313 defm : BWWriteResPair<WriteFMAX,   [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
 314 defm : BWWriteResPair<WriteFMAY,   [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM).
 315 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 316 defm : BWWriteResPair<WriteDPPD,   [BWPort0,BWPort1,BWPort5],  9, [1,1,1], 3, 5>; // Floating point double dot product.
 317 defm : BWWriteResPair<WriteDPPS,   [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product.
 318 defm : BWWriteResPair<WriteDPPSY,  [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM).
 319 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 320 defm : BWWriteResPair<WriteFSign,     [BWPort5], 1>; // Floating point fabs/fchs.
 321 defm : X86WriteRes<WriteFRnd,            [BWPort23],  6, [1],   1>; // Floating point rounding.
 322 defm : X86WriteRes<WriteFRndY,           [BWPort23],  6, [1],   1>; // Floating point rounding (YMM/ZMM).
 323 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 324 defm : X86WriteRes<WriteFRndLd,  [BWPort1,BWPort23], 11, [2,1], 3>;
 325 defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>;
 326 defm : BWWriteResPair<WriteFLogic,    [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals.
 327 defm : BWWriteResPair<WriteFLogicY,   [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM).
 328 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 329 defm : BWWriteResPair<WriteFTest,     [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions.
 330 defm : BWWriteResPair<WriteFTestY,    [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM).
 331 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 332 defm : BWWriteResPair<WriteFShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles.
 333 defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM).
 334 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 335 defm : BWWriteResPair<WriteFVarShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles.
 336 defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 337 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 338 defm : BWWriteResPair<WriteFBlend,  [BWPort015], 1, [1], 1, 5>; // Floating point vector blends.
 339 defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends.
 340 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 341 defm : BWWriteResPair<WriteFVarBlend,  [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends.
 342 defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends.
 343 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 344
 345 // FMA Scheduling helper class.
 346 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 347
 348 // Vector integer operations.
 349 defm : X86WriteRes<WriteVecLoad,         [BWPort23], 5, [1], 1>;
 350 defm : X86WriteRes<WriteVecLoadX,        [BWPort23], 5, [1], 1>;
 351 defm : X86WriteRes<WriteVecLoadY,        [BWPort23], 6, [1], 1>;
 352 defm : X86WriteRes<WriteVecLoadNT,       [BWPort23], 5, [1], 1>;
 353 defm : X86WriteRes<WriteVecLoadNTY,      [BWPort23], 6, [1], 1>;
 354 defm : X86WriteRes<WriteVecMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 355 defm : X86WriteRes<WriteVecMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 356 defm : X86WriteRes<WriteVecStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 357 defm : X86WriteRes<WriteVecStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 358 defm : X86WriteRes<WriteVecStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 359 defm : X86WriteRes<WriteVecStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 360 defm : X86WriteRes<WriteVecStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 361 defm : X86WriteRes<WriteVecMaskedStore32,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 362 defm : X86WriteRes<WriteVecMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 363 defm : X86WriteRes<WriteVecMaskedStore64,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 364 defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 365 defm : X86WriteRes<WriteVecMove,         [BWPort015], 1, [1], 1>;
 366 defm : X86WriteRes<WriteVecMoveX,        [BWPort015], 1, [1], 1>;
 367 defm : X86WriteRes<WriteVecMoveY,        [BWPort015], 1, [1], 1>;
 368 defm : X86WriteRes<WriteVecMoveToGpr,    [BWPort0], 1, [1], 1>;
 369 defm : X86WriteRes<WriteVecMoveFromGpr,  [BWPort5], 1, [1], 1>;
 370
 371 defm : X86WriteRes<WriteEMMS,            [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>;
 372
 373 defm : BWWriteResPair<WriteVecALU,   [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 374 defm : BWWriteResPair<WriteVecALUX,  [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 375 defm : BWWriteResPair<WriteVecALUY,  [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM).
 376 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 377 defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 378 defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 379 defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM).
 380 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 381 defm : BWWriteResPair<WriteVecTest,  [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions.
 382 defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM).
 383 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 384 defm : BWWriteResPair<WriteVecIMul,  [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 385 defm : BWWriteResPair<WriteVecIMulX, [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 386 defm : BWWriteResPair<WriteVecIMulY, [BWPort0],  5, [1], 1, 6>; // Vector integer multiply.
 387 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 388 defm : BWWriteResPair<WritePMULLD,   [BWPort0], 10, [2], 2, 5>; // Vector PMULLD.
 389 defm : BWWriteResPair<WritePMULLDY,  [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM).
 390 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 391 defm : BWWriteResPair<WriteShuffle,  [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 392 defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 393 defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM).
 394 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 395 defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 396 defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 397 defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM).
 398 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 399 defm : BWWriteResPair<WriteBlend,  [BWPort5], 1, [1], 1, 5>; // Vector blends.
 400 defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM).
 401 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 402 defm : BWWriteResPair<WriteVarBlend,  [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
 403 defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
 404 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 405 defm : BWWriteResPair<WriteMPSAD,  [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
 406 defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD.
 407 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 408 defm : BWWriteResPair<WritePSADBW,   [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 409 defm : BWWriteResPair<WritePSADBWX,  [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 410 defm : BWWriteResPair<WritePSADBWY,  [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM).
 411 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 412 defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
 413
 414 // Vector integer shifts.
 415 defm : BWWriteResPair<WriteVecShift,     [BWPort0], 1, [1], 1, 5>;
 416 defm : BWWriteResPair<WriteVecShiftX,    [BWPort0,BWPort5],  2, [1,1], 2, 5>;
 417 defm : X86WriteRes<WriteVecShiftY,       [BWPort0,BWPort5],  4, [1,1], 2>;
 418 defm : X86WriteRes<WriteVecShiftYLd,     [BWPort0,BWPort23], 7, [1,1], 2>;
 419 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 420
 421 defm : BWWriteResPair<WriteVecShiftImm,  [BWPort0],  1, [1], 1, 5>;
 422 defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0],  1, [1], 1, 5>; // Vector integer immediate shifts (XMM).
 423 defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0],  1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM).
 424 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 425 defm : BWWriteResPair<WriteVarVecShift,  [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts.
 426 defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM).
 427 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 428
 429 // Vector insert/extract operations.
 430 def : WriteRes<WriteVecInsert, [BWPort5]> {
 431   let Latency = 2;
 432   let NumMicroOps = 2;
 433   let ResourceCycles = [2];
 434 }
 435 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
 436   let Latency = 6;
 437   let NumMicroOps = 2;
 438 }
 439
 440 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
 441   let Latency = 2;
 442   let NumMicroOps = 2;
 443 }
 444 def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
 445   let Latency = 2;
 446   let NumMicroOps = 3;
 447 }
 448
 449 // Conversion between integer and float.
 450 defm : BWWriteResPair<WriteCvtSS2I,   [BWPort1], 3>;
 451 defm : BWWriteResPair<WriteCvtPS2I,   [BWPort1], 3>;
 452 defm : BWWriteResPair<WriteCvtPS2IY,  [BWPort1], 3>;
 453 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 454 defm : BWWriteResPair<WriteCvtSD2I,   [BWPort1], 3>;
 455 defm : BWWriteResPair<WriteCvtPD2I,   [BWPort1], 3>;
 456 defm : BWWriteResPair<WriteCvtPD2IY,  [BWPort1], 3>;
 457 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 458
 459 defm : BWWriteResPair<WriteCvtI2SS,   [BWPort1], 4>;
 460 defm : BWWriteResPair<WriteCvtI2PS,   [BWPort1], 4>;
 461 defm : BWWriteResPair<WriteCvtI2PSY,  [BWPort1], 4>;
 462 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 463 defm : BWWriteResPair<WriteCvtI2SD,   [BWPort1], 4>;
 464 defm : BWWriteResPair<WriteCvtI2PD,   [BWPort1], 4>;
 465 defm : BWWriteResPair<WriteCvtI2PDY,  [BWPort1], 4>;
 466 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 467
 468 defm : BWWriteResPair<WriteCvtSS2SD,  [BWPort1], 3>;
 469 defm : BWWriteResPair<WriteCvtPS2PD,  [BWPort1], 3>;
 470 defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>;
 471 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 472 defm : BWWriteResPair<WriteCvtSD2SS,  [BWPort1], 3>;
 473 defm : BWWriteResPair<WriteCvtPD2PS,  [BWPort1], 3>;
 474 defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>;
 475 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 476
 477 defm : X86WriteRes<WriteCvtPH2PS,     [BWPort0,BWPort5], 2, [1,1], 2>;
 478 defm : X86WriteRes<WriteCvtPH2PSY,    [BWPort0,BWPort5], 2, [1,1], 2>;
 479 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 480 defm : X86WriteRes<WriteCvtPH2PSLd,  [BWPort0,BWPort23], 6, [1,1], 2>;
 481 defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>;
 482 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 483
 484 defm : X86WriteRes<WriteCvtPS2PH,    [BWPort1,BWPort5], 4, [1,1], 2>;
 485 defm : X86WriteRes<WriteCvtPS2PHY,   [BWPort1,BWPort5], 6, [1,1], 2>;
 486 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 487 defm : X86WriteRes<WriteCvtPS2PHSt,  [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>;
 488 defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>;
 489 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 490
 491 // Strings instructions.
 492
 493 // Packed Compare Implicit Length Strings, Return Mask
 494 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
 495   let Latency = 11;
 496   let NumMicroOps = 3;
 497   let ResourceCycles = [3];
 498 }
 499 def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
 500   let Latency = 16;
 501   let NumMicroOps = 4;
 502   let ResourceCycles = [3,1];
 503 }
 504
 505 // Packed Compare Explicit Length Strings, Return Mask
 506 def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
 507   let Latency = 19;
 508   let NumMicroOps = 9;
 509   let ResourceCycles = [4,3,1,1];
 510 }
 511 def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
 512   let Latency = 24;
 513   let NumMicroOps = 10;
 514   let ResourceCycles = [4,3,1,1,1];
 515 }
 516
 517 // Packed Compare Implicit Length Strings, Return Index
 518 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
 519   let Latency = 11;
 520   let NumMicroOps = 3;
 521   let ResourceCycles = [3];
 522 }
 523 def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
 524   let Latency = 16;
 525   let NumMicroOps = 4;
 526   let ResourceCycles = [3,1];
 527 }
 528
 529 // Packed Compare Explicit Length Strings, Return Index
 530 def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
 531   let Latency = 18;
 532   let NumMicroOps = 8;
 533   let ResourceCycles = [4,3,1];
 534 }
 535 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
 536   let Latency = 23;
 537   let NumMicroOps = 9;
 538   let ResourceCycles = [4,3,1,1];
 539 }
 540
 541 // MOVMSK Instructions.
 542 def : WriteRes<WriteFMOVMSK,    [BWPort0]> { let Latency = 3; }
 543 def : WriteRes<WriteVecMOVMSK,  [BWPort0]> { let Latency = 3; }
 544 def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; }
 545 def : WriteRes<WriteMMXMOVMSK,  [BWPort0]> { let Latency = 1; }
 546
 547 // AES instructions.
 548 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
 549   let Latency = 7;
 550   let NumMicroOps = 1;
 551   let ResourceCycles = [1];
 552 }
 553 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
 554   let Latency = 12;
 555   let NumMicroOps = 2;
 556   let ResourceCycles = [1,1];
 557 }
 558
 559 def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
 560   let Latency = 14;
 561   let NumMicroOps = 2;
 562   let ResourceCycles = [2];
 563 }
 564 def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
 565   let Latency = 19;
 566   let NumMicroOps = 3;
 567   let ResourceCycles = [2,1];
 568 }
 569
 570 def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
 571   let Latency = 29;
 572   let NumMicroOps = 11;
 573   let ResourceCycles = [2,7,2];
 574 }
 575 def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
 576   let Latency = 33;
 577   let NumMicroOps = 11;
 578   let ResourceCycles = [2,7,1,1];
 579 }
 580
 581 // Carry-less multiplication instructions.
 582 defm : BWWriteResPair<WriteCLMul,  [BWPort0], 5>;
 583
 584 // Catch-all for expensive system instructions.
 585 def : WriteRes<WriteSystem,     [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 586
 587 // AVX2.
 588 defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles.
 589 defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles.
 590 defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector shuffles.
 591 defm : BWWriteResPair<WriteVPMOV256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width packed vector width-changing move.
 592 defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector variable shuffles.
 593
 594 // Old microcoded instructions that nobody use.
 595 def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 596
 597 // Fence instructions.
 598 def : WriteRes<WriteFence,  [BWPort23, BWPort4]>;
 599
 600 // Load/store MXCSR.
 601 def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 602 def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 603
 604 // Nop, not very useful expect it provides a model for nops!
 605 def : WriteRes<WriteNop, []>;
 606
 607 ////////////////////////////////////////////////////////////////////////////////
 608 // Horizontal add/sub  instructions.
 609 ////////////////////////////////////////////////////////////////////////////////
 610
 611 defm : BWWriteResPair<WriteFHAdd,   [BWPort1,BWPort5], 5, [1,2], 3, 5>;
 612 defm : BWWriteResPair<WriteFHAddY,  [BWPort1,BWPort5], 5, [1,2], 3, 6>;
 613 defm : BWWriteResPair<WritePHAdd,  [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 614 defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 615 defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
 616
 617 // Remaining instrs.
 618
 619 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
 620   let Latency = 1;
 621   let NumMicroOps = 1;
 622   let ResourceCycles = [1];
 623 }
 624 def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
 625                                            "VPSRLVQ(Y?)rr")>;
 626
 627 def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
 628   let Latency = 1;
 629   let NumMicroOps = 1;
 630   let ResourceCycles = [1];
 631 }
 632 def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
 633                                            "UCOM_F(P?)r")>;
 634
 635 def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
 636   let Latency = 1;
 637   let NumMicroOps = 1;
 638   let ResourceCycles = [1];
 639 }
 640 def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
 641
 642 def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
 643   let Latency = 1;
 644   let NumMicroOps = 1;
 645   let ResourceCycles = [1];
 646 }
 647 def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 648
 649 def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
 650   let Latency = 1;
 651   let NumMicroOps = 1;
 652   let ResourceCycles = [1];
 653 }
 654 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
 655
 656 def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
 657   let Latency = 1;
 658   let NumMicroOps = 1;
 659   let ResourceCycles = [1];
 660 }
 661 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
 662
 663 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
 664   let Latency = 1;
 665   let NumMicroOps = 1;
 666   let ResourceCycles = [1];
 667 }
 668 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
 669
 670 def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
 671   let Latency = 1;
 672   let NumMicroOps = 1;
 673   let ResourceCycles = [1];
 674 }
 675 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
 676
 677 def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
 678   let Latency = 1;
 679   let NumMicroOps = 1;
 680   let ResourceCycles = [1];
 681 }
 682 def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
 683                                         SIDT64m,
 684                                         SMSW16m,
 685                                         STRm,
 686                                         SYSCALL)>;
 687
 688 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
 689   let Latency = 1;
 690   let NumMicroOps = 2;
 691   let ResourceCycles = [1,1];
 692 }
 693 def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
 694 def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
 695
 696 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
 697   let Latency = 2;
 698   let NumMicroOps = 2;
 699   let ResourceCycles = [2];
 700 }
 701 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
 702
 703 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
 704   let Latency = 2;
 705   let NumMicroOps = 2;
 706   let ResourceCycles = [2];
 707 }
 708 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
 709                                          MFENCE,
 710                                          WAIT,
 711                                          XGETBV)>;
 712
 713 def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
 714   let Latency = 2;
 715   let NumMicroOps = 2;
 716   let ResourceCycles = [1,1];
 717 }
 718 def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr",
 719                                             "(V?)CVTSS2SDrr")>;
 720
 721 def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
 722   let Latency = 2;
 723   let NumMicroOps = 2;
 724   let ResourceCycles = [1,1];
 725 }
 726 def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
 727
 728 def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
 729   let Latency = 2;
 730   let NumMicroOps = 2;
 731   let ResourceCycles = [1,1];
 732 }
 733 def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
 734
 735 def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
 736   let Latency = 2;
 737   let NumMicroOps = 2;
 738   let ResourceCycles = [1,1];
 739 }
 740 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
 741
 742 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
 743   let Latency = 2;
 744   let NumMicroOps = 2;
 745   let ResourceCycles = [1,1];
 746 }
 747 def: InstRW<[BWWriteResGroup20], (instrs CWD,
 748                                          JCXZ, JECXZ, JRCXZ,
 749                                          ADC8i8, SBB8i8,
 750                                          ADC16i16, SBB16i16,
 751                                          ADC32i32, SBB32i32,
 752                                          ADC64i32, SBB64i32)>;
 753
 754 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
 755   let Latency = 2;
 756   let NumMicroOps = 3;
 757   let ResourceCycles = [1,1,1];
 758 }
 759 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
 760
 761 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
 762   let Latency = 2;
 763   let NumMicroOps = 3;
 764   let ResourceCycles = [1,1,1];
 765 }
 766 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
 767
 768 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 769   let Latency = 2;
 770   let NumMicroOps = 3;
 771   let ResourceCycles = [1,1,1];
 772 }
 773 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 774                                          STOSB, STOSL, STOSQ, STOSW)>;
 775 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
 776
 777 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
 778   let Latency = 3;
 779   let NumMicroOps = 1;
 780   let ResourceCycles = [1];
 781 }
 782 def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>;
 783 def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr",
 784                                             "(V?)CVTDQ2PS(Y?)rr")>;
 785
 786 def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
 787   let Latency = 3;
 788   let NumMicroOps = 1;
 789   let ResourceCycles = [1];
 790 }
 791 def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
 792                                          VPBROADCASTWrr)>;
 793
 794 def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
 795   let Latency = 3;
 796   let NumMicroOps = 3;
 797   let ResourceCycles = [2,1];
 798 }
 799 def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr,
 800                                          MMX_PACKSSWBirr,
 801                                          MMX_PACKUSWBirr)>;
 802
 803 def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
 804   let Latency = 3;
 805   let NumMicroOps = 3;
 806   let ResourceCycles = [1,2];
 807 }
 808 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
 809
 810 def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
 811   let Latency = 3;
 812   let NumMicroOps = 3;
 813   let ResourceCycles = [1,2];
 814 }
 815 def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)",
 816                                             "RCR(8|16|32|64)r(1|i)")>;
 817
 818 def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
 819   let Latency = 3;
 820   let NumMicroOps = 4;
 821   let ResourceCycles = [1,1,1,1];
 822 }
 823 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
 824
 825 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
 826   let Latency = 3;
 827   let NumMicroOps = 4;
 828   let ResourceCycles = [1,1,1,1];
 829 }
 830 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
 831
 832 def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
 833   let Latency = 4;
 834   let NumMicroOps = 2;
 835   let ResourceCycles = [1,1];
 836 }
 837 def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
 838                                             "(V?)CVT(T?)SD2SIrr",
 839                                             "(V?)CVT(T?)SS2SI64rr",
 840                                             "(V?)CVT(T?)SS2SIrr")>;
 841
 842 def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
 843   let Latency = 4;
 844   let NumMicroOps = 2;
 845   let ResourceCycles = [1,1];
 846 }
 847 def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>;
 848
 849 def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
 850   let Latency = 4;
 851   let NumMicroOps = 2;
 852   let ResourceCycles = [1,1];
 853 }
 854 def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
 855
 856 def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
 857   let Latency = 4;
 858   let NumMicroOps = 2;
 859   let ResourceCycles = [1,1];
 860 }
 861 def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>;
 862 def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr",
 863                                             "MMX_CVT(T?)PS2PIirr",
 864                                             "(V?)CVTDQ2PDrr",
 865                                             "(V?)CVTPD2PSrr",
 866                                             "(V?)CVTSD2SSrr",
 867                                             "(V?)CVTSI642SDrr",
 868                                             "(V?)CVTSI2SDrr",
 869                                             "(V?)CVTSI2SSrr",
 870                                             "(V?)CVT(T?)PD2DQrr")>;
 871
 872 def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
 873   let Latency = 4;
 874   let NumMicroOps = 3;
 875   let ResourceCycles = [1,1,1];
 876 }
 877 def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
 878
 879 def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
 880   let Latency = 4;
 881   let NumMicroOps = 3;
 882   let ResourceCycles = [1,1,1];
 883 }
 884 def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
 885                                             "IST_F(16|32)m")>;
 886
 887 def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
 888   let Latency = 4;
 889   let NumMicroOps = 4;
 890   let ResourceCycles = [4];
 891 }
 892 def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
 893
 894 def BWWriteResGroup46 : SchedWriteRes<[]> {
 895   let Latency = 0;
 896   let NumMicroOps = 4;
 897   let ResourceCycles = [];
 898 }
 899 def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
 900
 901 def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
 902   let Latency = 5;
 903   let NumMicroOps = 1;
 904   let ResourceCycles = [1];
 905 }
 906 def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 907
 908 def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
 909   let Latency = 5;
 910   let NumMicroOps = 1;
 911   let ResourceCycles = [1];
 912 }
 913 def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)",
 914                                             "MOVZX(16|32|64)rm(8|16)")>;
 915 def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
 916                                          VMOVDDUPrm, MOVDDUPrm,
 917                                          VMOVSHDUPrm, MOVSHDUPrm,
 918                                          VMOVSLDUPrm, MOVSLDUPrm,
 919                                          VPBROADCASTDrm,
 920                                          VPBROADCASTQrm)>;
 921
 922 def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
 923   let Latency = 5;
 924   let NumMicroOps = 3;
 925   let ResourceCycles = [1,2];
 926 }
 927 def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
 928
 929 def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
 930   let Latency = 5;
 931   let NumMicroOps = 3;
 932   let ResourceCycles = [1,1,1];
 933 }
 934 def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
 935
 936 def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
 937   let Latency = 5;
 938   let NumMicroOps = 5;
 939   let ResourceCycles = [1,4];
 940 }
 941 def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
 942
 943 def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
 944   let Latency = 5;
 945   let NumMicroOps = 5;
 946   let ResourceCycles = [1,4];
 947 }
 948 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
 949
 950 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 951   let Latency = 5;
 952   let NumMicroOps = 6;
 953   let ResourceCycles = [1,1,4];
 954 }
 955 def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
 956
 957 def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
 958   let Latency = 6;
 959   let NumMicroOps = 1;
 960   let ResourceCycles = [1];
 961 }
 962 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
 963 def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
 964                                          VBROADCASTI128,
 965                                          VBROADCASTSDYrm,
 966                                          VBROADCASTSSYrm,
 967                                          VMOVDDUPYrm,
 968                                          VMOVSHDUPYrm,
 969                                          VMOVSLDUPYrm,
 970                                          VPBROADCASTDYrm,
 971                                          VPBROADCASTQYrm)>;
 972
 973 def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
 974   let Latency = 6;
 975   let NumMicroOps = 2;
 976   let ResourceCycles = [1,1];
 977 }
 978 def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm,
 979                                          CVTSS2SDrm, VCVTSS2SDrm,
 980                                          CVTSS2SDrm_Int, VCVTSS2SDrm_Int,
 981                                          VPSLLVQrm,
 982                                          VPSRLVQrm)>;
 983
 984 def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
 985   let Latency = 6;
 986   let NumMicroOps = 2;
 987   let ResourceCycles = [1,1];
 988 }
 989 def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr,
 990                                          VCVTPD2PSYrr,
 991                                          VCVTPD2DQYrr,
 992                                          VCVTTPD2DQYrr)>;
 993
 994 def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
 995   let Latency = 6;
 996   let NumMicroOps = 2;
 997   let ResourceCycles = [1,1];
 998 }
 999 def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>;
1000 def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
1001
1002 def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1003   let Latency = 6;
1004   let NumMicroOps = 2;
1005   let ResourceCycles = [1,1];
1006 }
1007 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1008                                             "MOVBE(16|32|64)rm")>;
1009
1010 def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1011   let Latency = 6;
1012   let NumMicroOps = 2;
1013   let ResourceCycles = [1,1];
1014 }
1015 def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
1016                                          VINSERTI128rm,
1017                                          VPBLENDDrmi)>;
1018
1019 def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1020   let Latency = 6;
1021   let NumMicroOps = 2;
1022   let ResourceCycles = [1,1];
1023 }
1024 def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
1025 def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
1026
1027 def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1028   let Latency = 6;
1029   let NumMicroOps = 4;
1030   let ResourceCycles = [1,1,1,1];
1031 }
1032 def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1033
1034 def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1035   let Latency = 6;
1036   let NumMicroOps = 4;
1037   let ResourceCycles = [1,1,1,1];
1038 }
1039 def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
1040                                             "SHL(8|16|32|64)m(1|i)",
1041                                             "SHR(8|16|32|64)m(1|i)")>;
1042
1043 def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1044   let Latency = 6;
1045   let NumMicroOps = 4;
1046   let ResourceCycles = [1,1,1,1];
1047 }
1048 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1049                                             "PUSH(16|32|64)rmm")>;
1050
1051 def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1052   let Latency = 6;
1053   let NumMicroOps = 6;
1054   let ResourceCycles = [1,5];
1055 }
1056 def: InstRW<[BWWriteResGroup71], (instrs STD)>;
1057
1058 def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1059   let Latency = 7;
1060   let NumMicroOps = 2;
1061   let ResourceCycles = [1,1];
1062 }
1063 def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
1064                                          VPSRLVQYrm)>;
1065
1066 def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1067   let Latency = 7;
1068   let NumMicroOps = 2;
1069   let ResourceCycles = [1,1];
1070 }
1071 def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
1072
1073 def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1074   let Latency = 7;
1075   let NumMicroOps = 2;
1076   let ResourceCycles = [1,1];
1077 }
1078 def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>;
1079
1080 def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1081   let Latency = 7;
1082   let NumMicroOps = 3;
1083   let ResourceCycles = [2,1];
1084 }
1085 def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm,
1086                                          MMX_PACKSSWBirm,
1087                                          MMX_PACKUSWBirm)>;
1088
1089 def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1090   let Latency = 7;
1091   let NumMicroOps = 3;
1092   let ResourceCycles = [1,2];
1093 }
1094 def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1095                                          SCASB, SCASL, SCASQ, SCASW)>;
1096
1097 def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1098   let Latency = 7;
1099   let NumMicroOps = 3;
1100   let ResourceCycles = [1,1,1];
1101 }
1102 def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
1103
1104 def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1105   let Latency = 7;
1106   let NumMicroOps = 3;
1107   let ResourceCycles = [1,1,1];
1108 }
1109 def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>;
1110
1111 def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1112   let Latency = 7;
1113   let NumMicroOps = 5;
1114   let ResourceCycles = [1,1,1,2];
1115 }
1116 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
1117                                             "ROR(8|16|32|64)m(1|i)")>;
1118
1119 def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> {
1120   let Latency = 2;
1121   let NumMicroOps = 2;
1122   let ResourceCycles = [2];
1123 }
1124 def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1125                                            ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1126
1127 def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1128   let Latency = 7;
1129   let NumMicroOps = 5;
1130   let ResourceCycles = [1,1,1,2];
1131 }
1132 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
1133
1134 def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1135   let Latency = 7;
1136   let NumMicroOps = 5;
1137   let ResourceCycles = [1,1,1,1,1];
1138 }
1139 def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;
1140 def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>;
1141
1142 def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1143   let Latency = 7;
1144   let NumMicroOps = 7;
1145   let ResourceCycles = [2,2,1,2];
1146 }
1147 def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
1148
1149 def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1150   let Latency = 8;
1151   let NumMicroOps = 2;
1152   let ResourceCycles = [1,1];
1153 }
1154 def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm,
1155                                          CVTDQ2PSrm,
1156                                          VCVTDQ2PSrm)>;
1157 def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
1158
1159 def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1160   let Latency = 8;
1161   let NumMicroOps = 2;
1162   let ResourceCycles = [1,1];
1163 }
1164 def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
1165                                          VPMOVSXBQYrm,
1166                                          VPMOVSXBWYrm,
1167                                          VPMOVSXDQYrm,
1168                                          VPMOVSXWDYrm,
1169                                          VPMOVSXWQYrm,
1170                                          VPMOVZXWDYrm)>;
1171
1172 def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1173   let Latency = 8;
1174   let NumMicroOps = 5;
1175   let ResourceCycles = [1,1,1,2];
1176 }
1177 def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
1178                                             "RCR(8|16|32|64)m(1|i)")>;
1179
1180 def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1181   let Latency = 8;
1182   let NumMicroOps = 6;
1183   let ResourceCycles = [1,1,1,3];
1184 }
1185 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
1186
1187 def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1188   let Latency = 8;
1189   let NumMicroOps = 6;
1190   let ResourceCycles = [1,1,1,2,1];
1191 }
1192 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
1193 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
1194                                              "ROR(8|16|32|64)mCL",
1195                                              "SAR(8|16|32|64)mCL",
1196                                              "SHL(8|16|32|64)mCL",
1197                                              "SHR(8|16|32|64)mCL")>;
1198
1199 def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1200   let Latency = 9;
1201   let NumMicroOps = 2;
1202   let ResourceCycles = [1,1];
1203 }
1204 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1205                                              "ILD_F(16|32|64)m")>;
1206 def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm,
1207                                           VCVTTPS2DQYrm)>;
1208
1209 def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1210   let Latency = 9;
1211   let NumMicroOps = 3;
1212   let ResourceCycles = [1,1,1];
1213 }
1214 def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
1215                                              "(V?)CVT(T?)SD2SI64rm",
1216                                              "(V?)CVT(T?)SD2SIrm",
1217                                              "VCVTTSS2SI64rm",
1218                                              "(V?)CVTTSS2SIrm")>;
1219
1220 def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1221   let Latency = 9;
1222   let NumMicroOps = 3;
1223   let ResourceCycles = [1,1,1];
1224 }
1225 def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>;
1226
1227 def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1228   let Latency = 9;
1229   let NumMicroOps = 3;
1230   let ResourceCycles = [1,1,1];
1231 }
1232 def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm,
1233                                           CVTPD2DQrm,
1234                                           CVTTPD2DQrm,
1235                                           MMX_CVTPI2PDirm)>;
1236 def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm",
1237                                              "(V?)CVTDQ2PDrm",
1238                                              "(V?)CVTSD2SSrm")>;
1239
1240 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
1241   let Latency = 9;
1242   let NumMicroOps = 3;
1243   let ResourceCycles = [1,1,1];
1244 }
1245 def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
1246                                              "VPBROADCASTW(Y?)rm")>;
1247
1248 def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1249   let Latency = 9;
1250   let NumMicroOps = 5;
1251   let ResourceCycles = [1,1,3];
1252 }
1253 def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
1254
1255 def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1256   let Latency = 9;
1257   let NumMicroOps = 5;
1258   let ResourceCycles = [1,2,1,1];
1259 }
1260 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1261                                              "LSL(16|32|64)rm")>;
1262
1263 def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
1264   let Latency = 10;
1265   let NumMicroOps = 2;
1266   let ResourceCycles = [1,1];
1267 }
1268 def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
1269
1270 def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
1271   let Latency = 10;
1272   let NumMicroOps = 3;
1273   let ResourceCycles = [2,1];
1274 }
1275 def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
1276
1277 def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1278   let Latency = 10;
1279   let NumMicroOps = 4;
1280   let ResourceCycles = [1,1,1,1];
1281 }
1282 def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1283
1284 def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1285   let Latency = 11;
1286   let NumMicroOps = 1;
1287   let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
1288 }
1289 def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
1290
1291 def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
1292   let Latency = 11;
1293   let NumMicroOps = 2;
1294   let ResourceCycles = [1,1];
1295 }
1296 def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
1297 def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
1298
1299 def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1300   let Latency = 11;
1301   let NumMicroOps = 3;
1302   let ResourceCycles = [1,1,1];
1303 }
1304 def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>;
1305
1306 def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1307   let Latency = 11;
1308   let NumMicroOps = 7;
1309   let ResourceCycles = [2,2,3];
1310 }
1311 def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
1312                                              "RCR(16|32|64)rCL")>;
1313
1314 def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1315   let Latency = 11;
1316   let NumMicroOps = 9;
1317   let ResourceCycles = [1,4,1,3];
1318 }
1319 def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>;
1320
1321 def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
1322   let Latency = 11;
1323   let NumMicroOps = 11;
1324   let ResourceCycles = [2,9];
1325 }
1326 def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
1327 def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
1328
1329 def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
1330   let Latency = 12;
1331   let NumMicroOps = 3;
1332   let ResourceCycles = [2,1];
1333 }
1334 def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1335
1336 def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1337   let Latency = 14;
1338   let NumMicroOps = 1;
1339   let ResourceCycles = [1,4];
1340 }
1341 def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
1342
1343 def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1344   let Latency = 14;
1345   let NumMicroOps = 3;
1346   let ResourceCycles = [1,1,1];
1347 }
1348 def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
1349
1350 def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1351   let Latency = 14;
1352   let NumMicroOps = 8;
1353   let ResourceCycles = [2,2,1,3];
1354 }
1355 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
1356
1357 def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1358   let Latency = 14;
1359   let NumMicroOps = 10;
1360   let ResourceCycles = [2,3,1,4];
1361 }
1362 def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>;
1363
1364 def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
1365   let Latency = 14;
1366   let NumMicroOps = 12;
1367   let ResourceCycles = [2,1,4,5];
1368 }
1369 def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
1370
1371 def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
1372   let Latency = 15;
1373   let NumMicroOps = 1;
1374   let ResourceCycles = [1];
1375 }
1376 def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1377
1378 def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1379   let Latency = 15;
1380   let NumMicroOps = 10;
1381   let ResourceCycles = [1,1,1,4,1,2];
1382 }
1383 def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
1384
1385 def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1386   let Latency = 16;
1387   let NumMicroOps = 2;
1388   let ResourceCycles = [1,1,5];
1389 }
1390 def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
1391
1392 def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1393   let Latency = 16;
1394   let NumMicroOps = 14;
1395   let ResourceCycles = [1,1,1,4,2,5];
1396 }
1397 def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
1398
1399 def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> {
1400   let Latency = 8;
1401   let NumMicroOps = 20;
1402   let ResourceCycles = [1,1];
1403 }
1404 def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
1405
1406 def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
1407   let Latency = 18;
1408   let NumMicroOps = 8;
1409   let ResourceCycles = [1,1,1,5];
1410 }
1411 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
1412 def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
1413
1414 def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1415   let Latency = 18;
1416   let NumMicroOps = 11;
1417   let ResourceCycles = [2,1,1,3,1,3];
1418 }
1419 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
1420
1421 def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1422   let Latency = 19;
1423   let NumMicroOps = 2;
1424   let ResourceCycles = [1,1,8];
1425 }
1426 def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
1427
1428 def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
1429   let Latency = 20;
1430   let NumMicroOps = 1;
1431   let ResourceCycles = [1];
1432 }
1433 def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1434
1435 def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1436   let Latency = 20;
1437   let NumMicroOps = 8;
1438   let ResourceCycles = [1,1,1,1,1,1,2];
1439 }
1440 def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
1441
1442 def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
1443   let Latency = 21;
1444   let NumMicroOps = 2;
1445   let ResourceCycles = [1,1];
1446 }
1447 def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
1448
1449 def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1450   let Latency = 21;
1451   let NumMicroOps = 19;
1452   let ResourceCycles = [2,1,4,1,1,4,6];
1453 }
1454 def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
1455
1456 def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1457   let Latency = 22;
1458   let NumMicroOps = 18;
1459   let ResourceCycles = [1,1,16];
1460 }
1461 def: InstRW<[BWWriteResGroup172], (instrs POPF64)>;
1462
1463 def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1464   let Latency = 23;
1465   let NumMicroOps = 19;
1466   let ResourceCycles = [3,1,15];
1467 }
1468 def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
1469
1470 def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1471   let Latency = 24;
1472   let NumMicroOps = 3;
1473   let ResourceCycles = [1,1,1];
1474 }
1475 def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
1476
1477 def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
1478   let Latency = 26;
1479   let NumMicroOps = 2;
1480   let ResourceCycles = [1,1];
1481 }
1482 def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
1483
1484 def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1485   let Latency = 29;
1486   let NumMicroOps = 3;
1487   let ResourceCycles = [1,1,1];
1488 }
1489 def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
1490
1491 def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1492   let Latency = 17;
1493   let NumMicroOps = 7;
1494   let ResourceCycles = [1,3,2,1];
1495 }
1496 def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm,
1497                                             VGATHERQPDrm, VPGATHERQQrm)>;
1498
1499 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1500   let Latency = 18;
1501   let NumMicroOps = 9;
1502   let ResourceCycles = [1,3,4,1];
1503 }
1504 def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
1505                                             VGATHERQPDYrm, VPGATHERQQYrm)>;
1506
1507 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1508   let Latency = 19;
1509   let NumMicroOps = 9;
1510   let ResourceCycles = [1,5,2,1];
1511 }
1512 def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
1513
1514 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1515   let Latency = 19;
1516   let NumMicroOps = 10;
1517   let ResourceCycles = [1,4,4,1];
1518 }
1519 def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm,
1520                                             VGATHERQPSYrm, VPGATHERQDYrm)>;
1521
1522 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1523   let Latency = 21;
1524   let NumMicroOps = 14;
1525   let ResourceCycles = [1,4,8,1];
1526 }
1527 def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
1528
1529 def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1530   let Latency = 29;
1531   let NumMicroOps = 27;
1532   let ResourceCycles = [1,5,1,1,19];
1533 }
1534 def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
1535
1536 def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1537   let Latency = 30;
1538   let NumMicroOps = 28;
1539   let ResourceCycles = [1,6,1,1,19];
1540 }
1541 def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
1542 def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1543
1544 def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
1545   let Latency = 34;
1546   let NumMicroOps = 23;
1547   let ResourceCycles = [1,5,3,4,10];
1548 }
1549 def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
1550                                              "IN(8|16|32)rr")>;
1551
1552 def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1553   let Latency = 35;
1554   let NumMicroOps = 23;
1555   let ResourceCycles = [1,5,2,1,4,10];
1556 }
1557 def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
1558                                              "OUT(8|16|32)rr")>;
1559
1560 def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
1561   let Latency = 42;
1562   let NumMicroOps = 22;
1563   let ResourceCycles = [2,20];
1564 }
1565 def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
1566
1567 def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
1568   let Latency = 60;
1569   let NumMicroOps = 64;
1570   let ResourceCycles = [2,2,8,1,10,2,39];
1571 }
1572 def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
1573
1574 def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1575   let Latency = 63;
1576   let NumMicroOps = 88;
1577   let ResourceCycles = [4,4,31,1,2,1,45];
1578 }
1579 def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
1580
1581 def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1582   let Latency = 63;
1583   let NumMicroOps = 90;
1584   let ResourceCycles = [4,2,33,1,2,1,47];
1585 }
1586 def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
1587
1588 def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
1589   let Latency = 75;
1590   let NumMicroOps = 15;
1591   let ResourceCycles = [6,3,6];
1592 }
1593 def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
1594
1595 def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
1596   let Latency = 115;
1597   let NumMicroOps = 100;
1598   let ResourceCycles = [9,9,11,8,1,11,21,30];
1599 }
1600 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
1601
1602 def: InstRW<[WriteZero], (instrs CLC)>;
1603
1604
1605 // Instruction variants handled by the renamer. These might not need execution
1606 // ports in certain conditions.
1607 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1608 // section "Haswell and Broadwell Pipeline" > "Register allocation and
1609 // renaming".
1610 // These can be investigated with llvm-exegesis, e.g.
1611 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1612 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1613
1614 def BWWriteZeroLatency : SchedWriteRes<[]> {
1615   let Latency = 0;
1616 }
1617
1618 def BWWriteZeroIdiom : SchedWriteVariant<[
1619     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1620     SchedVar<NoSchedPred,                          [WriteALU]>
1621 ]>;
1622 def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1623                                          XOR32rr, XOR64rr)>;
1624
1625 def BWWriteFZeroIdiom : SchedWriteVariant<[
1626     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1627     SchedVar<NoSchedPred,                          [WriteFLogic]>
1628 ]>;
1629 def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1630                                           VXORPDrr)>;
1631
1632 def BWWriteFZeroIdiomY : SchedWriteVariant<[
1633     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1634     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1635 ]>;
1636 def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1637
1638 def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[
1639     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1640     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1641 ]>;
1642 def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1643
1644 def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[
1645     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1646     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1647 ]>;
1648 def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1649
1650 def BWWriteVZeroIdiomALUX : SchedWriteVariant<[
1651     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1652     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1653 ]>;
1654 def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1655                                               PSUBDrr, VPSUBDrr,
1656                                               PSUBQrr, VPSUBQrr,
1657                                               PSUBWrr, VPSUBWrr,
1658                                               PCMPGTBrr, VPCMPGTBrr,
1659                                               PCMPGTDrr, VPCMPGTDrr,
1660                                               PCMPGTWrr, VPCMPGTWrr)>;
1661
1662 def BWWriteVZeroIdiomALUY : SchedWriteVariant<[
1663     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1664     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1665 ]>;
1666 def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
1667                                               VPSUBDYrr,
1668                                               VPSUBQYrr,
1669                                               VPSUBWYrr,
1670                                               VPCMPGTBYrr,
1671                                               VPCMPGTDYrr,
1672                                               VPCMPGTWYrr)>;
1673
1674 def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> {
1675   let Latency = 5;
1676   let NumMicroOps = 1;
1677   let ResourceCycles = [1];
1678 }
1679
1680 def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1681     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1682     SchedVar<NoSchedPred,                          [BWWritePCMPGTQ]>
1683 ]>;
1684 def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1685                                                  VPCMPGTQYrr)>;
1686
1687
1688 // CMOVs that use both Z and C flag require an extra uop.
1689 def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> {
1690   let Latency = 2;
1691   let ResourceCycles = [1,1];
1692   let NumMicroOps = 2;
1693 }
1694
1695 def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1696   let Latency = 7;
1697   let ResourceCycles = [1,1,1];
1698   let NumMicroOps = 3;
1699 }
1700
1701 def BWCMOVA_CMOVBErr :  SchedWriteVariant<[
1702   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>,
1703   SchedVar<NoSchedPred,                             [WriteCMOV]>
1704 ]>;
1705
1706 def BWCMOVA_CMOVBErm :  SchedWriteVariant<[
1707   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>,
1708   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1709 ]>;
1710
1711 def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1712 def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1713
1714 // SETCCs that use both Z and C flag require an extra uop.
1715 def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> {
1716   let Latency = 2;
1717   let ResourceCycles = [1,1];
1718   let NumMicroOps = 2;
1719 }
1720
1721 def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1722   let Latency = 3;
1723   let ResourceCycles = [1,1,1,1];
1724   let NumMicroOps = 4;
1725 }
1726
1727 def BWSETA_SETBErr :  SchedWriteVariant<[
1728   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>,
1729   SchedVar<NoSchedPred,                         [WriteSETCC]>
1730 ]>;
1731
1732 def BWSETA_SETBErm :  SchedWriteVariant<[
1733   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>,
1734   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1735 ]>;
1736
1737 def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>;
1738 def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>;
1739
1740 } // SchedModel