llvm/lib/Target/X86/X86ScheduleZnver2.td

   1 //=- X86ScheduleZnver2.td - X86 Znver2 Scheduling -------------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Znver2 to support instruction
  10 // scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def Znver2Model : SchedMachineModel {
  15   // Zen can decode 4 instructions per cycle.
  16   let IssueWidth = 4;
  17   // Based on the reorder buffer we define MicroOpBufferSize
  18   let MicroOpBufferSize = 224;
  19   let LoadLatency = 4;
  20   let MispredictPenalty = 17;
  21   let HighLatency = 25;
  22   let PostRAScheduler = 1;
  23
  24   // FIXME: This variable is required for incomplete model.
  25   // We haven't catered all instructions.
  26   // So, we reset the value of this variable so as to
  27   // say that the model is incomplete.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = Znver2Model in {
  32
  33 // Zen can issue micro-ops to 10 different units in one cycle.
  34 // These are
  35 //  * Four integer ALU units (ZALU0, ZALU1, ZALU2, ZALU3)
  36 //  * Three AGU units (ZAGU0, ZAGU1, ZAGU2)
  37 //  * Four FPU units (ZFPU0, ZFPU1, ZFPU2, ZFPU3)
  38 // AGUs feed load store queues @two loads and 1 store per cycle.
  39
  40 // Four ALU units are defined below
  41 def Zn2ALU0 : ProcResource<1>;
  42 def Zn2ALU1 : ProcResource<1>;
  43 def Zn2ALU2 : ProcResource<1>;
  44 def Zn2ALU3 : ProcResource<1>;
  45
  46 // Three AGU units are defined below
  47 def Zn2AGU0 : ProcResource<1>;
  48 def Zn2AGU1 : ProcResource<1>;
  49 def Zn2AGU2 : ProcResource<1>;
  50
  51 // Four FPU units are defined below
  52 def Zn2FPU0 : ProcResource<1>;
  53 def Zn2FPU1 : ProcResource<1>;
  54 def Zn2FPU2 : ProcResource<1>;
  55 def Zn2FPU3 : ProcResource<1>;
  56
  57 // FPU grouping
  58 def Zn2FPU013  : ProcResGroup<[Zn2FPU0, Zn2FPU1, Zn2FPU3]>;
  59 def Zn2FPU01   : ProcResGroup<[Zn2FPU0, Zn2FPU1]>;
  60 def Zn2FPU12   : ProcResGroup<[Zn2FPU1, Zn2FPU2]>;
  61 def Zn2FPU13   : ProcResGroup<[Zn2FPU1, Zn2FPU3]>;
  62 def Zn2FPU23   : ProcResGroup<[Zn2FPU2, Zn2FPU3]>;
  63 def Zn2FPU02   : ProcResGroup<[Zn2FPU0, Zn2FPU2]>;
  64 def Zn2FPU03   : ProcResGroup<[Zn2FPU0, Zn2FPU3]>;
  65
  66 // Below are the grouping of the units.
  67 // Micro-ops to be issued to multiple units are tackled this way.
  68
  69 // ALU grouping
  70 // Zn2ALU03 - 0,3 grouping
  71 def Zn2ALU03: ProcResGroup<[Zn2ALU0, Zn2ALU3]>;
  72
  73 // 64 Entry (16x4 entries) Int Scheduler
  74 def Zn2ALU : ProcResGroup<[Zn2ALU0, Zn2ALU1, Zn2ALU2, Zn2ALU3]> {
  75   let BufferSize=64;
  76 }
  77
  78 // 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations
  79 // but are relevant for some instructions
  80 def Zn2AGU : ProcResGroup<[Zn2AGU0, Zn2AGU1, Zn2AGU2]> {
  81   let BufferSize=28;
  82 }
  83
  84 // Integer Multiplication issued on ALU1.
  85 def Zn2Multiplier : ProcResource<1>;
  86
  87 // Integer division issued on ALU2.
  88 def Zn2Divider : ProcResource<1>;
  89
  90 // 4 Cycles load-to use Latency is captured
  91 def : ReadAdvance<ReadAfterLd, 4>;
  92
  93 // 7 Cycles vector load-to use Latency is captured
  94 def : ReadAdvance<ReadAfterVecLd, 7>;
  95 def : ReadAdvance<ReadAfterVecXLd, 7>;
  96 def : ReadAdvance<ReadAfterVecYLd, 7>;
  97
  98 def : ReadAdvance<ReadInt2Fpu, 0>;
  99
 100 // The Integer PRF for Zen is 168 entries, and it holds the architectural and
 101 // speculative version of the 64-bit integer registers.
 102 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
 103 def Zn2IntegerPRF : RegisterFile<168, [GR64, CCR]>;
 104
 105 // 36 Entry (9x4 entries) floating-point Scheduler
 106 def Zn2FPU     : ProcResGroup<[Zn2FPU0, Zn2FPU1, Zn2FPU2, Zn2FPU3]> {
 107   let BufferSize=36;
 108 }
 109
 110 // The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit
 111 // registers. Operations on 256-bit data types are cracked into two COPs.
 112 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
 113 def Zn2FpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
 114
 115 // The unit can track up to 192 macro ops in-flight.
 116 // The retire unit handles in-order commit of up to 8 macro ops per cycle.
 117 // Reference: "Software Optimization Guide for AMD Family 17h Processors"
 118 // To be noted, the retire unit is shared between integer and FP ops.
 119 // In SMT mode it is 96 entry per thread. But, we do not use the conservative
 120 // value here because there is currently no way to fully mode the SMT mode,
 121 // so there is no point in trying.
 122 def Zn2RCU : RetireControlUnit<192, 8>;
 123
 124 // (a folded load is an instruction that loads and does some operation)
 125 // Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops
 126 // Instructions with folded loads are usually micro-fused, so they only appear
 127 // as two micro-ops.
 128 //      a. load and
 129 //      b. addpd
 130 // This multiclass is for folded loads for integer units.
 131 multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
 132                           list<ProcResourceKind> ExePorts,
 133                           int Lat, list<int> Res = [], int UOps = 1,
 134                           int LoadLat = 4, int LoadUOps = 1> {
 135   // Register variant takes 1-cycle on Execution Port.
 136   def : WriteRes<SchedRW, ExePorts> {
 137     let Latency = Lat;
 138     let ResourceCycles = Res;
 139     let NumMicroOps = UOps;
 140   }
 141
 142   // Memory variant also uses a cycle on Zn2AGU
 143   // adds LoadLat cycles to the latency (default = 4).
 144   def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
 145     let Latency = !add(Lat, LoadLat);
 146     let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
 147     let NumMicroOps = !add(UOps, LoadUOps);
 148   }
 149 }
 150
 151 // This multiclass is for folded loads for floating point units.
 152 multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
 153                           list<ProcResourceKind> ExePorts,
 154                           int Lat, list<int> Res = [], int UOps = 1,
 155                           int LoadLat = 7, int LoadUOps = 0> {
 156   // Register variant takes 1-cycle on Execution Port.
 157   def : WriteRes<SchedRW, ExePorts> {
 158     let Latency = Lat;
 159     let ResourceCycles = Res;
 160     let NumMicroOps = UOps;
 161   }
 162
 163   // Memory variant also uses a cycle on Zn2AGU
 164   // adds LoadLat cycles to the latency (default = 7).
 165   def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
 166     let Latency = !add(Lat, LoadLat);
 167     let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
 168     let NumMicroOps = !add(UOps, LoadUOps);
 169   }
 170 }
 171
 172 // WriteRMW is set for instructions with Memory write
 173 // operation in codegen
 174 def : WriteRes<WriteRMW, [Zn2AGU]>;
 175
 176 def : WriteRes<WriteStore,   [Zn2AGU]>;
 177 def : WriteRes<WriteStoreNT, [Zn2AGU]>;
 178 def : WriteRes<WriteMove,    [Zn2ALU]>;
 179 def : WriteRes<WriteLoad,    [Zn2AGU]> { let Latency = 8; }
 180
 181 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
 182 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
 183 def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 8; let NumMicroOps = 0; }
 184
 185 def : WriteRes<WriteZero,  []>;
 186 def : WriteRes<WriteLEA, [Zn2ALU]>;
 187 defm : Zn2WriteResPair<WriteALU,   [Zn2ALU], 1>;
 188 defm : Zn2WriteResPair<WriteADC,   [Zn2ALU], 1>;
 189
 190 defm : Zn2WriteResPair<WriteIMul8,     [Zn2ALU1, Zn2Multiplier], 4>;
 191
 192 defm : X86WriteRes<WriteBSWAP32, [Zn2ALU], 1, [4], 1>;
 193 defm : X86WriteRes<WriteBSWAP64, [Zn2ALU], 1, [4], 1>;
 194 defm : X86WriteRes<WriteCMPXCHG, [Zn2ALU], 3, [1], 1>;
 195 defm : X86WriteRes<WriteCMPXCHGRMW,[Zn2ALU,Zn2AGU], 8, [1,1], 5>;
 196 defm : X86WriteRes<WriteXCHG, [Zn2ALU], 1, [2], 2>;
 197
 198 defm : Zn2WriteResPair<WriteShift, [Zn2ALU], 1>;
 199 defm : Zn2WriteResPair<WriteShiftCL,  [Zn2ALU], 1>;
 200 defm : Zn2WriteResPair<WriteRotate,   [Zn2ALU], 1>;
 201 defm : Zn2WriteResPair<WriteRotateCL, [Zn2ALU], 1>;
 202
 203 defm : X86WriteRes<WriteSHDrri, [Zn2ALU], 1, [1], 1>;
 204 defm : X86WriteResUnsupported<WriteSHDrrcl>;
 205 defm : X86WriteResUnsupported<WriteSHDmri>;
 206 defm : X86WriteResUnsupported<WriteSHDmrcl>;
 207
 208 defm : Zn2WriteResPair<WriteJump,  [Zn2ALU], 1>;
 209 defm : Zn2WriteResFpuPair<WriteCRC32, [Zn2FPU0], 3>;
 210
 211 defm : Zn2WriteResPair<WriteCMOV,   [Zn2ALU], 1>;
 212 def  : WriteRes<WriteSETCC,  [Zn2ALU]>;
 213 def  : WriteRes<WriteSETCCStore,  [Zn2ALU, Zn2AGU]>;
 214 defm : X86WriteRes<WriteLAHFSAHF, [Zn2ALU], 2, [1], 2>;
 215
 216 defm : X86WriteRes<WriteBitTest,         [Zn2ALU], 1, [1], 1>;
 217 defm : X86WriteRes<WriteBitTestImmLd,    [Zn2ALU,Zn2AGU], 5, [1,1], 2>;
 218 defm : X86WriteRes<WriteBitTestRegLd,    [Zn2ALU,Zn2AGU], 5, [1,1], 2>;
 219 defm : X86WriteRes<WriteBitTestSet,      [Zn2ALU], 2, [1], 2>;
 220
 221 // Bit counts.
 222 defm : Zn2WriteResPair<WriteBSF, [Zn2ALU], 3>;
 223 defm : Zn2WriteResPair<WriteBSR, [Zn2ALU], 4>;
 224 defm : Zn2WriteResPair<WriteLZCNT,          [Zn2ALU], 1>;
 225 defm : Zn2WriteResPair<WriteTZCNT,          [Zn2ALU], 2>;
 226 defm : Zn2WriteResPair<WritePOPCNT,         [Zn2ALU], 1>;
 227
 228 // Treat misc copies as a move.
 229 def : InstRW<[WriteMove], (instrs COPY)>;
 230
 231 // BMI1 BEXTR, BMI2 BZHI
 232 defm : Zn2WriteResPair<WriteBEXTR, [Zn2ALU], 1>;
 233 defm : Zn2WriteResPair<WriteBZHI, [Zn2ALU], 1>;
 234
 235 // IDIV
 236 defm : Zn2WriteResPair<WriteDiv8,   [Zn2ALU2, Zn2Divider], 15, [1,15], 1>;
 237 defm : Zn2WriteResPair<WriteDiv16,  [Zn2ALU2, Zn2Divider], 17, [1,17], 2>;
 238 defm : Zn2WriteResPair<WriteDiv32,  [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
 239 defm : Zn2WriteResPair<WriteDiv64,  [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
 240 defm : Zn2WriteResPair<WriteIDiv8,  [Zn2ALU2, Zn2Divider], 15, [1,15], 1>;
 241 defm : Zn2WriteResPair<WriteIDiv16, [Zn2ALU2, Zn2Divider], 17, [1,17], 2>;
 242 defm : Zn2WriteResPair<WriteIDiv32, [Zn2ALU2, Zn2Divider], 25, [1,25], 2>;
 243 defm : Zn2WriteResPair<WriteIDiv64, [Zn2ALU2, Zn2Divider], 41, [1,41], 2>;
 244
 245 // IMULH
 246 def  : WriteRes<WriteIMulH, [Zn2Multiplier]>{
 247   let Latency = 3;
 248   let NumMicroOps = 0;
 249 }
 250
 251 // Floating point operations
 252 defm : X86WriteRes<WriteFLoad,         [Zn2AGU], 8, [1], 1>;
 253 defm : X86WriteRes<WriteFLoadX,        [Zn2AGU], 8, [1], 1>;
 254 defm : X86WriteRes<WriteFLoadY,        [Zn2AGU], 8, [1], 1>;
 255 defm : X86WriteRes<WriteFMaskedLoad,   [Zn2AGU,Zn2FPU01], 8, [1,1], 1>;
 256 defm : X86WriteRes<WriteFMaskedLoadY,  [Zn2AGU,Zn2FPU01], 8, [1,1], 2>;
 257 defm : X86WriteRes<WriteFMaskedStore32,  [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
 258 defm : X86WriteRes<WriteFMaskedStore32Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
 259 defm : X86WriteRes<WriteFMaskedStore64,  [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
 260 defm : X86WriteRes<WriteFMaskedStore64Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
 261
 262 defm : X86WriteRes<WriteFStore,        [Zn2AGU], 1, [1], 1>;
 263 defm : X86WriteRes<WriteFStoreX,       [Zn2AGU], 1, [1], 1>;
 264 defm : X86WriteRes<WriteFStoreY,       [Zn2AGU], 1, [1], 1>;
 265 defm : X86WriteRes<WriteFStoreNT,      [Zn2AGU,Zn2FPU2], 8, [1,1], 1>;
 266 defm : X86WriteRes<WriteFStoreNTX,     [Zn2AGU], 1, [1], 1>;
 267 defm : X86WriteRes<WriteFStoreNTY,     [Zn2AGU], 1, [1], 1>;
 268 defm : X86WriteRes<WriteFMove,         [Zn2FPU], 1, [1], 1>;
 269 defm : X86WriteRes<WriteFMoveX,        [Zn2FPU], 1, [1], 1>;
 270 defm : X86WriteRes<WriteFMoveY,        [Zn2FPU], 1, [1], 1>;
 271
 272 defm : Zn2WriteResFpuPair<WriteFAdd,      [Zn2FPU0],  3>;
 273 defm : Zn2WriteResFpuPair<WriteFAddX,     [Zn2FPU0],  3>;
 274 defm : Zn2WriteResFpuPair<WriteFAddY,     [Zn2FPU0],  3>;
 275 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 276 defm : Zn2WriteResFpuPair<WriteFAdd64,    [Zn2FPU0],  3>;
 277 defm : Zn2WriteResFpuPair<WriteFAdd64X,   [Zn2FPU0],  3>;
 278 defm : Zn2WriteResFpuPair<WriteFAdd64Y,   [Zn2FPU0],  3>;
 279 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 280 defm : Zn2WriteResFpuPair<WriteFCmp,      [Zn2FPU0],  1>;
 281 defm : Zn2WriteResFpuPair<WriteFCmpX,     [Zn2FPU0],  1>;
 282 defm : Zn2WriteResFpuPair<WriteFCmpY,     [Zn2FPU0],  1>;
 283 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 284 defm : Zn2WriteResFpuPair<WriteFCmp64,    [Zn2FPU0],  1>;
 285 defm : Zn2WriteResFpuPair<WriteFCmp64X,   [Zn2FPU0],  1>;
 286 defm : Zn2WriteResFpuPair<WriteFCmp64Y,   [Zn2FPU0],  1>;
 287 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 288 defm : Zn2WriteResFpuPair<WriteFCom,      [Zn2FPU0],  3>;
 289 defm : Zn2WriteResFpuPair<WriteFComX,     [Zn2FPU0],  3>;
 290 defm : Zn2WriteResFpuPair<WriteFBlend,    [Zn2FPU01], 1>;
 291 defm : Zn2WriteResFpuPair<WriteFBlendY,   [Zn2FPU01], 1>;
 292 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 293 defm : Zn2WriteResFpuPair<WriteFVarBlend, [Zn2FPU01], 1>;
 294 defm : Zn2WriteResFpuPair<WriteFVarBlendY,[Zn2FPU01], 1>;
 295 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 296 defm : Zn2WriteResFpuPair<WriteVarBlend,  [Zn2FPU0],  1>;
 297 defm : Zn2WriteResFpuPair<WriteVarBlendY, [Zn2FPU0],  1>;
 298 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 299 defm : Zn2WriteResFpuPair<WriteCvtSS2I,   [Zn2FPU3],  5>;
 300 defm : Zn2WriteResFpuPair<WriteCvtPS2I,   [Zn2FPU3],  5>;
 301 defm : Zn2WriteResFpuPair<WriteCvtPS2IY,  [Zn2FPU3],  5>;
 302 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 303 defm : Zn2WriteResFpuPair<WriteCvtSD2I,   [Zn2FPU3],  5>;
 304 defm : Zn2WriteResFpuPair<WriteCvtPD2I,   [Zn2FPU3],  5>;
 305 defm : Zn2WriteResFpuPair<WriteCvtPD2IY,  [Zn2FPU3],  5>;
 306 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 307 defm : Zn2WriteResFpuPair<WriteCvtI2SS,   [Zn2FPU3],  5>;
 308 defm : Zn2WriteResFpuPair<WriteCvtI2PS,   [Zn2FPU3],  5>;
 309 defm : Zn2WriteResFpuPair<WriteCvtI2PSY,  [Zn2FPU3],  5>;
 310 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 311 defm : Zn2WriteResFpuPair<WriteCvtI2SD,   [Zn2FPU3],  5>;
 312 defm : Zn2WriteResFpuPair<WriteCvtI2PD,   [Zn2FPU3],  5>;
 313 defm : Zn2WriteResFpuPair<WriteCvtI2PDY,  [Zn2FPU3],  5>;
 314 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 315 defm : Zn2WriteResFpuPair<WriteFDiv,      [Zn2FPU3], 15>;
 316 defm : Zn2WriteResFpuPair<WriteFDivX,     [Zn2FPU3], 15>;
 317 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 318 defm : Zn2WriteResFpuPair<WriteFDiv64,    [Zn2FPU3], 15>;
 319 defm : Zn2WriteResFpuPair<WriteFDiv64X,   [Zn2FPU3], 15>;
 320 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 321 defm : Zn2WriteResFpuPair<WriteFSign,     [Zn2FPU3],  2>;
 322 defm : Zn2WriteResFpuPair<WriteFRnd,      [Zn2FPU3],  3, [1], 1, 7, 0>;
 323 defm : Zn2WriteResFpuPair<WriteFRndY,     [Zn2FPU3],  3, [1], 1, 7, 0>;
 324 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 325 defm : Zn2WriteResFpuPair<WriteFLogic,    [Zn2FPU],   1>;
 326 defm : Zn2WriteResFpuPair<WriteFLogicY,   [Zn2FPU],   1>;
 327 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 328 defm : Zn2WriteResFpuPair<WriteFTest,     [Zn2FPU],   1>;
 329 defm : Zn2WriteResFpuPair<WriteFTestY,    [Zn2FPU],   1>;
 330 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 331 defm : Zn2WriteResFpuPair<WriteFShuffle,  [Zn2FPU12], 1>;
 332 defm : Zn2WriteResFpuPair<WriteFShuffleY, [Zn2FPU12], 1>;
 333 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 334 defm : Zn2WriteResFpuPair<WriteFVarShuffle, [Zn2FPU12], 3>;
 335 defm : Zn2WriteResFpuPair<WriteFVarShuffleY,[Zn2FPU12], 3>;
 336 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 337 defm : Zn2WriteResFpuPair<WriteFMul,      [Zn2FPU01], 3, [1], 1, 7, 1>;
 338 defm : Zn2WriteResFpuPair<WriteFMulX,     [Zn2FPU01], 3, [1], 1, 7, 1>;
 339 defm : Zn2WriteResFpuPair<WriteFMulY,     [Zn2FPU01], 3, [1], 1, 7, 1>;
 340 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 341 defm : Zn2WriteResFpuPair<WriteFMul64,    [Zn2FPU01], 3, [1], 1, 7, 1>;
 342 defm : Zn2WriteResFpuPair<WriteFMul64X,   [Zn2FPU01], 3, [1], 1, 7, 1>;
 343 defm : Zn2WriteResFpuPair<WriteFMul64Y,   [Zn2FPU01], 3, [1], 1, 7, 1>;
 344 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 345 defm : Zn2WriteResFpuPair<WriteFMA,       [Zn2FPU03], 5>;
 346 defm : Zn2WriteResFpuPair<WriteFMAX,      [Zn2FPU03], 5>;
 347 defm : Zn2WriteResFpuPair<WriteFMAY,      [Zn2FPU03], 5>;
 348 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 349 defm : Zn2WriteResFpuPair<WriteFRcp,      [Zn2FPU01], 5>;
 350 defm : Zn2WriteResFpuPair<WriteFRcpX,     [Zn2FPU01], 5>;
 351 defm : Zn2WriteResFpuPair<WriteFRcpY,     [Zn2FPU01], 5, [1], 1, 7, 2>;
 352 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 353 defm : Zn2WriteResFpuPair<WriteFRsqrtX,   [Zn2FPU01], 5, [1], 1, 7, 1>;
 354 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 355 defm : Zn2WriteResFpuPair<WriteFSqrt,     [Zn2FPU3], 20, [20]>;
 356 defm : Zn2WriteResFpuPair<WriteFSqrtX,    [Zn2FPU3], 20, [20]>;
 357 defm : Zn2WriteResFpuPair<WriteFSqrtY,    [Zn2FPU3], 28, [28], 1, 7, 1>;
 358 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 359 defm : Zn2WriteResFpuPair<WriteFSqrt64,   [Zn2FPU3], 20, [20]>;
 360 defm : Zn2WriteResFpuPair<WriteFSqrt64X,  [Zn2FPU3], 20, [20]>;
 361 defm : Zn2WriteResFpuPair<WriteFSqrt64Y,  [Zn2FPU3], 20, [20], 1, 7, 1>;
 362 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 363 defm : Zn2WriteResFpuPair<WriteFSqrt80,   [Zn2FPU3], 20, [20]>;
 364
 365 // Vector integer operations which uses FPU units
 366 defm : X86WriteRes<WriteVecLoad,         [Zn2AGU], 8, [1], 1>;
 367 defm : X86WriteRes<WriteVecLoadX,        [Zn2AGU], 8, [1], 1>;
 368 defm : X86WriteRes<WriteVecLoadY,        [Zn2AGU], 8, [1], 1>;
 369 defm : X86WriteRes<WriteVecLoadNT,       [Zn2AGU], 8, [1], 1>;
 370 defm : X86WriteRes<WriteVecLoadNTY,      [Zn2AGU], 8, [1], 1>;
 371 defm : X86WriteRes<WriteVecMaskedLoad,   [Zn2AGU,Zn2FPU01], 8, [1,2], 2>;
 372 defm : X86WriteRes<WriteVecMaskedLoadY,  [Zn2AGU,Zn2FPU01], 8, [1,2], 2>;
 373 defm : X86WriteRes<WriteVecStore,        [Zn2AGU], 1, [1], 1>;
 374 defm : X86WriteRes<WriteVecStoreX,       [Zn2AGU], 1, [1], 1>;
 375 defm : X86WriteRes<WriteVecStoreY,       [Zn2AGU], 1, [1], 1>;
 376 defm : X86WriteRes<WriteVecStoreNT,      [Zn2AGU], 1, [1], 1>;
 377 defm : X86WriteRes<WriteVecStoreNTY,     [Zn2AGU], 1, [1], 1>;
 378 defm : X86WriteRes<WriteVecMaskedStore32,  [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
 379 defm : X86WriteRes<WriteVecMaskedStore32Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
 380 defm : X86WriteRes<WriteVecMaskedStore64,  [Zn2AGU,Zn2FPU01], 4, [1,1], 1>;
 381 defm : X86WriteRes<WriteVecMaskedStore64Y, [Zn2AGU,Zn2FPU01], 5, [1,2], 2>;
 382 defm : X86WriteRes<WriteVecMove,         [Zn2FPU], 1, [1], 1>;
 383 defm : X86WriteRes<WriteVecMoveX,        [Zn2FPU], 1, [1], 1>;
 384 defm : X86WriteRes<WriteVecMoveY,        [Zn2FPU], 2, [1], 2>;
 385 defm : X86WriteRes<WriteVecMoveToGpr,    [Zn2FPU2], 2, [1], 1>;
 386 defm : X86WriteRes<WriteVecMoveFromGpr,  [Zn2FPU2], 3, [1], 1>;
 387 defm : X86WriteRes<WriteEMMS,            [Zn2FPU], 2, [1], 1>;
 388
 389 defm : Zn2WriteResFpuPair<WriteVecShift,   [Zn2FPU],   1>;
 390 defm : Zn2WriteResFpuPair<WriteVecShiftX,  [Zn2FPU2],  1>;
 391 defm : Zn2WriteResFpuPair<WriteVecShiftY,  [Zn2FPU2],  1>;
 392 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 393 defm : Zn2WriteResFpuPair<WriteVecShiftImm,  [Zn2FPU], 1>;
 394 defm : Zn2WriteResFpuPair<WriteVecShiftImmX, [Zn2FPU], 1>;
 395 defm : Zn2WriteResFpuPair<WriteVecShiftImmY, [Zn2FPU], 1>;
 396 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 397 defm : Zn2WriteResFpuPair<WriteVecLogic,   [Zn2FPU],   1>;
 398 defm : Zn2WriteResFpuPair<WriteVecLogicX,  [Zn2FPU],   1>;
 399 defm : Zn2WriteResFpuPair<WriteVecLogicY,  [Zn2FPU],   1>;
 400 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 401 defm : Zn2WriteResFpuPair<WriteVecTest,    [Zn2FPU12], 1, [2], 1, 7, 1>;
 402 defm : Zn2WriteResFpuPair<WriteVecTestY,   [Zn2FPU12], 1, [2], 1, 7, 1>;
 403 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 404 defm : Zn2WriteResFpuPair<WriteVecALU,     [Zn2FPU],   1>;
 405 defm : Zn2WriteResFpuPair<WriteVecALUX,    [Zn2FPU],   1>;
 406 defm : Zn2WriteResFpuPair<WriteVecALUY,    [Zn2FPU],   1>;
 407 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 408 defm : Zn2WriteResFpuPair<WriteVecIMul,    [Zn2FPU0],  4>;
 409 defm : Zn2WriteResFpuPair<WriteVecIMulX,   [Zn2FPU0],  4>;
 410 defm : Zn2WriteResFpuPair<WriteVecIMulY,   [Zn2FPU0],  4>;
 411 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 412 defm : Zn2WriteResFpuPair<WritePMULLD,     [Zn2FPU0],  4, [1], 1, 7, 1>;
 413 defm : Zn2WriteResFpuPair<WritePMULLDY,    [Zn2FPU0],  4, [1], 1, 7, 1>;
 414 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 415 defm : Zn2WriteResFpuPair<WriteShuffle,    [Zn2FPU],   1>;
 416 defm : Zn2WriteResFpuPair<WriteShuffleX,   [Zn2FPU],   1>;
 417 defm : Zn2WriteResFpuPair<WriteShuffleY,   [Zn2FPU],   1>;
 418 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 419 defm : Zn2WriteResFpuPair<WriteVarShuffle, [Zn2FPU],   1>;
 420 defm : Zn2WriteResFpuPair<WriteVarShuffleX,[Zn2FPU],   1>;
 421 defm : Zn2WriteResFpuPair<WriteVarShuffleY,[Zn2FPU],   1>;
 422 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 423 defm : Zn2WriteResFpuPair<WriteBlend,      [Zn2FPU01], 1>;
 424 defm : Zn2WriteResFpuPair<WriteBlendY,     [Zn2FPU01], 1>;
 425 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 426 defm : Zn2WriteResFpuPair<WriteShuffle256, [Zn2FPU],   2>;
 427 defm : Zn2WriteResFpuPair<WriteVPMOV256,   [Zn2FPU12],  4, [1], 2, 4>;
 428 defm : Zn2WriteResFpuPair<WriteVarShuffle256, [Zn2FPU],   2>;
 429 defm : Zn2WriteResFpuPair<WritePSADBW,     [Zn2FPU0],  3>;
 430 defm : Zn2WriteResFpuPair<WritePSADBWX,    [Zn2FPU0],  3>;
 431 defm : Zn2WriteResFpuPair<WritePSADBWY,    [Zn2FPU0],  3>;
 432 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 433 defm : Zn2WriteResFpuPair<WritePHMINPOS,   [Zn2FPU0],  4>;
 434
 435 // Vector Shift Operations
 436 defm : Zn2WriteResFpuPair<WriteVarVecShift,  [Zn2FPU12], 3>;
 437 defm : Zn2WriteResFpuPair<WriteVarVecShiftY, [Zn2FPU12], 3>;
 438 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 439
 440 // Vector insert/extract operations.
 441 defm : Zn2WriteResFpuPair<WriteVecInsert,   [Zn2FPU],   1>;
 442
 443 def : WriteRes<WriteVecExtract, [Zn2FPU12, Zn2FPU2]> {
 444   let Latency = 2;
 445   let ResourceCycles = [1, 2];
 446 }
 447 def : WriteRes<WriteVecExtractSt, [Zn2AGU, Zn2FPU12, Zn2FPU2]> {
 448   let Latency = 5;
 449   let NumMicroOps = 2;
 450   let ResourceCycles = [1, 2, 3];
 451 }
 452
 453 // MOVMSK Instructions.
 454 def : WriteRes<WriteFMOVMSK, [Zn2FPU2]>;
 455 def : WriteRes<WriteMMXMOVMSK, [Zn2FPU2]>;
 456 def : WriteRes<WriteVecMOVMSK, [Zn2FPU2]>;
 457
 458 def : WriteRes<WriteVecMOVMSKY, [Zn2FPU2]> {
 459   let NumMicroOps = 2;
 460   let Latency = 2;
 461   let ResourceCycles = [2];
 462 }
 463
 464 // AES Instructions.
 465 defm : Zn2WriteResFpuPair<WriteAESDecEnc, [Zn2FPU01], 4>;
 466 defm : Zn2WriteResFpuPair<WriteAESIMC,    [Zn2FPU01], 4>;
 467 defm : Zn2WriteResFpuPair<WriteAESKeyGen, [Zn2FPU01], 4>;
 468
 469 def : WriteRes<WriteFence,  [Zn2AGU]>;
 470 def : WriteRes<WriteNop, []>;
 471
 472 // Following instructions with latency=100 are microcoded.
 473 // We set long latency so as to block the entire pipeline.
 474 defm : Zn2WriteResFpuPair<WriteFShuffle256, [Zn2FPU], 100>;
 475 defm : Zn2WriteResFpuPair<WriteFVarShuffle256, [Zn2FPU], 100>;
 476
 477 // Microcoded Instructions
 478 def Zn2WriteMicrocoded : SchedWriteRes<[]> {
 479   let Latency = 100;
 480 }
 481 defm : Zn2WriteResPair<WriteDPPS, [], 15>;
 482 defm : Zn2WriteResPair<WriteFHAdd, [], 7>;
 483 defm : Zn2WriteResPair<WriteFHAddY, [], 7>;
 484 defm : Zn2WriteResPair<WritePHAdd, [], 3>;
 485 defm : Zn2WriteResPair<WritePHAddX, [], 3>;
 486 defm : Zn2WriteResPair<WritePHAddY, [], 3>;
 487
 488 def : SchedAlias<WriteMicrocoded, Zn2WriteMicrocoded>;
 489 def : SchedAlias<WriteFCMOV, Zn2WriteMicrocoded>;
 490 def : SchedAlias<WriteSystem, Zn2WriteMicrocoded>;
 491 def : SchedAlias<WriteMPSAD, Zn2WriteMicrocoded>;
 492 def : SchedAlias<WriteMPSADY, Zn2WriteMicrocoded>;
 493 def : SchedAlias<WriteMPSADLd, Zn2WriteMicrocoded>;
 494 def : SchedAlias<WriteMPSADYLd, Zn2WriteMicrocoded>;
 495 def : SchedAlias<WriteCLMul, Zn2WriteMicrocoded>;
 496 def : SchedAlias<WriteCLMulLd, Zn2WriteMicrocoded>;
 497 def : SchedAlias<WritePCmpIStrM, Zn2WriteMicrocoded>;
 498 def : SchedAlias<WritePCmpIStrMLd, Zn2WriteMicrocoded>;
 499 def : SchedAlias<WritePCmpEStrI, Zn2WriteMicrocoded>;
 500 def : SchedAlias<WritePCmpEStrILd, Zn2WriteMicrocoded>;
 501 def : SchedAlias<WritePCmpEStrM, Zn2WriteMicrocoded>;
 502 def : SchedAlias<WritePCmpEStrMLd, Zn2WriteMicrocoded>;
 503 def : SchedAlias<WritePCmpIStrI, Zn2WriteMicrocoded>;
 504 def : SchedAlias<WritePCmpIStrILd, Zn2WriteMicrocoded>;
 505 def : SchedAlias<WriteLDMXCSR, Zn2WriteMicrocoded>;
 506 def : SchedAlias<WriteSTMXCSR, Zn2WriteMicrocoded>;
 507
 508 //=== Regex based InstRW ===//
 509 // Notation:
 510 // - r: register.
 511 // - m = memory.
 512 // - i = immediate
 513 // - mm: 64 bit mmx register.
 514 // - x = 128 bit xmm register.
 515 // - (x)mm = mmx or xmm register.
 516 // - y = 256 bit ymm register.
 517 // - v = any vector register.
 518
 519 //=== Integer Instructions ===//
 520 //-- Move instructions --//
 521 // MOV.
 522 // r16,m.
 523 def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>;
 524
 525 // MOVSX, MOVZX.
 526 // r,m.
 527 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
 528
 529 // XCHG.
 530 // r,r.
 531 def Zn2WriteXCHG : SchedWriteRes<[Zn2ALU]> {
 532   let NumMicroOps = 2;
 533 }
 534
 535 def : InstRW<[Zn2WriteXCHG], (instregex "^XCHG(8|16|32|64)rr", "^XCHG(16|32|64)ar")>;
 536
 537 // r,m.
 538 def Zn2WriteXCHGrm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 539   let Latency = 5;
 540   let NumMicroOps = 2;
 541 }
 542 def : InstRW<[Zn2WriteXCHGrm, ReadAfterLd], (instregex "^XCHG(8|16|32|64)rm")>;
 543
 544 def : InstRW<[WriteMicrocoded], (instrs XLAT)>;
 545
 546 // POP16.
 547 // r.
 548 def Zn2WritePop16r : SchedWriteRes<[Zn2AGU]>{
 549   let Latency = 5;
 550   let NumMicroOps = 2;
 551 }
 552 def : InstRW<[Zn2WritePop16r], (instregex "POP16rmm")>;
 553 def : InstRW<[WriteMicrocoded], (instregex "POPF(16|32)")>;
 554 def : InstRW<[WriteMicrocoded], (instregex "POPA(16|32)")>;
 555
 556
 557 // PUSH.
 558 // r. Has default values.
 559 // m.
 560 def Zn2WritePUSH : SchedWriteRes<[Zn2AGU]>{
 561   let Latency = 4;
 562 }
 563 def : InstRW<[Zn2WritePUSH], (instregex "PUSH(16|32)rmm")>;
 564
 565 //PUSHF
 566 def : InstRW<[WriteMicrocoded], (instregex "PUSHF(16|32)")>;
 567
 568 // PUSHA.
 569 def Zn2WritePushA : SchedWriteRes<[Zn2AGU]> {
 570   let Latency = 8;
 571 }
 572 def : InstRW<[Zn2WritePushA], (instregex "PUSHA(16|32)")>;
 573
 574 //LAHF
 575 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
 576
 577 // MOVBE.
 578 // r,m.
 579 def Zn2WriteMOVBE : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 580   let Latency = 5;
 581 }
 582 def : InstRW<[Zn2WriteMOVBE, ReadAfterLd], (instregex "MOVBE(16|32|64)rm")>;
 583
 584 // m16,r16.
 585 def : InstRW<[Zn2WriteMOVBE], (instregex "MOVBE(16|32|64)mr")>;
 586
 587 //-- Arithmetic instructions --//
 588
 589 // ADD SUB.
 590 // m,r/i.
 591 def : InstRW<[WriteALULd], (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
 592                           "(ADD|SUB)(8|16|32|64)mi8",
 593                           "(ADD|SUB)64mi32")>;
 594
 595 // ADC SBB.
 596 // m,r/i.
 597 def : InstRW<[WriteALULd],
 598              (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
 599               "(ADC|SBB)(16|32|64)mi8",
 600               "(ADC|SBB)64mi32")>;
 601
 602 // INC DEC NOT NEG.
 603 // m.
 604 def : InstRW<[WriteALULd],
 605              (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>;
 606
 607 // MUL IMUL.
 608 // r16.
 609 def Zn2WriteMul16 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 610   let Latency = 3;
 611 }
 612 def Zn2WriteMul16Imm : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 613   let Latency = 4;
 614 }
 615 def : SchedAlias<WriteIMul16, Zn2WriteMul16>;
 616 def : SchedAlias<WriteIMul16Imm, Zn2WriteMul16Imm>;
 617 def : SchedAlias<WriteIMul16Reg, Zn2WriteMul16>;
 618
 619 // m16.
 620 def Zn2WriteMul16Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 621   let Latency = 7;
 622 }
 623 def : SchedAlias<WriteIMul16Ld, Zn2WriteMul16Ld>;
 624 def : SchedAlias<WriteIMul16ImmLd, Zn2WriteMul16Ld>;
 625 def : SchedAlias<WriteIMul16RegLd, Zn2WriteMul16Ld>;
 626
 627 // r32.
 628 def Zn2WriteMul32 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 629   let Latency = 3;
 630 }
 631 def : SchedAlias<WriteIMul32, Zn2WriteMul32>;
 632 def : SchedAlias<WriteIMul32Imm, Zn2WriteMul32>;
 633 def : SchedAlias<WriteIMul32Reg, Zn2WriteMul32>;
 634
 635 // m32.
 636 def Zn2WriteMul32Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 637   let Latency = 7;
 638 }
 639 def : SchedAlias<WriteIMul32Ld, Zn2WriteMul32Ld>;
 640 def : SchedAlias<WriteIMul32ImmLd, Zn2WriteMul32Ld>;
 641 def : SchedAlias<WriteIMul32RegLd, Zn2WriteMul32Ld>;
 642
 643 // r64.
 644 def Zn2WriteMul64 : SchedWriteRes<[Zn2ALU1, Zn2Multiplier]> {
 645   let Latency = 4;
 646   let NumMicroOps = 2;
 647 }
 648 def : SchedAlias<WriteIMul64, Zn2WriteMul64>;
 649 def : SchedAlias<WriteIMul64Imm, Zn2WriteMul64>;
 650 def : SchedAlias<WriteIMul64Reg, Zn2WriteMul64>;
 651
 652 // m64.
 653 def Zn2WriteMul64Ld : SchedWriteRes<[Zn2AGU, Zn2ALU1, Zn2Multiplier]> {
 654   let Latency = 8;
 655   let NumMicroOps = 2;
 656 }
 657 def : SchedAlias<WriteIMul64Ld, Zn2WriteMul64Ld>;
 658 def : SchedAlias<WriteIMul64ImmLd, Zn2WriteMul64Ld>;
 659 def : SchedAlias<WriteIMul64RegLd, Zn2WriteMul64Ld>;
 660
 661 // MULX.
 662 // Numbers are based on the AMD SOG for Family 17h - Instruction Latencies.
 663 defm : Zn2WriteResPair<WriteMULX32, [Zn2ALU1, Zn2Multiplier], 3, [1, 1], 1, 4, 0>;
 664 defm : Zn2WriteResPair<WriteMULX64, [Zn2ALU1, Zn2Multiplier], 3, [1, 1], 1, 4, 0>;
 665
 666 //-- Control transfer instructions --//
 667
 668 // J(E|R)CXZ.
 669 def Zn2WriteJCXZ : SchedWriteRes<[Zn2ALU03]>;
 670 def : InstRW<[Zn2WriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
 671
 672 // INTO
 673 def : InstRW<[WriteMicrocoded], (instrs INTO)>;
 674
 675 // LOOP.
 676 def Zn2WriteLOOP : SchedWriteRes<[Zn2ALU03]>;
 677 def : InstRW<[Zn2WriteLOOP], (instrs LOOP)>;
 678
 679 // LOOP(N)E, LOOP(N)Z
 680 def Zn2WriteLOOPE : SchedWriteRes<[Zn2ALU03]>;
 681 def : InstRW<[Zn2WriteLOOPE], (instrs LOOPE, LOOPNE)>;
 682
 683 // CALL.
 684 // r.
 685 def Zn2WriteCALLr : SchedWriteRes<[Zn2AGU, Zn2ALU03]>;
 686 def : InstRW<[Zn2WriteCALLr], (instregex "CALL(16|32)r")>;
 687
 688 def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
 689
 690 // RET.
 691 def Zn2WriteRET : SchedWriteRes<[Zn2ALU03]> {
 692   let NumMicroOps = 2;
 693 }
 694 def : InstRW<[Zn2WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
 695                             "IRET(16|32|64)")>;
 696
 697 //-- Logic instructions --//
 698
 699 // AND OR XOR.
 700 // m,r/i.
 701 def : InstRW<[WriteALULd],
 702              (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
 703               "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
 704
 705 // Define ALU latency variants
 706 def Zn2WriteALULat2 : SchedWriteRes<[Zn2ALU]> {
 707   let Latency = 2;
 708 }
 709 def Zn2WriteALULat2Ld : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 710   let Latency = 6;
 711 }
 712
 713 // BT.
 714 // m,i.
 715 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
 716
 717 // BTR BTS BTC.
 718 // r,r,i.
 719 def Zn2WriteBTRSC : SchedWriteRes<[Zn2ALU]> {
 720   let Latency = 2;
 721   let NumMicroOps = 2;
 722 }
 723 def : InstRW<[Zn2WriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
 724
 725 // m,r,i.
 726 def Zn2WriteBTRSCm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 727   let Latency = 6;
 728   let NumMicroOps = 2;
 729 }
 730 // m,r,i.
 731 def : SchedAlias<WriteBitTestSetImmRMW, Zn2WriteBTRSCm>;
 732 def : SchedAlias<WriteBitTestSetRegRMW, Zn2WriteBTRSCm>;
 733
 734 // BLSI BLSMSK BLSR.
 735 // r,r.
 736 def : SchedAlias<WriteBLS, Zn2WriteALULat2>;
 737 // r,m.
 738 def : SchedAlias<WriteBLSLd, Zn2WriteALULat2Ld>;
 739
 740 // CLD STD.
 741 def : InstRW<[WriteALU], (instrs STD, CLD)>;
 742
 743 // PDEP PEXT.
 744 // r,r,r.
 745 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
 746 // r,r,m.
 747 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
 748
 749 // RCR RCL.
 750 // m,i.
 751 def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(1|i|CL)")>;
 752
 753 // SHR SHL SAR.
 754 // m,i.
 755 def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
 756
 757 // SHRD SHLD.
 758 // m,r
 759 def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>;
 760
 761 // r,r,cl.
 762 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)rrCL")>;
 763
 764 // m,r,cl.
 765 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;
 766
 767 //-- Misc instructions --//
 768 // CMPXCHG8B.
 769 def Zn2WriteCMPXCHG8B : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
 770   let NumMicroOps = 18;
 771 }
 772 def : InstRW<[Zn2WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
 773
 774 def : InstRW<[WriteMicrocoded], (instrs CMPXCHG16B)>;
 775
 776 // LEAVE
 777 def Zn2WriteLEAVE : SchedWriteRes<[Zn2ALU, Zn2AGU]> {
 778   let Latency = 8;
 779   let NumMicroOps = 2;
 780 }
 781 def : InstRW<[Zn2WriteLEAVE], (instregex "LEAVE")>;
 782
 783 // PAUSE.
 784 def : InstRW<[WriteMicrocoded], (instrs PAUSE)>;
 785
 786 // RDTSC.
 787 def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>;
 788
 789 // RDPMC.
 790 def : InstRW<[WriteMicrocoded], (instrs RDPMC)>;
 791
 792 // RDRAND.
 793 def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>;
 794
 795 // XGETBV.
 796 def : InstRW<[WriteMicrocoded], (instregex "XGETBV")>;
 797
 798 //-- String instructions --//
 799 // CMPS.
 800 def : InstRW<[WriteMicrocoded], (instregex "CMPS(B|L|Q|W)")>;
 801
 802 // LODSB/W.
 803 def : InstRW<[WriteMicrocoded], (instregex "LODS(B|W)")>;
 804
 805 // LODSD/Q.
 806 def : InstRW<[WriteMicrocoded], (instregex "LODS(L|Q)")>;
 807
 808 // MOVS.
 809 def : InstRW<[WriteMicrocoded], (instregex "MOVS(B|L|Q|W)")>;
 810
 811 // SCAS.
 812 def : InstRW<[WriteMicrocoded], (instregex "SCAS(B|W|L|Q)")>;
 813
 814 // STOS
 815 def : InstRW<[WriteMicrocoded], (instregex "STOS(B|L|Q|W)")>;
 816
 817 // XADD.
 818 def Zn2XADD : SchedWriteRes<[Zn2ALU]>;
 819 def : InstRW<[Zn2XADD], (instregex "XADD(8|16|32|64)rr")>;
 820 def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>;
 821
 822 //=== Floating Point x87 Instructions ===//
 823 //-- Move instructions --//
 824
 825 def Zn2WriteFLDr : SchedWriteRes<[Zn2FPU13]> ;
 826
 827 def Zn2WriteSTr: SchedWriteRes<[Zn2FPU23]> {
 828   let Latency = 5;
 829   let NumMicroOps = 2;
 830 }
 831
 832 // LD_F.
 833 // r.
 834 def : InstRW<[Zn2WriteFLDr], (instregex "LD_Frr")>;
 835
 836 // m.
 837 def Zn2WriteLD_F80m : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
 838   let NumMicroOps = 2;
 839 }
 840 def : InstRW<[Zn2WriteLD_F80m], (instregex "LD_F80m")>;
 841
 842 // FBLD.
 843 def : InstRW<[WriteMicrocoded], (instregex "FBLDm")>;
 844
 845 // FST(P).
 846 // r.
 847 def : InstRW<[Zn2WriteSTr], (instregex "ST_(F|FP)rr")>;
 848
 849 // m80.
 850 def Zn2WriteST_FP80m : SchedWriteRes<[Zn2AGU, Zn2FPU23]> {
 851   let Latency = 5;
 852 }
 853 def : InstRW<[Zn2WriteST_FP80m], (instregex "ST_FP80m")>;
 854
 855 // FBSTP.
 856 // m80.
 857 def : InstRW<[WriteMicrocoded], (instregex "FBSTPm")>;
 858
 859 def Zn2WriteFXCH : SchedWriteRes<[Zn2FPU]>;
 860
 861 // FXCHG.
 862 def : InstRW<[Zn2WriteFXCH], (instrs XCH_F)>;
 863
 864 // FILD.
 865 def Zn2WriteFILD : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
 866   let Latency = 11;
 867   let NumMicroOps = 2;
 868 }
 869 def : InstRW<[Zn2WriteFILD], (instregex "ILD_F(16|32|64)m")>;
 870
 871 // FIST(P) FISTTP.
 872 def Zn2WriteFIST : SchedWriteRes<[Zn2AGU, Zn2FPU23]> {
 873   let Latency = 12;
 874 }
 875 def : InstRW<[Zn2WriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>;
 876
 877 def Zn2WriteFPU13 : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
 878   let Latency = 8;
 879 }
 880
 881 def Zn2WriteFPU3 : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
 882   let Latency = 11;
 883 }
 884
 885 // FLDZ.
 886 def : SchedAlias<WriteFLD0, Zn2WriteFPU13>;
 887
 888 // FLD1.
 889 def : SchedAlias<WriteFLD1, Zn2WriteFPU3>;
 890
 891 // FLDPI FLDL2E etc.
 892 def : SchedAlias<WriteFLDC, Zn2WriteFPU3>;
 893
 894 // FNSTSW.
 895 // AX.
 896 def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>;
 897
 898 // m16.
 899 def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>;
 900
 901 // FLDCW.
 902 def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>;
 903
 904 // FNSTCW.
 905 def : InstRW<[WriteMicrocoded], (instrs FNSTCW16m)>;
 906
 907 // FINCSTP FDECSTP.
 908 def : InstRW<[Zn2WriteFPU3], (instrs FINCSTP, FDECSTP)>;
 909
 910 // FFREE.
 911 def : InstRW<[Zn2WriteFPU3], (instregex "FFREE")>;
 912
 913 // FNSAVE.
 914 def : InstRW<[WriteMicrocoded], (instregex "FSAVEm")>;
 915
 916 // FRSTOR.
 917 def : InstRW<[WriteMicrocoded], (instregex "FRSTORm")>;
 918
 919 //-- Arithmetic instructions --//
 920
 921 def Zn2WriteFPU3Lat1 : SchedWriteRes<[Zn2FPU3]> ;
 922
 923 def Zn2WriteFPU0Lat1 : SchedWriteRes<[Zn2FPU0]> ;
 924
 925 def Zn2WriteFPU0Lat1Ld : SchedWriteRes<[Zn2AGU, Zn2FPU0]> {
 926   let Latency = 8;
 927 }
 928
 929 // FCHS.
 930 def : InstRW<[Zn2WriteFPU3Lat1], (instregex "CHS_F")>;
 931
 932 // FCOM(P) FUCOM(P).
 933 // r.
 934 def : InstRW<[Zn2WriteFPU0Lat1], (instregex "COM(P?)_FST0r", "UCOM_F(P?)r")>;
 935 // m.
 936 def : InstRW<[Zn2WriteFPU0Lat1Ld], (instregex "FCOM(P?)(32|64)m")>;
 937
 938 // FCOMPP FUCOMPP.
 939 // r.
 940 def : InstRW<[Zn2WriteFPU0Lat1], (instrs FCOMPP, UCOM_FPPr)>;
 941
 942 def Zn2WriteFPU02 : SchedWriteRes<[Zn2AGU, Zn2FPU02]>
 943 {
 944   let Latency = 9;
 945 }
 946
 947 // FCOMI(P) FUCOMI(P).
 948 // m.
 949 def : InstRW<[Zn2WriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
 950
 951 def Zn2WriteFPU03 : SchedWriteRes<[Zn2AGU, Zn2FPU03]>
 952 {
 953   let Latency = 12;
 954   let NumMicroOps = 2;
 955   let ResourceCycles = [1,3];
 956 }
 957
 958 // FICOM(P).
 959 def : InstRW<[Zn2WriteFPU03], (instregex "FICOM(P?)(16|32)m")>;
 960
 961 // FTST.
 962 def : InstRW<[Zn2WriteFPU0Lat1], (instregex "TST_F")>;
 963
 964 // FXAM.
 965 def : InstRW<[Zn2WriteFPU3Lat1], (instrs XAM_F)>;
 966
 967 // FPREM.
 968 def : InstRW<[WriteMicrocoded], (instrs FPREM)>;
 969
 970 // FPREM1.
 971 def : InstRW<[WriteMicrocoded], (instrs FPREM1)>;
 972
 973 // FRNDINT.
 974 def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>;
 975
 976 // FSCALE.
 977 def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
 978
 979 // FXTRACT.
 980 def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>;
 981
 982 // FNOP.
 983 def : InstRW<[Zn2WriteFPU0Lat1], (instrs FNOP)>;
 984
 985 // WAIT.
 986 def : InstRW<[Zn2WriteFPU0Lat1], (instrs WAIT)>;
 987
 988 // FNCLEX.
 989 def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>;
 990
 991 // FNINIT.
 992 def : InstRW<[WriteMicrocoded], (instrs FNINIT)>;
 993
 994 //=== Integer MMX and XMM Instructions ===//
 995
 996 // PACKSSWB/DW.
 997 // mm <- mm.
 998 def Zn2WriteFPU12 : SchedWriteRes<[Zn2FPU12]> ;
 999 def Zn2WriteFPU12Y : SchedWriteRes<[Zn2FPU12]> {
1000   let Latency = 4;
1001   let NumMicroOps = 2;
1002 }
1003 def Zn2WriteFPU12m : SchedWriteRes<[Zn2AGU, Zn2FPU12]> ;
1004 def Zn2WriteFPU12Ym : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1005   let Latency = 8;
1006   let NumMicroOps = 2;
1007 }
1008
1009 def : InstRW<[Zn2WriteFPU12], (instrs MMX_PACKSSDWirr,
1010                                      MMX_PACKSSWBirr,
1011                                      MMX_PACKUSWBirr)>;
1012 def : InstRW<[Zn2WriteFPU12m], (instrs MMX_PACKSSDWirm,
1013                                       MMX_PACKSSWBirm,
1014                                       MMX_PACKUSWBirm)>;
1015
1016 def Zn2WriteFPU013 : SchedWriteRes<[Zn2FPU013]> ;
1017 def Zn2WriteFPU013Y : SchedWriteRes<[Zn2FPU013]> ;
1018 def Zn2WriteFPU013m : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1019   let Latency = 8;
1020   let NumMicroOps = 2;
1021 }
1022 def Zn2WriteFPU013Ld : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1023   let Latency = 8;
1024   let NumMicroOps = 2;
1025 }
1026 def Zn2WriteFPU013LdY : SchedWriteRes<[Zn2AGU, Zn2FPU013]> {
1027   let Latency = 8;
1028   let NumMicroOps = 2;
1029 }
1030
1031 // PBLENDW.
1032 // x,x,i / v,v,v,i
1033 def : InstRW<[Zn2WriteFPU013], (instregex "(V?)PBLENDWrri")>;
1034 // ymm
1035 def : InstRW<[Zn2WriteFPU013Y], (instrs VPBLENDWYrri)>;
1036
1037 // x,m,i / v,v,m,i
1038 def : InstRW<[Zn2WriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>;
1039 // y,m,i
1040 def : InstRW<[Zn2WriteFPU013LdY], (instrs VPBLENDWYrmi)>;
1041
1042 def Zn2WriteFPU01 : SchedWriteRes<[Zn2FPU01]> ;
1043 def Zn2WriteFPU01Y : SchedWriteRes<[Zn2FPU01]> {
1044   let NumMicroOps = 2;
1045 }
1046
1047 // VPBLENDD.
1048 // v,v,v,i.
1049 def : InstRW<[Zn2WriteFPU01], (instrs VPBLENDDrri)>;
1050 // ymm
1051 def : InstRW<[Zn2WriteFPU01Y], (instrs VPBLENDDYrri)>;
1052
1053 // v,v,m,i
1054 def Zn2WriteFPU01Op2 : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1055   let NumMicroOps = 2;
1056   let Latency = 8;
1057   let ResourceCycles = [1, 2];
1058 }
1059 def Zn2WriteFPU01Op2Y : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1060   let NumMicroOps = 2;
1061   let Latency = 9;
1062   let ResourceCycles = [1, 3];
1063 }
1064 def : InstRW<[Zn2WriteFPU01Op2], (instrs VPBLENDDrmi)>;
1065 def : InstRW<[Zn2WriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
1066
1067 // MASKMOVQ.
1068 def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>;
1069
1070 // MASKMOVDQU.
1071 def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>;
1072
1073 // VPMASKMOVD.
1074 // ymm
1075 def : InstRW<[WriteMicrocoded],
1076                                (instregex "VPMASKMOVD(Y?)rm")>;
1077 // m, v,v.
1078 def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
1079
1080 // VPBROADCAST B/W.
1081 // x, m8/16.
1082 def Zn2WriteVPBROADCAST128Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1083   let Latency = 8;
1084   let NumMicroOps = 2;
1085   let ResourceCycles = [1, 2];
1086 }
1087 def : InstRW<[Zn2WriteVPBROADCAST128Ld],
1088                                      (instregex "VPBROADCAST(B|W)rm")>;
1089
1090 // y, m8/16
1091 def Zn2WriteVPBROADCAST256Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1092   let Latency = 8;
1093   let NumMicroOps = 2;
1094   let ResourceCycles = [1, 2];
1095 }
1096 def : InstRW<[Zn2WriteVPBROADCAST256Ld],
1097                                      (instregex "VPBROADCAST(B|W)Yrm")>;
1098
1099 // VPGATHER.
1100 def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>;
1101
1102 //-- Arithmetic instructions --//
1103
1104 // PCMPGTQ.
1105 def Zn2WritePCMPGTQr : SchedWriteRes<[Zn2FPU03]>;
1106 def : InstRW<[Zn2WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>;
1107
1108 // x <- x,m.
1109 def Zn2WritePCMPGTQm : SchedWriteRes<[Zn2AGU, Zn2FPU03]> {
1110   let Latency = 8;
1111 }
1112 // ymm.
1113 def Zn2WritePCMPGTQYm : SchedWriteRes<[Zn2AGU, Zn2FPU03]> {
1114   let Latency = 8;
1115 }
1116 def : InstRW<[Zn2WritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
1117 def : InstRW<[Zn2WritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
1118
1119 //-- Logic instructions --//
1120
1121 // PSLL,PSRL,PSRA W/D/Q.
1122 // x,x / v,v,x.
1123 def Zn2WritePShift  : SchedWriteRes<[Zn2FPU2]> {
1124   let Latency = 3;
1125 }
1126 def Zn2WritePShiftY : SchedWriteRes<[Zn2FPU2]> {
1127   let Latency = 3;
1128 }
1129
1130 // PSLL,PSRL DQ.
1131 def : InstRW<[Zn2WritePShift], (instregex "(V?)PS(R|L)LDQri")>;
1132 def : InstRW<[Zn2WritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>;
1133
1134 //=== Floating Point XMM and YMM Instructions ===//
1135 //-- Move instructions --//
1136
1137 // VPERM2F128.
1138 def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>;
1139 def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rm)>;
1140
1141 def Zn2WriteBROADCAST : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
1142   let NumMicroOps = 2;
1143   let Latency = 8;
1144 }
1145 // VBROADCASTF128.
1146 def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128)>;
1147
1148 // EXTRACTPS.
1149 // r32,x,i.
1150 def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
1151   let Latency = 2;
1152   let ResourceCycles = [1, 2];
1153 }
1154 def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1155
1156 def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
1157   let Latency = 5;
1158   let NumMicroOps = 2;
1159   let ResourceCycles = [5, 1, 2];
1160 }
1161 // m32,x,i.
1162 def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1163
1164 // VEXTRACTF128.
1165 // x,y,i.
1166 def : InstRW<[Zn2WriteFPU013], (instrs VEXTRACTF128rr)>;
1167
1168 // m128,y,i.
1169 def : InstRW<[Zn2WriteFPU013m], (instrs VEXTRACTF128mr)>;
1170
1171 def Zn2WriteVINSERT128r: SchedWriteRes<[Zn2FPU013]> {
1172   let Latency = 2;
1173 //  let ResourceCycles = [2];
1174 }
1175 def Zn2WriteVINSERT128Ld: SchedWriteRes<[Zn2AGU,Zn2FPU013]> {
1176   let Latency = 9;
1177   let NumMicroOps = 2;
1178 }
1179 // VINSERTF128.
1180 // y,y,x,i.
1181 def : InstRW<[Zn2WriteVINSERT128r], (instrs VINSERTF128rr)>;
1182 def : InstRW<[Zn2WriteVINSERT128Ld], (instrs VINSERTF128rm)>;
1183
1184 // VGATHER.
1185 def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>;
1186
1187 //-- Conversion instructions --//
1188 def Zn2WriteCVTPD2PSr: SchedWriteRes<[Zn2FPU3]> {
1189   let Latency = 3;
1190 }
1191 def Zn2WriteCVTPD2PSYr: SchedWriteRes<[Zn2FPU3]> {
1192   let Latency = 3;
1193 }
1194
1195 // CVTPD2PS.
1196 // x,x.
1197 def : SchedAlias<WriteCvtPD2PS,  Zn2WriteCVTPD2PSr>;
1198 // y,y.
1199 def : SchedAlias<WriteCvtPD2PSY, Zn2WriteCVTPD2PSYr>;
1200 // z,z.
1201 defm : X86WriteResUnsupported<WriteCvtPD2PSZ>;
1202
1203 def Zn2WriteCVTPD2PSLd: SchedWriteRes<[Zn2AGU,Zn2FPU03]> {
1204   let Latency = 10;
1205   let NumMicroOps = 2;
1206 }
1207 // x,m128.
1208 def : SchedAlias<WriteCvtPD2PSLd, Zn2WriteCVTPD2PSLd>;
1209
1210 // x,m256.
1211 def Zn2WriteCVTPD2PSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1212   let Latency = 10;
1213 }
1214 def : SchedAlias<WriteCvtPD2PSYLd, Zn2WriteCVTPD2PSYLd>;
1215 // z,m512
1216 defm : X86WriteResUnsupported<WriteCvtPD2PSZLd>;
1217
1218 // CVTSD2SS.
1219 // x,x.
1220 // Same as WriteCVTPD2PSr
1221 def : SchedAlias<WriteCvtSD2SS, Zn2WriteCVTPD2PSr>;
1222
1223 // x,m64.
1224 def : SchedAlias<WriteCvtSD2SSLd, Zn2WriteCVTPD2PSLd>;
1225
1226 // CVTPS2PD.
1227 // x,x.
1228 def Zn2WriteCVTPS2PDr : SchedWriteRes<[Zn2FPU3]> {
1229   let Latency = 3;
1230 }
1231 def : SchedAlias<WriteCvtPS2PD, Zn2WriteCVTPS2PDr>;
1232
1233 // x,m64.
1234 // y,m128.
1235 def Zn2WriteCVTPS2PDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1236   let Latency = 10;
1237   let NumMicroOps = 2;
1238 }
1239 def : SchedAlias<WriteCvtPS2PDLd, Zn2WriteCVTPS2PDLd>;
1240 def : SchedAlias<WriteCvtPS2PDYLd, Zn2WriteCVTPS2PDLd>;
1241 defm : X86WriteResUnsupported<WriteCvtPS2PDZLd>;
1242
1243 // y,x.
1244 def Zn2WriteVCVTPS2PDY : SchedWriteRes<[Zn2FPU3]> {
1245   let Latency = 3;
1246 }
1247 def : SchedAlias<WriteCvtPS2PDY, Zn2WriteVCVTPS2PDY>;
1248 defm : X86WriteResUnsupported<WriteCvtPS2PDZ>;
1249
1250 // CVTSS2SD.
1251 // x,x.
1252 def Zn2WriteCVTSS2SDr : SchedWriteRes<[Zn2FPU3]> {
1253   let Latency = 3;
1254 }
1255 def : SchedAlias<WriteCvtSS2SD, Zn2WriteCVTSS2SDr>;
1256
1257 // x,m32.
1258 def Zn2WriteCVTSS2SDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1259   let Latency = 10;
1260   let NumMicroOps = 2;
1261   let ResourceCycles = [1, 2];
1262 }
1263 def : SchedAlias<WriteCvtSS2SDLd, Zn2WriteCVTSS2SDLd>;
1264
1265 def Zn2WriteCVTDQ2PDr: SchedWriteRes<[Zn2FPU12,Zn2FPU3]> {
1266   let Latency = 3;
1267 }
1268 // CVTDQ2PD.
1269 // x,x.
1270 def : InstRW<[Zn2WriteCVTDQ2PDr], (instregex "(V)?CVTDQ2P(D|S)rr")>;
1271
1272 // Same as xmm
1273 // y,x.
1274 def : InstRW<[Zn2WriteCVTDQ2PDr], (instrs VCVTDQ2PDYrr)>;
1275 def : InstRW<[Zn2WriteCVTDQ2PDr], (instrs VCVTDQ2PSYrr)>;
1276
1277 def Zn2WriteCVTPD2DQr: SchedWriteRes<[Zn2FPU12, Zn2FPU3]> {
1278   let Latency = 3;
1279 }
1280 // CVT(T)P(D|S)2DQ.
1281 // x,x.
1282 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "(V?)CVT(T?)P(D|S)2DQrr")>;
1283
1284 def Zn2WriteCVTPD2DQLd: SchedWriteRes<[Zn2AGU,Zn2FPU12,Zn2FPU3]> {
1285   let Latency = 10;
1286   let NumMicroOps = 2;
1287 }
1288 // x,m128.
1289 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "(V?)CVT(T?)PD2DQrm")>;
1290 // same as xmm handling
1291 // x,y.
1292 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>;
1293 // x,m256.
1294 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
1295
1296 def Zn2WriteCVTPS2PIr: SchedWriteRes<[Zn2FPU3]> {
1297   let Latency = 4;
1298 }
1299 // CVT(T)PS2PI.
1300 // mm,x.
1301 def : InstRW<[Zn2WriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>;
1302
1303 // CVTPI2PD.
1304 // x,mm.
1305 def : InstRW<[Zn2WriteCVTPS2PDr], (instrs MMX_CVTPI2PDirr)>;
1306
1307 // CVT(T)PD2PI.
1308 // mm,x.
1309 def : InstRW<[Zn2WriteCVTPS2PIr], (instregex "MMX_CVT(T?)PD2PIirr")>;
1310
1311 def Zn2WriteCVSTSI2SSr: SchedWriteRes<[Zn2FPU3]> {
1312   let Latency = 3;
1313 }
1314
1315 // same as CVTPD2DQr
1316 // CVT(T)SS2SI.
1317 // r32,x.
1318 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "(V?)CVT(T?)SS2SI(64)?rr")>;
1319 // same as CVTPD2DQm
1320 // r32,m32.
1321 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "(V?)CVT(T?)SS2SI(64)?rm")>;
1322
1323 def Zn2WriteCVSTSI2SDr: SchedWriteRes<[Zn2FPU013, Zn2FPU3]> {
1324   let Latency = 3;
1325 }
1326 // CVTSI2SD.
1327 // x,r32/64.
1328 def : InstRW<[Zn2WriteCVSTSI2SDr], (instregex "(V?)CVTSI(64)?2SDrr")>;
1329
1330
1331 def Zn2WriteCVSTSI2SIr: SchedWriteRes<[Zn2FPU3, Zn2FPU2]> {
1332   let Latency = 4;
1333 }
1334 def Zn2WriteCVSTSI2SILd: SchedWriteRes<[Zn2AGU, Zn2FPU3, Zn2FPU2]> {
1335   let Latency = 11;
1336 }
1337 // CVTSD2SI.
1338 // r32/64
1339 def : InstRW<[Zn2WriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>;
1340 // r32,m32.
1341 def : InstRW<[Zn2WriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>;
1342
1343 // VCVTPS2PH.
1344 // x,v,i.
1345 def : SchedAlias<WriteCvtPS2PH,    Zn2WriteMicrocoded>;
1346 def : SchedAlias<WriteCvtPS2PHY,   Zn2WriteMicrocoded>;
1347 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
1348 // m,v,i.
1349 def : SchedAlias<WriteCvtPS2PHSt,  Zn2WriteMicrocoded>;
1350 def : SchedAlias<WriteCvtPS2PHYSt, Zn2WriteMicrocoded>;
1351 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
1352
1353 // VCVTPH2PS.
1354 // v,x.
1355 def : SchedAlias<WriteCvtPH2PS,    Zn2WriteMicrocoded>;
1356 def : SchedAlias<WriteCvtPH2PSY,   Zn2WriteMicrocoded>;
1357 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
1358 // v,m.
1359 def : SchedAlias<WriteCvtPH2PSLd,  Zn2WriteMicrocoded>;
1360 def : SchedAlias<WriteCvtPH2PSYLd, Zn2WriteMicrocoded>;
1361 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
1362
1363 //-- SSE4A instructions --//
1364 // EXTRQ
1365 def Zn2WriteEXTRQ: SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
1366   let Latency = 3;
1367 }
1368 def : InstRW<[Zn2WriteEXTRQ], (instregex "EXTRQ")>;
1369
1370 // INSERTQ
1371 def Zn2WriteINSERTQ: SchedWriteRes<[Zn2FPU03,Zn2FPU1]> {
1372   let Latency = 4;
1373 }
1374 def : InstRW<[Zn2WriteINSERTQ], (instregex "INSERTQ")>;
1375
1376 //-- SHA instructions --//
1377 // SHA256MSG2
1378 def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
1379
1380 // SHA1MSG1, SHA256MSG1
1381 // x,x.
1382 def Zn2WriteSHA1MSG1r : SchedWriteRes<[Zn2FPU12]> {
1383   let Latency = 2;
1384 }
1385 def : InstRW<[Zn2WriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>;
1386 // x,m.
1387 def Zn2WriteSHA1MSG1Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1388   let Latency = 9;
1389 }
1390 def : InstRW<[Zn2WriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>;
1391
1392 // SHA1MSG2
1393 // x,x.
1394 def Zn2WriteSHA1MSG2r : SchedWriteRes<[Zn2FPU12]> ;
1395 def : InstRW<[Zn2WriteSHA1MSG2r], (instregex "SHA1MSG2rr")>;
1396 // x,m.
1397 def Zn2WriteSHA1MSG2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
1398   let Latency = 8;
1399 }
1400 def : InstRW<[Zn2WriteSHA1MSG2Ld], (instregex "SHA1MSG2rm")>;
1401
1402 // SHA1NEXTE
1403 // x,x.
1404 def Zn2WriteSHA1NEXTEr : SchedWriteRes<[Zn2FPU1]> ;
1405 def : InstRW<[Zn2WriteSHA1NEXTEr], (instregex "SHA1NEXTErr")>;
1406 // x,m.
1407 def Zn2WriteSHA1NEXTELd : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1408   let Latency = 8;
1409 }
1410 def : InstRW<[Zn2WriteSHA1NEXTELd], (instregex "SHA1NEXTErm")>;
1411
1412 // SHA1RNDS4
1413 // x,x.
1414 def Zn2WriteSHA1RNDS4r : SchedWriteRes<[Zn2FPU1]> {
1415   let Latency = 6;
1416 }
1417 def : InstRW<[Zn2WriteSHA1RNDS4r], (instregex "SHA1RNDS4rr")>;
1418 // x,m.
1419 def Zn2WriteSHA1RNDS4Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1420   let Latency = 13;
1421 }
1422 def : InstRW<[Zn2WriteSHA1RNDS4Ld], (instregex "SHA1RNDS4rm")>;
1423
1424 // SHA256RNDS2
1425 // x,x.
1426 def Zn2WriteSHA256RNDS2r : SchedWriteRes<[Zn2FPU1]> {
1427   let Latency = 4;
1428 }
1429 def : InstRW<[Zn2WriteSHA256RNDS2r], (instregex "SHA256RNDS2rr")>;
1430 // x,m.
1431 def Zn2WriteSHA256RNDS2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
1432   let Latency = 11;
1433 }
1434 def : InstRW<[Zn2WriteSHA256RNDS2Ld], (instregex "SHA256RNDS2rm")>;
1435
1436 //-- Arithmetic instructions --//
1437
1438 // VDIVPS.
1439 // TODO - convert to Zn2WriteResFpuPair
1440 // y,y,y.
1441 def Zn2WriteVDIVPSYr : SchedWriteRes<[Zn2FPU3]> {
1442   let Latency = 10;
1443   let ResourceCycles = [10];
1444 }
1445 def : SchedAlias<WriteFDivY,   Zn2WriteVDIVPSYr>;
1446
1447 // y,y,m256.
1448 def Zn2WriteVDIVPSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1449   let Latency = 17;
1450   let NumMicroOps = 2;
1451   let ResourceCycles = [1, 17];
1452 }
1453 def : SchedAlias<WriteFDivYLd,  Zn2WriteVDIVPSYLd>;
1454
1455 // VDIVPD.
1456 // TODO - convert to Zn2WriteResFpuPair
1457 // y,y,y.
1458 def Zn2WriteVDIVPDY : SchedWriteRes<[Zn2FPU3]> {
1459   let Latency = 13;
1460   let ResourceCycles = [13];
1461 }
1462 def : SchedAlias<WriteFDiv64Y, Zn2WriteVDIVPDY>;
1463
1464 // y,y,m256.
1465 def Zn2WriteVDIVPDYLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
1466   let Latency = 20;
1467   let NumMicroOps = 2;
1468   let ResourceCycles = [1,20];
1469 }
1470 def : SchedAlias<WriteFDiv64YLd, Zn2WriteVDIVPDYLd>;
1471
1472 // DPPS.
1473 // x,x,i / v,v,v,i.
1474 def : SchedAlias<WriteDPPSY,  Zn2WriteMicrocoded>;
1475
1476 // x,m,i / v,v,m,i.
1477 def : SchedAlias<WriteDPPSYLd,Zn2WriteMicrocoded>;
1478
1479 // DPPD.
1480 // x,x,i.
1481 def : SchedAlias<WriteDPPD,   Zn2WriteMicrocoded>;
1482
1483 // x,m,i.
1484 def : SchedAlias<WriteDPPDLd, Zn2WriteMicrocoded>;
1485
1486 // RSQRTSS
1487 // TODO - convert to Zn2WriteResFpuPair
1488 // x,x.
1489 def Zn2WriteRSQRTSSr : SchedWriteRes<[Zn2FPU02]> {
1490   let Latency = 5;
1491 }
1492 def : SchedAlias<WriteFRsqrt, Zn2WriteRSQRTSSr>;
1493
1494 // x,m128.
1495 def Zn2WriteRSQRTSSLd: SchedWriteRes<[Zn2AGU, Zn2FPU02]> {
1496   let Latency = 12;
1497   let NumMicroOps = 2;
1498   let ResourceCycles = [1,2];
1499 }
1500 def : SchedAlias<WriteFRsqrtLd, Zn2WriteRSQRTSSLd>;
1501
1502 // RSQRTPS
1503 // TODO - convert to Zn2WriteResFpuPair
1504 // y,y.
1505 def Zn2WriteRSQRTPSYr : SchedWriteRes<[Zn2FPU01]> {
1506   let Latency = 5;
1507   let NumMicroOps = 2;
1508   let ResourceCycles = [2];
1509 }
1510 def : SchedAlias<WriteFRsqrtY, Zn2WriteRSQRTPSYr>;
1511
1512 // y,m256.
1513 def Zn2WriteRSQRTPSYLd : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
1514   let Latency = 12;
1515   let NumMicroOps = 2;
1516 }
1517 def : SchedAlias<WriteFRsqrtYLd, Zn2WriteRSQRTPSYLd>;
1518
1519 //-- Other instructions --//
1520
1521 // VZEROUPPER.
1522 def : InstRW<[WriteALU], (instrs VZEROUPPER)>;
1523
1524 // VZEROALL.
1525 def : InstRW<[WriteMicrocoded], (instrs VZEROALL)>;
1526
1527 } // SchedModel