llvm/lib/Target/X86/X86Subtarget.h

   1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
  14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
  15
  16 #include "X86FrameLowering.h"
  17 #include "X86ISelLowering.h"
  18 #include "X86InstrInfo.h"
  19 #include "X86SelectionDAGInfo.h"
  20 #include "llvm/ADT/Triple.h"
  21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  22 #include "llvm/IR/CallingConv.h"
  23 #include <climits>
  24 #include <memory>
  25
  26 #define GET_SUBTARGETINFO_HEADER
  27 #include "X86GenSubtargetInfo.inc"
  28
  29 namespace llvm {
  30
  31 class CallLowering;
  32 class GlobalValue;
  33 class InstructionSelector;
  34 class LegalizerInfo;
  35 class RegisterBankInfo;
  36 class StringRef;
  37 class TargetMachine;
  38
  39 /// The X86 backend supports a number of different styles of PIC.
  40 ///
  41 namespace PICStyles {
  42
  43 enum class Style {
  44   StubPIC,          // Used on i386-darwin in pic mode.
  45   GOT,              // Used on 32 bit elf on when in pic mode.
  46   RIPRel,           // Used on X86-64 when in pic mode.
  47   None              // Set when not in pic mode.
  48 };
  49
  50 } // end namespace PICStyles
  51
  52 class X86Subtarget final : public X86GenSubtargetInfo {
  53   // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
  54   // are not a good idea. We should be migrating away from these.
  55   enum X86ProcFamilyEnum {
  56     Others,
  57     IntelAtom,
  58     IntelSLM
  59   };
  60
  61   enum X86SSEEnum {
  62     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
  63   };
  64
  65   enum X863DNowEnum {
  66     NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
  67   };
  68
  69   /// X86 processor family: Intel Atom, and others
  70   X86ProcFamilyEnum X86ProcFamily = Others;
  71
  72   /// Which PIC style to use
  73   PICStyles::Style PICStyle;
  74
  75   const TargetMachine &TM;
  76
  77   /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
  78   X86SSEEnum X86SSELevel = NoSSE;
  79
  80   /// MMX, 3DNow, 3DNow Athlon, or none supported.
  81   X863DNowEnum X863DNowLevel = NoThreeDNow;
  82
  83   /// True if the processor supports X87 instructions.
  84   bool HasX87 = false;
  85
  86   /// True if the processor supports CMPXCHG8B.
  87   bool HasCmpxchg8b = false;
  88
  89   /// True if this processor has NOPL instruction
  90   /// (generally pentium pro+).
  91   bool HasNOPL = false;
  92
  93   /// True if this processor has conditional move instructions
  94   /// (generally pentium pro+).
  95   bool HasCMov = false;
  96
  97   /// True if the processor supports X86-64 instructions.
  98   bool HasX86_64 = false;
  99
 100   /// True if the processor supports POPCNT.
 101   bool HasPOPCNT = false;
 102
 103   /// True if the processor supports SSE4A instructions.
 104   bool HasSSE4A = false;
 105
 106   /// Target has AES instructions
 107   bool HasAES = false;
 108   bool HasVAES = false;
 109
 110   /// Target has FXSAVE/FXRESTOR instructions
 111   bool HasFXSR = false;
 112
 113   /// Target has XSAVE instructions
 114   bool HasXSAVE = false;
 115
 116   /// Target has XSAVEOPT instructions
 117   bool HasXSAVEOPT = false;
 118
 119   /// Target has XSAVEC instructions
 120   bool HasXSAVEC = false;
 121
 122   /// Target has XSAVES instructions
 123   bool HasXSAVES = false;
 124
 125   /// Target has carry-less multiplication
 126   bool HasPCLMUL = false;
 127   bool HasVPCLMULQDQ = false;
 128
 129   /// Target has Galois Field Arithmetic instructions
 130   bool HasGFNI = false;
 131
 132   /// Target has 3-operand fused multiply-add
 133   bool HasFMA = false;
 134
 135   /// Target has 4-operand fused multiply-add
 136   bool HasFMA4 = false;
 137
 138   /// Target has XOP instructions
 139   bool HasXOP = false;
 140
 141   /// Target has TBM instructions.
 142   bool HasTBM = false;
 143
 144   /// Target has LWP instructions
 145   bool HasLWP = false;
 146
 147   /// True if the processor has the MOVBE instruction.
 148   bool HasMOVBE = false;
 149
 150   /// True if the processor has the RDRAND instruction.
 151   bool HasRDRAND = false;
 152
 153   /// Processor has 16-bit floating point conversion instructions.
 154   bool HasF16C = false;
 155
 156   /// Processor has FS/GS base insturctions.
 157   bool HasFSGSBase = false;
 158
 159   /// Processor has LZCNT instruction.
 160   bool HasLZCNT = false;
 161
 162   /// Processor has BMI1 instructions.
 163   bool HasBMI = false;
 164
 165   /// Processor has BMI2 instructions.
 166   bool HasBMI2 = false;
 167
 168   /// Processor has VBMI instructions.
 169   bool HasVBMI = false;
 170
 171   /// Processor has VBMI2 instructions.
 172   bool HasVBMI2 = false;
 173
 174   /// Processor has Integer Fused Multiply Add
 175   bool HasIFMA = false;
 176
 177   /// Processor has RTM instructions.
 178   bool HasRTM = false;
 179
 180   /// Processor has ADX instructions.
 181   bool HasADX = false;
 182
 183   /// Processor has SHA instructions.
 184   bool HasSHA = false;
 185
 186   /// Processor has PRFCHW instructions.
 187   bool HasPRFCHW = false;
 188
 189   /// Processor has RDSEED instructions.
 190   bool HasRDSEED = false;
 191
 192   /// Processor has LAHF/SAHF instructions in 64-bit mode.
 193   bool HasLAHFSAHF64 = false;
 194
 195   /// Processor has MONITORX/MWAITX instructions.
 196   bool HasMWAITX = false;
 197
 198   /// Processor has Cache Line Zero instruction
 199   bool HasCLZERO = false;
 200
 201   /// Processor has Cache Line Demote instruction
 202   bool HasCLDEMOTE = false;
 203
 204   /// Processor has MOVDIRI instruction (direct store integer).
 205   bool HasMOVDIRI = false;
 206
 207   /// Processor has MOVDIR64B instruction (direct store 64 bytes).
 208   bool HasMOVDIR64B = false;
 209
 210   /// Processor has ptwrite instruction.
 211   bool HasPTWRITE = false;
 212
 213   /// Processor has Prefetch with intent to Write instruction
 214   bool HasPREFETCHWT1 = false;
 215
 216   /// True if SHLD instructions are slow.
 217   bool IsSHLDSlow = false;
 218
 219   /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
 220   //  PMULUDQ.
 221   bool IsPMULLDSlow = false;
 222
 223   /// True if the PMADDWD instruction is slow compared to PMULLD.
 224   bool IsPMADDWDSlow = false;
 225
 226   /// True if unaligned memory accesses of 16-bytes are slow.
 227   bool IsUAMem16Slow = false;
 228
 229   /// True if unaligned memory accesses of 32-bytes are slow.
 230   bool IsUAMem32Slow = false;
 231
 232   /// True if SSE operations can have unaligned memory operands.
 233   /// This may require setting a configuration bit in the processor.
 234   bool HasSSEUnalignedMem = false;
 235
 236   /// True if this processor has the CMPXCHG16B instruction;
 237   /// this is true for most x86-64 chips, but not the first AMD chips.
 238   bool HasCmpxchg16b = false;
 239
 240   /// True if the LEA instruction should be used for adjusting
 241   /// the stack pointer. This is an optimization for Intel Atom processors.
 242   bool UseLeaForSP = false;
 243
 244   /// True if POPCNT instruction has a false dependency on the destination register.
 245   bool HasPOPCNTFalseDeps = false;
 246
 247   /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
 248   bool HasLZCNTFalseDeps = false;
 249
 250   /// True if its preferable to combine to a single cross-lane shuffle
 251   /// using a variable mask over multiple fixed shuffles.
 252   bool HasFastVariableCrossLaneShuffle = false;
 253
 254   /// True if its preferable to combine to a single per-lane shuffle
 255   /// using a variable mask over multiple fixed shuffles.
 256   bool HasFastVariablePerLaneShuffle = false;
 257
 258   /// True if vzeroupper instructions should be inserted after code that uses
 259   /// ymm or zmm registers.
 260   bool InsertVZEROUPPER = false;
 261
 262   /// True if there is no performance penalty for writing NOPs with up to
 263   /// 7 bytes.
 264   bool HasFast7ByteNOP = false;
 265
 266   /// True if there is no performance penalty for writing NOPs with up to
 267   /// 11 bytes.
 268   bool HasFast11ByteNOP = false;
 269
 270   /// True if there is no performance penalty for writing NOPs with up to
 271   /// 15 bytes.
 272   bool HasFast15ByteNOP = false;
 273
 274   /// True if gather is reasonably fast. This is true for Skylake client and
 275   /// all AVX-512 CPUs.
 276   bool HasFastGather = false;
 277
 278   /// True if hardware SQRTSS instruction is at least as fast (latency) as
 279   /// RSQRTSS followed by a Newton-Raphson iteration.
 280   bool HasFastScalarFSQRT = false;
 281
 282   /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
 283   /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
 284   bool HasFastVectorFSQRT = false;
 285
 286   /// True if 8-bit divisions are significantly faster than
 287   /// 32-bit divisions and should be used when possible.
 288   bool HasSlowDivide32 = false;
 289
 290   /// True if 32-bit divides are significantly faster than
 291   /// 64-bit divisions and should be used when possible.
 292   bool HasSlowDivide64 = false;
 293
 294   /// True if LZCNT instruction is fast.
 295   bool HasFastLZCNT = false;
 296
 297   /// True if SHLD based rotate is fast.
 298   bool HasFastSHLDRotate = false;
 299
 300   /// True if the processor supports macrofusion.
 301   bool HasMacroFusion = false;
 302
 303   /// True if the processor supports branch fusion.
 304   bool HasBranchFusion = false;
 305
 306   /// True if the processor has enhanced REP MOVSB/STOSB.
 307   bool HasERMSB = false;
 308
 309   /// True if the processor has fast short REP MOV.
 310   bool HasFSRM = false;
 311
 312   /// True if the short functions should be padded to prevent
 313   /// a stall when returning too early.
 314   bool PadShortFunctions = false;
 315
 316   /// True if two memory operand instructions should use a temporary register
 317   /// instead.
 318   bool SlowTwoMemOps = false;
 319
 320   /// True if the LEA instruction inputs have to be ready at address generation
 321   /// (AG) time.
 322   bool LEAUsesAG = false;
 323
 324   /// True if the LEA instruction with certain arguments is slow
 325   bool SlowLEA = false;
 326
 327   /// True if the LEA instruction has all three source operands: base, index,
 328   /// and offset or if the LEA instruction uses base and index registers where
 329   /// the base is EBP, RBP,or R13
 330   bool Slow3OpsLEA = false;
 331
 332   /// True if INC and DEC instructions are slow when writing to flags
 333   bool SlowIncDec = false;
 334
 335   /// Processor has AVX-512 PreFetch Instructions
 336   bool HasPFI = false;
 337
 338   /// Processor has AVX-512 Exponential and Reciprocal Instructions
 339   bool HasERI = false;
 340
 341   /// Processor has AVX-512 Conflict Detection Instructions
 342   bool HasCDI = false;
 343
 344   /// Processor has AVX-512 population count Instructions
 345   bool HasVPOPCNTDQ = false;
 346
 347   /// Processor has AVX-512 Doubleword and Quadword instructions
 348   bool HasDQI = false;
 349
 350   /// Processor has AVX-512 Byte and Word instructions
 351   bool HasBWI = false;
 352
 353   /// Processor has AVX-512 Vector Length eXtenstions
 354   bool HasVLX = false;
 355
 356   /// Processor has AVX-512 16 bit floating-point extenstions
 357   bool HasFP16 = false;
 358
 359   /// Processor has PKU extenstions
 360   bool HasPKU = false;
 361
 362   /// Processor has AVX-512 Vector Neural Network Instructions
 363   bool HasVNNI = false;
 364
 365   /// Processor has AVX Vector Neural Network Instructions
 366   bool HasAVXVNNI = false;
 367
 368   /// Processor has AVX-512 bfloat16 floating-point extensions
 369   bool HasBF16 = false;
 370
 371   /// Processor supports ENQCMD instructions
 372   bool HasENQCMD = false;
 373
 374   /// Processor has AVX-512 Bit Algorithms instructions
 375   bool HasBITALG = false;
 376
 377   /// Processor has AVX-512 vp2intersect instructions
 378   bool HasVP2INTERSECT = false;
 379
 380   /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
 381   /// using Shadow Stack
 382   bool HasSHSTK = false;
 383
 384   /// Processor supports Invalidate Process-Context Identifier
 385   bool HasINVPCID = false;
 386
 387   /// Processor has Software Guard Extensions
 388   bool HasSGX = false;
 389
 390   /// Processor supports Flush Cache Line instruction
 391   bool HasCLFLUSHOPT = false;
 392
 393   /// Processor supports Cache Line Write Back instruction
 394   bool HasCLWB = false;
 395
 396   /// Processor supports Write Back No Invalidate instruction
 397   bool HasWBNOINVD = false;
 398
 399   /// Processor support RDPID instruction
 400   bool HasRDPID = false;
 401
 402   /// Processor supports WaitPKG instructions
 403   bool HasWAITPKG = false;
 404
 405   /// Processor supports PCONFIG instruction
 406   bool HasPCONFIG = false;
 407
 408   /// Processor support key locker instructions
 409   bool HasKL = false;
 410
 411   /// Processor support key locker wide instructions
 412   bool HasWIDEKL = false;
 413
 414   /// Processor supports HRESET instruction
 415   bool HasHRESET = false;
 416
 417   /// Processor supports SERIALIZE instruction
 418   bool HasSERIALIZE = false;
 419
 420   /// Processor supports TSXLDTRK instruction
 421   bool HasTSXLDTRK = false;
 422
 423   /// Processor has AMX support
 424   bool HasAMXTILE = false;
 425   bool HasAMXBF16 = false;
 426   bool HasAMXINT8 = false;
 427
 428   /// Processor supports User Level Interrupt instructions
 429   bool HasUINTR = false;
 430
 431   /// Processor has a single uop BEXTR implementation.
 432   bool HasFastBEXTR = false;
 433
 434   /// Try harder to combine to horizontal vector ops if they are fast.
 435   bool HasFastHorizontalOps = false;
 436
 437   /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
 438   bool HasFastScalarShiftMasks = false;
 439
 440   /// Prefer a left/right vector logical shifts pair over a shift+and pair.
 441   bool HasFastVectorShiftMasks = false;
 442
 443   /// Prefer a movbe over a single-use load + bswap / single-use bswap + store.
 444   bool HasFastMOVBE = false;
 445
 446   /// Use a retpoline thunk rather than indirect calls to block speculative
 447   /// execution.
 448   bool UseRetpolineIndirectCalls = false;
 449
 450   /// Use a retpoline thunk or remove any indirect branch to block speculative
 451   /// execution.
 452   bool UseRetpolineIndirectBranches = false;
 453
 454   /// Deprecated flag, query `UseRetpolineIndirectCalls` and
 455   /// `UseRetpolineIndirectBranches` instead.
 456   bool DeprecatedUseRetpoline = false;
 457
 458   /// When using a retpoline thunk, call an externally provided thunk rather
 459   /// than emitting one inside the compiler.
 460   bool UseRetpolineExternalThunk = false;
 461
 462   /// Prevent generation of indirect call/branch instructions from memory,
 463   /// and force all indirect call/branch instructions from a register to be
 464   /// preceded by an LFENCE. Also decompose RET instructions into a
 465   /// POP+LFENCE+JMP sequence.
 466   bool UseLVIControlFlowIntegrity = false;
 467
 468   /// Enable Speculative Execution Side Effect Suppression
 469   bool UseSpeculativeExecutionSideEffectSuppression = false;
 470
 471   /// Insert LFENCE instructions to prevent data speculatively injected into
 472   /// loads from being used maliciously.
 473   bool UseLVILoadHardening = false;
 474
 475   /// Use software floating point for code generation.
 476   bool UseSoftFloat = false;
 477
 478   /// Use alias analysis during code generation.
 479   bool UseAA = false;
 480
 481   /// The minimum alignment known to hold of the stack frame on
 482   /// entry to the function and which must be maintained by every function.
 483   Align stackAlignment = Align(4);
 484
 485   Align TileConfigAlignment = Align(4);
 486
 487   /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
 488   ///
 489   // FIXME: this is a known good value for Yonah. How about others?
 490   unsigned MaxInlineSizeThreshold = 128;
 491
 492   /// Indicates target prefers 128 bit instructions.
 493   bool Prefer128Bit = false;
 494
 495   /// Indicates target prefers 256 bit instructions.
 496   bool Prefer256Bit = false;
 497
 498   /// Indicates target prefers AVX512 mask registers.
 499   bool PreferMaskRegisters = false;
 500
 501   /// Use Goldmont specific floating point div/sqrt costs.
 502   bool UseGLMDivSqrtCosts = false;
 503
 504   /// What processor and OS we're targeting.
 505   Triple TargetTriple;
 506
 507   /// GlobalISel related APIs.
 508   std::unique_ptr<CallLowering> CallLoweringInfo;
 509   std::unique_ptr<LegalizerInfo> Legalizer;
 510   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 511   std::unique_ptr<InstructionSelector> InstSelector;
 512
 513 private:
 514   /// Override the stack alignment.
 515   MaybeAlign StackAlignOverride;
 516
 517   /// Preferred vector width from function attribute.
 518   unsigned PreferVectorWidthOverride;
 519
 520   /// Resolved preferred vector width from function attribute and subtarget
 521   /// features.
 522   unsigned PreferVectorWidth = UINT32_MAX;
 523
 524   /// Required vector width from function attribute.
 525   unsigned RequiredVectorWidth;
 526
 527   /// True if compiling for 64-bit, false for 16-bit or 32-bit.
 528   bool In64BitMode = false;
 529
 530   /// True if compiling for 32-bit, false for 16-bit or 64-bit.
 531   bool In32BitMode = false;
 532
 533   /// True if compiling for 16-bit, false for 32-bit or 64-bit.
 534   bool In16BitMode = false;
 535
 536   X86SelectionDAGInfo TSInfo;
 537   // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
 538   // X86TargetLowering needs.
 539   X86InstrInfo InstrInfo;
 540   X86TargetLowering TLInfo;
 541   X86FrameLowering FrameLowering;
 542
 543 public:
 544   /// This constructor initializes the data members to match that
 545   /// of the specified triple.
 546   ///
 547   X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
 548                const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
 549                unsigned PreferVectorWidthOverride,
 550                unsigned RequiredVectorWidth);
 551
 552   const X86TargetLowering *getTargetLowering() const override {
 553     return &TLInfo;
 554   }
 555
 556   const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
 557
 558   const X86FrameLowering *getFrameLowering() const override {
 559     return &FrameLowering;
 560   }
 561
 562   const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
 563     return &TSInfo;
 564   }
 565
 566   const X86RegisterInfo *getRegisterInfo() const override {
 567     return &getInstrInfo()->getRegisterInfo();
 568   }
 569
 570   unsigned getTileConfigSize() const { return 64; }
 571   Align getTileConfigAlignment() const { return TileConfigAlignment; }
 572
 573   /// Returns the minimum alignment known to hold of the
 574   /// stack frame on entry to the function and which must be maintained by every
 575   /// function for this subtarget.
 576   Align getStackAlignment() const { return stackAlignment; }
 577
 578   /// Returns the maximum memset / memcpy size
 579   /// that still makes it profitable to inline the call.
 580   unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
 581
 582   /// ParseSubtargetFeatures - Parses features string setting specified
 583   /// subtarget options.  Definition of function is auto generated by tblgen.
 584   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 585
 586   /// Methods used by Global ISel
 587   const CallLowering *getCallLowering() const override;
 588   InstructionSelector *getInstructionSelector() const override;
 589   const LegalizerInfo *getLegalizerInfo() const override;
 590   const RegisterBankInfo *getRegBankInfo() const override;
 591
 592 private:
 593   /// Initialize the full set of dependencies so we can use an initializer
 594   /// list for X86Subtarget.
 595   X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
 596                                                 StringRef TuneCPU,
 597                                                 StringRef FS);
 598   void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 599
 600 public:
 601   /// Is this x86_64? (disregarding specific ABI / programming model)
 602   bool is64Bit() const {
 603     return In64BitMode;
 604   }
 605
 606   bool is32Bit() const {
 607     return In32BitMode;
 608   }
 609
 610   bool is16Bit() const {
 611     return In16BitMode;
 612   }
 613
 614   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
 615   bool isTarget64BitILP32() const {
 616     return In64BitMode && (TargetTriple.isX32() || TargetTriple.isOSNaCl());
 617   }
 618
 619   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
 620   bool isTarget64BitLP64() const {
 621     return In64BitMode && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl());
 622   }
 623
 624   PICStyles::Style getPICStyle() const { return PICStyle; }
 625   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
 626
 627   bool hasX87() const { return HasX87; }
 628   bool hasCmpxchg8b() const { return HasCmpxchg8b; }
 629   bool hasNOPL() const { return HasNOPL; }
 630   // SSE codegen depends on cmovs, and all SSE1+ processors support them.
 631   // All 64-bit processors support cmov.
 632   bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
 633   bool hasSSE1() const { return X86SSELevel >= SSE1; }
 634   bool hasSSE2() const { return X86SSELevel >= SSE2; }
 635   bool hasSSE3() const { return X86SSELevel >= SSE3; }
 636   bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
 637   bool hasSSE41() const { return X86SSELevel >= SSE41; }
 638   bool hasSSE42() const { return X86SSELevel >= SSE42; }
 639   bool hasAVX() const { return X86SSELevel >= AVX; }
 640   bool hasAVX2() const { return X86SSELevel >= AVX2; }
 641   bool hasAVX512() const { return X86SSELevel >= AVX512F; }
 642   bool hasInt256() const { return hasAVX2(); }
 643   bool hasSSE4A() const { return HasSSE4A; }
 644   bool hasMMX() const { return X863DNowLevel >= MMX; }
 645   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
 646   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
 647   bool hasPOPCNT() const { return HasPOPCNT; }
 648   bool hasAES() const { return HasAES; }
 649   bool hasVAES() const { return HasVAES; }
 650   bool hasFXSR() const { return HasFXSR; }
 651   bool hasXSAVE() const { return HasXSAVE; }
 652   bool hasXSAVEOPT() const { return HasXSAVEOPT; }
 653   bool hasXSAVEC() const { return HasXSAVEC; }
 654   bool hasXSAVES() const { return HasXSAVES; }
 655   bool hasPCLMUL() const { return HasPCLMUL; }
 656   bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
 657   bool hasGFNI() const { return HasGFNI; }
 658   // Prefer FMA4 to FMA - its better for commutation/memory folding and
 659   // has equal or better performance on all supported targets.
 660   bool hasFMA() const { return HasFMA; }
 661   bool hasFMA4() const { return HasFMA4; }
 662   bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
 663   bool hasXOP() const { return HasXOP; }
 664   bool hasTBM() const { return HasTBM; }
 665   bool hasLWP() const { return HasLWP; }
 666   bool hasMOVBE() const { return HasMOVBE; }
 667   bool hasRDRAND() const { return HasRDRAND; }
 668   bool hasF16C() const { return HasF16C; }
 669   bool hasFSGSBase() const { return HasFSGSBase; }
 670   bool hasLZCNT() const { return HasLZCNT; }
 671   bool hasBMI() const { return HasBMI; }
 672   bool hasBMI2() const { return HasBMI2; }
 673   bool hasVBMI() const { return HasVBMI; }
 674   bool hasVBMI2() const { return HasVBMI2; }
 675   bool hasIFMA() const { return HasIFMA; }
 676   bool hasRTM() const { return HasRTM; }
 677   bool hasADX() const { return HasADX; }
 678   bool hasSHA() const { return HasSHA; }
 679   bool hasPRFCHW() const { return HasPRFCHW; }
 680   bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
 681   bool hasPrefetchW() const {
 682     // The PREFETCHW instruction was added with 3DNow but later CPUs gave it
 683     // its own CPUID bit as part of deprecating 3DNow. Intel eventually added
 684     // it and KNL has another that prefetches to L2 cache. We assume the
 685     // L1 version exists if the L2 version does.
 686     return has3DNow() || hasPRFCHW() || hasPREFETCHWT1();
 687   }
 688   bool hasSSEPrefetch() const {
 689     // We implicitly enable these when we have a write prefix supporting cache
 690     // level OR if we have prfchw, but don't already have a read prefetch from
 691     // 3dnow.
 692     return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
 693   }
 694   bool hasRDSEED() const { return HasRDSEED; }
 695   bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); }
 696   bool hasMWAITX() const { return HasMWAITX; }
 697   bool hasCLZERO() const { return HasCLZERO; }
 698   bool hasCLDEMOTE() const { return HasCLDEMOTE; }
 699   bool hasMOVDIRI() const { return HasMOVDIRI; }
 700   bool hasMOVDIR64B() const { return HasMOVDIR64B; }
 701   bool hasPTWRITE() const { return HasPTWRITE; }
 702   bool isSHLDSlow() const { return IsSHLDSlow; }
 703   bool isPMULLDSlow() const { return IsPMULLDSlow; }
 704   bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
 705   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
 706   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
 707   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
 708   bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
 709   bool useLeaForSP() const { return UseLeaForSP; }
 710   bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
 711   bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
 712   bool hasFastVariableCrossLaneShuffle() const {
 713     return HasFastVariableCrossLaneShuffle;
 714   }
 715   bool hasFastVariablePerLaneShuffle() const {
 716     return HasFastVariablePerLaneShuffle;
 717   }
 718   bool insertVZEROUPPER() const { return InsertVZEROUPPER; }
 719   bool hasFastGather() const { return HasFastGather; }
 720   bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
 721   bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
 722   bool hasFastLZCNT() const { return HasFastLZCNT; }
 723   bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
 724   bool hasFastBEXTR() const { return HasFastBEXTR; }
 725   bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
 726   bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
 727   bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
 728   bool hasFastMOVBE() const { return HasFastMOVBE; }
 729   bool hasMacroFusion() const { return HasMacroFusion; }
 730   bool hasBranchFusion() const { return HasBranchFusion; }
 731   bool hasERMSB() const { return HasERMSB; }
 732   bool hasFSRM() const { return HasFSRM; }
 733   bool hasSlowDivide32() const { return HasSlowDivide32; }
 734   bool hasSlowDivide64() const { return HasSlowDivide64; }
 735   bool padShortFunctions() const { return PadShortFunctions; }
 736   bool slowTwoMemOps() const { return SlowTwoMemOps; }
 737   bool LEAusesAG() const { return LEAUsesAG; }
 738   bool slowLEA() const { return SlowLEA; }
 739   bool slow3OpsLEA() const { return Slow3OpsLEA; }
 740   bool slowIncDec() const { return SlowIncDec; }
 741   bool hasCDI() const { return HasCDI; }
 742   bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
 743   bool hasPFI() const { return HasPFI; }
 744   bool hasERI() const { return HasERI; }
 745   bool hasDQI() const { return HasDQI; }
 746   bool hasBWI() const { return HasBWI; }
 747   bool hasVLX() const { return HasVLX; }
 748   bool hasFP16() const { return HasFP16; }
 749   bool hasPKU() const { return HasPKU; }
 750   bool hasVNNI() const { return HasVNNI; }
 751   bool hasBF16() const { return HasBF16; }
 752   bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
 753   bool hasBITALG() const { return HasBITALG; }
 754   bool hasSHSTK() const { return HasSHSTK; }
 755   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
 756   bool hasCLWB() const { return HasCLWB; }
 757   bool hasWBNOINVD() const { return HasWBNOINVD; }
 758   bool hasRDPID() const { return HasRDPID; }
 759   bool hasWAITPKG() const { return HasWAITPKG; }
 760   bool hasPCONFIG() const { return HasPCONFIG; }
 761   bool hasSGX() const { return HasSGX; }
 762   bool hasINVPCID() const { return HasINVPCID; }
 763   bool hasENQCMD() const { return HasENQCMD; }
 764   bool hasKL() const { return HasKL; }
 765   bool hasWIDEKL() const { return HasWIDEKL; }
 766   bool hasHRESET() const { return HasHRESET; }
 767   bool hasSERIALIZE() const { return HasSERIALIZE; }
 768   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
 769   bool hasUINTR() const { return HasUINTR; }
 770   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
 771   bool useRetpolineIndirectBranches() const {
 772     return UseRetpolineIndirectBranches;
 773   }
 774   bool hasAVXVNNI() const { return HasAVXVNNI; }
 775   bool hasAMXTILE() const { return HasAMXTILE; }
 776   bool hasAMXBF16() const { return HasAMXBF16; }
 777   bool hasAMXINT8() const { return HasAMXINT8; }
 778   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
 779
 780   // These are generic getters that OR together all of the thunk types
 781   // supported by the subtarget. Therefore useIndirectThunk*() will return true
 782   // if any respective thunk feature is enabled.
 783   bool useIndirectThunkCalls() const {
 784     return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity();
 785   }
 786   bool useIndirectThunkBranches() const {
 787     return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
 788   }
 789
 790   bool preferMaskRegisters() const { return PreferMaskRegisters; }
 791   bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; }
 792   bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; }
 793   bool useLVILoadHardening() const { return UseLVILoadHardening; }
 794   bool useSpeculativeExecutionSideEffectSuppression() const {
 795     return UseSpeculativeExecutionSideEffectSuppression;
 796   }
 797
 798   unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
 799   unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
 800
 801   // Helper functions to determine when we should allow widening to 512-bit
 802   // during codegen.
 803   // TODO: Currently we're always allowing widening on CPUs without VLX,
 804   // because for many cases we don't have a better option.
 805   bool canExtendTo512DQ() const {
 806     return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
 807   }
 808   bool canExtendTo512BW() const  {
 809     return hasBWI() && canExtendTo512DQ();
 810   }
 811
 812   // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
 813   // disable them in the legalizer.
 814   bool useAVX512Regs() const {
 815     return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
 816   }
 817
 818   bool useBWIRegs() const {
 819     return hasBWI() && useAVX512Regs();
 820   }
 821
 822   bool isXRaySupported() const override { return is64Bit(); }
 823
 824   /// TODO: to be removed later and replaced with suitable properties
 825   bool isAtom() const { return X86ProcFamily == IntelAtom; }
 826   bool isSLM() const { return X86ProcFamily == IntelSLM; }
 827   bool useSoftFloat() const { return UseSoftFloat; }
 828   bool useAA() const override { return UseAA; }
 829
 830   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
 831   /// no-sse2). There isn't any reason to disable it if the target processor
 832   /// supports it.
 833   bool hasMFence() const { return hasSSE2() || is64Bit(); }
 834
 835   const Triple &getTargetTriple() const { return TargetTriple; }
 836
 837   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 838   bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
 839   bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
 840   bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
 841   bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
 842
 843   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 844   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
 845   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 846
 847   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 848   bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
 849   bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
 850   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
 851   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
 852   bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
 853   bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
 854   bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
 855   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 856
 857   bool isTargetWindowsMSVC() const {
 858     return TargetTriple.isWindowsMSVCEnvironment();
 859   }
 860
 861   bool isTargetWindowsCoreCLR() const {
 862     return TargetTriple.isWindowsCoreCLREnvironment();
 863   }
 864
 865   bool isTargetWindowsCygwin() const {
 866     return TargetTriple.isWindowsCygwinEnvironment();
 867   }
 868
 869   bool isTargetWindowsGNU() const {
 870     return TargetTriple.isWindowsGNUEnvironment();
 871   }
 872
 873   bool isTargetWindowsItanium() const {
 874     return TargetTriple.isWindowsItaniumEnvironment();
 875   }
 876
 877   bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
 878
 879   bool isOSWindows() const { return TargetTriple.isOSWindows(); }
 880
 881   bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
 882
 883   bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
 884
 885   bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
 886   bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
 887
 888   bool isPICStyleStubPIC() const {
 889     return PICStyle == PICStyles::Style::StubPIC;
 890   }
 891
 892   bool isPositionIndependent() const;
 893
 894   bool isCallingConvWin64(CallingConv::ID CC) const {
 895     switch (CC) {
 896     // On Win64, all these conventions just use the default convention.
 897     case CallingConv::C:
 898     case CallingConv::Fast:
 899     case CallingConv::Tail:
 900     case CallingConv::Swift:
 901     case CallingConv::SwiftTail:
 902     case CallingConv::X86_FastCall:
 903     case CallingConv::X86_StdCall:
 904     case CallingConv::X86_ThisCall:
 905     case CallingConv::X86_VectorCall:
 906     case CallingConv::Intel_OCL_BI:
 907       return isTargetWin64();
 908     // This convention allows using the Win64 convention on other targets.
 909     case CallingConv::Win64:
 910       return true;
 911     // This convention allows using the SysV convention on Windows targets.
 912     case CallingConv::X86_64_SysV:
 913       return false;
 914     // Otherwise, who knows what this is.
 915     default:
 916       return false;
 917     }
 918   }
 919
 920   /// Classify a global variable reference for the current subtarget according
 921   /// to how we should reference it in a non-pcrel context.
 922   unsigned char classifyLocalReference(const GlobalValue *GV) const;
 923
 924   unsigned char classifyGlobalReference(const GlobalValue *GV,
 925                                         const Module &M) const;
 926   unsigned char classifyGlobalReference(const GlobalValue *GV) const;
 927
 928   /// Classify a global function reference for the current subtarget.
 929   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
 930                                                 const Module &M) const;
 931   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
 932
 933   /// Classify a blockaddress reference for the current subtarget according to
 934   /// how we should reference it in a non-pcrel context.
 935   unsigned char classifyBlockAddressReference() const;
 936
 937   /// Return true if the subtarget allows calls to immediate address.
 938   bool isLegalToCallImmediateAddr() const;
 939
 940   /// If we are using indirect thunks, we need to expand indirectbr to avoid it
 941   /// lowering to an actual indirect jump.
 942   bool enableIndirectBrExpand() const override {
 943     return useIndirectThunkBranches();
 944   }
 945
 946   /// Enable the MachineScheduler pass for all X86 subtargets.
 947   bool enableMachineScheduler() const override { return true; }
 948
 949   bool enableEarlyIfConversion() const override;
 950
 951   void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
 952                               &Mutations) const override;
 953
 954   AntiDepBreakMode getAntiDepBreakMode() const override {
 955     return TargetSubtargetInfo::ANTIDEP_CRITICAL;
 956   }
 957
 958   bool enableAdvancedRASplitCost() const override { return false; }
 959 };
 960
 961 } // end namespace llvm
 962
 963 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H