llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This file is part of the XCore Disassembler.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "TargetInfo/XCoreTargetInfo.h"
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 #define DEBUG_TYPE "xcore-disassembler"
  27
  28 typedef MCDisassembler::DecodeStatus DecodeStatus;
  29
  30 namespace {
  31
  32 /// A disassembler class for XCore.
  33 class XCoreDisassembler : public MCDisassembler {
  34 public:
  35   XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
  36     MCDisassembler(STI, Ctx) {}
  37
  38   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  39                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  40                               raw_ostream &CStream) const override;
  41 };
  42 }
  43
  44 static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
  45                               uint64_t &Size, uint16_t &Insn) {
  46   // We want to read exactly 2 Bytes of data.
  47   if (Bytes.size() < 2) {
  48     Size = 0;
  49     return false;
  50   }
  51   // Encoded as a little-endian 16-bit word in the stream.
  52   Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
  53   return true;
  54 }
  55
  56 static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
  57                               uint64_t &Size, uint32_t &Insn) {
  58   // We want to read exactly 4 Bytes of data.
  59   if (Bytes.size() < 4) {
  60     Size = 0;
  61     return false;
  62   }
  63   // Encoded as a little-endian 32-bit word in the stream.
  64   Insn =
  65       (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
  66   return true;
  67 }
  68
  69 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  70   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  71   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
  72   return *(RegInfo->getRegClass(RC).begin() + RegNo);
  73 }
  74
  75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  76                                               unsigned RegNo,
  77                                               uint64_t Address,
  78                                               const void *Decoder);
  79
  80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
  81                                              unsigned RegNo,
  82                                              uint64_t Address,
  83                                              const void *Decoder);
  84
  85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  86                                       uint64_t Address, const void *Decoder);
  87
  88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
  89                                         uint64_t Address, const void *Decoder);
  90
  91 static DecodeStatus Decode2RInstruction(MCInst &Inst,
  92                                         unsigned Insn,
  93                                         uint64_t Address,
  94                                         const void *Decoder);
  95
  96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
  97                                            unsigned Insn,
  98                                            uint64_t Address,
  99                                            const void *Decoder);
 100
 101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 102                                          unsigned Insn,
 103                                          uint64_t Address,
 104                                          const void *Decoder);
 105
 106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 107                                               unsigned Insn,
 108                                               uint64_t Address,
 109                                               const void *Decoder);
 110
 111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 112                                          unsigned Insn,
 113                                          uint64_t Address,
 114                                          const void *Decoder);
 115
 116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 117                                              unsigned Insn,
 118                                              uint64_t Address,
 119                                              const void *Decoder);
 120
 121 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 122                                                    unsigned Insn,
 123                                                    uint64_t Address,
 124                                                    const void *Decoder);
 125
 126 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 127                                          unsigned Insn,
 128                                          uint64_t Address,
 129                                          const void *Decoder);
 130
 131 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 132                                           unsigned Insn,
 133                                           uint64_t Address,
 134                                           const void *Decoder);
 135
 136 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 137                                         unsigned Insn,
 138                                         uint64_t Address,
 139                                         const void *Decoder);
 140
 141 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
 142                                            unsigned Insn,
 143                                            uint64_t Address,
 144                                            const void *Decoder);
 145
 146 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 147                                           unsigned Insn,
 148                                           uint64_t Address,
 149                                           const void *Decoder);
 150
 151 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 152                                               unsigned Insn,
 153                                               uint64_t Address,
 154                                               const void *Decoder);
 155
 156 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
 157                                          unsigned Insn,
 158                                          uint64_t Address,
 159                                          const void *Decoder);
 160
 161 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
 162                                                unsigned Insn,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
 167                                            unsigned Insn,
 168                                            uint64_t Address,
 169                                            const void *Decoder);
 170
 171 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
 172                                                unsigned Insn,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
 177                                          unsigned Insn,
 178                                          uint64_t Address,
 179                                          const void *Decoder);
 180
 181 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
 182                                          unsigned Insn,
 183                                          uint64_t Address,
 184                                          const void *Decoder);
 185
 186 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
 187                                                unsigned Insn,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
 192                                                      unsigned Insn,
 193                                                      uint64_t Address,
 194                                                      const void *Decoder);
 195
 196 #include "XCoreGenDisassemblerTables.inc"
 197
 198 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 199                                               unsigned RegNo,
 200                                               uint64_t Address,
 201                                               const void *Decoder)
 202 {
 203   if (RegNo > 11)
 204     return MCDisassembler::Fail;
 205   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 206   Inst.addOperand(MCOperand::createReg(Reg));
 207   return MCDisassembler::Success;
 208 }
 209
 210 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
 211                                              unsigned RegNo,
 212                                              uint64_t Address,
 213                                              const void *Decoder)
 214 {
 215   if (RegNo > 15)
 216     return MCDisassembler::Fail;
 217   unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
 218   Inst.addOperand(MCOperand::createReg(Reg));
 219   return MCDisassembler::Success;
 220 }
 221
 222 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 223                                       uint64_t Address, const void *Decoder) {
 224   if (Val > 11)
 225     return MCDisassembler::Fail;
 226   static const unsigned Values[] = {
 227     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 228   };
 229   Inst.addOperand(MCOperand::createImm(Values[Val]));
 230   return MCDisassembler::Success;
 231 }
 232
 233 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
 234                                         uint64_t Address, const void *Decoder) {
 235   Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
 236   return MCDisassembler::Success;
 237 }
 238
 239 static DecodeStatus
 240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 241   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 242   if (Combined < 27)
 243     return MCDisassembler::Fail;
 244   if (fieldFromInstruction(Insn, 5, 1)) {
 245     if (Combined == 31)
 246       return MCDisassembler::Fail;
 247     Combined += 5;
 248   }
 249   Combined -= 27;
 250   unsigned Op1High = Combined % 3;
 251   unsigned Op2High = Combined / 3;
 252   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 253   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 254   return MCDisassembler::Success;
 255 }
 256
 257 static DecodeStatus
 258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 259                      unsigned &Op3) {
 260   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 261   if (Combined >= 27)
 262     return MCDisassembler::Fail;
 263
 264   unsigned Op1High = Combined % 3;
 265   unsigned Op2High = (Combined / 3) % 3;
 266   unsigned Op3High = Combined / 9;
 267   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 268   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 269   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 270   return MCDisassembler::Success;
 271 }
 272
 273 static DecodeStatus
 274 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 275                          const void *Decoder) {
 276   // Try and decode as a 3R instruction.
 277   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 278   switch (Opcode) {
 279   case 0x0:
 280     Inst.setOpcode(XCore::STW_2rus);
 281     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 282   case 0x1:
 283     Inst.setOpcode(XCore::LDW_2rus);
 284     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 285   case 0x2:
 286     Inst.setOpcode(XCore::ADD_3r);
 287     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 288   case 0x3:
 289     Inst.setOpcode(XCore::SUB_3r);
 290     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 291   case 0x4:
 292     Inst.setOpcode(XCore::SHL_3r);
 293     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 294   case 0x5:
 295     Inst.setOpcode(XCore::SHR_3r);
 296     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 297   case 0x6:
 298     Inst.setOpcode(XCore::EQ_3r);
 299     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 300   case 0x7:
 301     Inst.setOpcode(XCore::AND_3r);
 302     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 303   case 0x8:
 304     Inst.setOpcode(XCore::OR_3r);
 305     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 306   case 0x9:
 307     Inst.setOpcode(XCore::LDW_3r);
 308     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 309   case 0x10:
 310     Inst.setOpcode(XCore::LD16S_3r);
 311     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 312   case 0x11:
 313     Inst.setOpcode(XCore::LD8U_3r);
 314     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 315   case 0x12:
 316     Inst.setOpcode(XCore::ADD_2rus);
 317     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 318   case 0x13:
 319     Inst.setOpcode(XCore::SUB_2rus);
 320     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 321   case 0x14:
 322     Inst.setOpcode(XCore::SHL_2rus);
 323     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 324   case 0x15:
 325     Inst.setOpcode(XCore::SHR_2rus);
 326     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 327   case 0x16:
 328     Inst.setOpcode(XCore::EQ_2rus);
 329     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 330   case 0x17:
 331     Inst.setOpcode(XCore::TSETR_3r);
 332     return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
 333   case 0x18:
 334     Inst.setOpcode(XCore::LSS_3r);
 335     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 336   case 0x19:
 337     Inst.setOpcode(XCore::LSU_3r);
 338     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 339   }
 340   return MCDisassembler::Fail;
 341 }
 342
 343 static DecodeStatus
 344 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 345                     const void *Decoder) {
 346   unsigned Op1, Op2;
 347   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 348   if (S != MCDisassembler::Success)
 349     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 350
 351   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 352   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 353   return S;
 354 }
 355
 356 static DecodeStatus
 357 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 358                        const void *Decoder) {
 359   unsigned Op1, Op2;
 360   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 361   if (S != MCDisassembler::Success)
 362     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 363
 364   Inst.addOperand(MCOperand::createImm(Op1));
 365   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 366   return S;
 367 }
 368
 369 static DecodeStatus
 370 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 371                      const void *Decoder) {
 372   unsigned Op1, Op2;
 373   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 374   if (S != MCDisassembler::Success)
 375     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 376
 377   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 378   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 379   return S;
 380 }
 381
 382 static DecodeStatus
 383 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 384                           const void *Decoder) {
 385   unsigned Op1, Op2;
 386   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 387   if (S != MCDisassembler::Success)
 388     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 389
 390   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 391   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 392   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 393   return S;
 394 }
 395
 396 static DecodeStatus
 397 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 398                      const void *Decoder) {
 399   unsigned Op1, Op2;
 400   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 401   if (S != MCDisassembler::Success)
 402     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 403
 404   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 405   Inst.addOperand(MCOperand::createImm(Op2));
 406   return S;
 407 }
 408
 409 static DecodeStatus
 410 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 411                          const void *Decoder) {
 412   unsigned Op1, Op2;
 413   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 414   if (S != MCDisassembler::Success)
 415     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 416
 417   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 418   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 419   return S;
 420 }
 421
 422 static DecodeStatus
 423 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 424                                const void *Decoder) {
 425   unsigned Op1, Op2;
 426   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 427   if (S != MCDisassembler::Success)
 428     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 429
 430   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 431   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 432   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 433   return S;
 434 }
 435
 436 static DecodeStatus
 437 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 438                           const void *Decoder) {
 439   // Try and decode as a L3R / L2RUS instruction.
 440   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
 441                     fieldFromInstruction(Insn, 27, 5) << 4;
 442   switch (Opcode) {
 443   case 0x0c:
 444     Inst.setOpcode(XCore::STW_l3r);
 445     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 446   case 0x1c:
 447     Inst.setOpcode(XCore::XOR_l3r);
 448     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 449   case 0x2c:
 450     Inst.setOpcode(XCore::ASHR_l3r);
 451     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 452   case 0x3c:
 453     Inst.setOpcode(XCore::LDAWF_l3r);
 454     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 455   case 0x4c:
 456     Inst.setOpcode(XCore::LDAWB_l3r);
 457     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 458   case 0x5c:
 459     Inst.setOpcode(XCore::LDA16F_l3r);
 460     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 461   case 0x6c:
 462     Inst.setOpcode(XCore::LDA16B_l3r);
 463     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 464   case 0x7c:
 465     Inst.setOpcode(XCore::MUL_l3r);
 466     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 467   case 0x8c:
 468     Inst.setOpcode(XCore::DIVS_l3r);
 469     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 470   case 0x9c:
 471     Inst.setOpcode(XCore::DIVU_l3r);
 472     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 473   case 0x10c:
 474     Inst.setOpcode(XCore::ST16_l3r);
 475     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 476   case 0x11c:
 477     Inst.setOpcode(XCore::ST8_l3r);
 478     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 479   case 0x12c:
 480     Inst.setOpcode(XCore::ASHR_l2rus);
 481     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 482   case 0x12d:
 483     Inst.setOpcode(XCore::OUTPW_l2rus);
 484     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 485   case 0x12e:
 486     Inst.setOpcode(XCore::INPW_l2rus);
 487     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 488   case 0x13c:
 489     Inst.setOpcode(XCore::LDAWF_l2rus);
 490     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 491   case 0x14c:
 492     Inst.setOpcode(XCore::LDAWB_l2rus);
 493     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 494   case 0x15c:
 495     Inst.setOpcode(XCore::CRC_l3r);
 496     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
 497   case 0x18c:
 498     Inst.setOpcode(XCore::REMS_l3r);
 499     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 500   case 0x19c:
 501     Inst.setOpcode(XCore::REMU_l3r);
 502     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 503   }
 504   return MCDisassembler::Fail;
 505 }
 506
 507 static DecodeStatus
 508 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 509                                const void *Decoder) {
 510   unsigned Op1, Op2;
 511   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 512                                         Op1, Op2);
 513   if (S != MCDisassembler::Success)
 514     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 515
 516   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 517   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 518   return S;
 519 }
 520
 521 static DecodeStatus
 522 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 523                                const void *Decoder) {
 524   unsigned Op1, Op2;
 525   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 526                                         Op1, Op2);
 527   if (S != MCDisassembler::Success)
 528     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 529
 530   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 531   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 532   return S;
 533 }
 534
 535 static DecodeStatus
 536 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 537                     const void *Decoder) {
 538   unsigned Op1, Op2, Op3;
 539   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 540   if (S == MCDisassembler::Success) {
 541     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 542     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 543     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 544   }
 545   return S;
 546 }
 547
 548 static DecodeStatus
 549 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 550                        const void *Decoder) {
 551   unsigned Op1, Op2, Op3;
 552   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 553   if (S == MCDisassembler::Success) {
 554     Inst.addOperand(MCOperand::createImm(Op1));
 555     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 556     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 557   }
 558   return S;
 559 }
 560
 561 static DecodeStatus
 562 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 563                       const void *Decoder) {
 564   unsigned Op1, Op2, Op3;
 565   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 566   if (S == MCDisassembler::Success) {
 567     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 568     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 569     Inst.addOperand(MCOperand::createImm(Op3));
 570   }
 571   return S;
 572 }
 573
 574 static DecodeStatus
 575 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 576                       const void *Decoder) {
 577   unsigned Op1, Op2, Op3;
 578   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 579   if (S == MCDisassembler::Success) {
 580     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 581     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 582     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 583   }
 584   return S;
 585 }
 586
 587 static DecodeStatus
 588 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 589                      const void *Decoder) {
 590   unsigned Op1, Op2, Op3;
 591   DecodeStatus S =
 592     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 593   if (S == MCDisassembler::Success) {
 594     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 595     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 596     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 597   }
 598   return S;
 599 }
 600
 601 static DecodeStatus
 602 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 603                            const void *Decoder) {
 604   unsigned Op1, Op2, Op3;
 605   DecodeStatus S =
 606   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 607   if (S == MCDisassembler::Success) {
 608     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 609     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 610     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 611     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 612   }
 613   return S;
 614 }
 615
 616 static DecodeStatus
 617 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 618                        const void *Decoder) {
 619   unsigned Op1, Op2, Op3;
 620   DecodeStatus S =
 621   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 622   if (S == MCDisassembler::Success) {
 623     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 624     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 625     Inst.addOperand(MCOperand::createImm(Op3));
 626   }
 627   return S;
 628 }
 629
 630 static DecodeStatus
 631 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 632                            const void *Decoder) {
 633   unsigned Op1, Op2, Op3;
 634   DecodeStatus S =
 635   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 636   if (S == MCDisassembler::Success) {
 637     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 638     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 639     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 640   }
 641   return S;
 642 }
 643
 644 static DecodeStatus
 645 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 646                      const void *Decoder) {
 647   unsigned Op1, Op2, Op3, Op4, Op5, Op6;
 648   DecodeStatus S =
 649     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 650   if (S != MCDisassembler::Success)
 651     return S;
 652   S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
 653   if (S != MCDisassembler::Success)
 654     return S;
 655   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 656   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 657   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 658   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 659   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 660   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
 661   return S;
 662 }
 663
 664 static DecodeStatus
 665 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 666                      const void *Decoder) {
 667   // Try and decode as a L6R instruction.
 668   Inst.clear();
 669   unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
 670   switch (Opcode) {
 671   case 0x00:
 672     Inst.setOpcode(XCore::LMUL_l6r);
 673     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
 674   }
 675   return MCDisassembler::Fail;
 676 }
 677
 678 static DecodeStatus
 679 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 680                      const void *Decoder) {
 681   unsigned Op1, Op2, Op3, Op4, Op5;
 682   DecodeStatus S =
 683     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 684   if (S != MCDisassembler::Success)
 685     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 686   S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
 687   if (S != MCDisassembler::Success)
 688     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 689
 690   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 691   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 692   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 693   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 694   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 695   return S;
 696 }
 697
 698 static DecodeStatus
 699 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 700                            const void *Decoder) {
 701   unsigned Op1, Op2, Op3;
 702   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 703   DecodeStatus S =
 704     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 705   if (S == MCDisassembler::Success) {
 706     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 707     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 708   }
 709   if (S == MCDisassembler::Success) {
 710     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 711     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 712     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 713   }
 714   return S;
 715 }
 716
 717 static DecodeStatus
 718 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 719                                  const void *Decoder) {
 720   unsigned Op1, Op2, Op3;
 721   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 722   DecodeStatus S =
 723   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 724   if (S == MCDisassembler::Success) {
 725     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 726     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 727   }
 728   if (S == MCDisassembler::Success) {
 729     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 730     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 731     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 732     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 733   }
 734   return S;
 735 }
 736
 737 MCDisassembler::DecodeStatus
 738 XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size,
 739                                   ArrayRef<uint8_t> Bytes, uint64_t Address,
 740                                   raw_ostream &cStream) const {
 741   uint16_t insn16;
 742
 743   if (!readInstruction16(Bytes, Address, Size, insn16)) {
 744     return Fail;
 745   }
 746
 747   // Calling the auto-generated decoder function.
 748   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 749                                           Address, this, STI);
 750   if (Result != Fail) {
 751     Size = 2;
 752     return Result;
 753   }
 754
 755   uint32_t insn32;
 756
 757   if (!readInstruction32(Bytes, Address, Size, insn32)) {
 758     return Fail;
 759   }
 760
 761   // Calling the auto-generated decoder function.
 762   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 763   if (Result != Fail) {
 764     Size = 4;
 765     return Result;
 766   }
 767
 768   return Fail;
 769 }
 770
 771 static MCDisassembler *createXCoreDisassembler(const Target &T,
 772                                                const MCSubtargetInfo &STI,
 773                                                MCContext &Ctx) {
 774   return new XCoreDisassembler(STI, Ctx);
 775 }
 776
 777 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreDisassembler() {
 778   // Register the disassembler.
 779   TargetRegistry::RegisterMCDisassembler(getTheXCoreTarget(),
 780                                          createXCoreDisassembler);
 781 }