| blob | dcd80c403e451a56f929eeda20d3bf23257df6f6 |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3 #
4 # Test widening and narrowing on test bit operations using subregister copies
5 # or SUBREG_TO_REG.
6 --- |
7 @glob = external dso_local unnamed_addr global i1, align 4
8 define void @s1_no_copy() { ret void }
9 define void @s16_no_copy() { ret void }
10 define void @p0_no_copy() { ret void }
11 define void @widen_s32_to_s64() { ret void }
12 define void @widen_s16_to_s64() { ret void }
13 define void @narrow_s64_to_s32() { ret void }
15 ...
16 ---
17 name: s1_no_copy
18 alignment: 4
19 legalized: true
20 regBankSelected: true
21 tracksRegLiveness: true
22 body: |
23 ; CHECK-LABEL: name: s1_no_copy
24 ; CHECK: bb.0:
25 ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
26 ; CHECK: %narrow:gpr32 = IMPLICIT_DEF
27 ; CHECK: TBNZW %narrow, 0, %bb.1
28 ; CHECK: B %bb.0
29 ; CHECK: bb.1:
30 ; CHECK: RET_ReallyLR
31 bb.0:
32 successors: %bb.0, %bb.1
33 %narrow:gpr(s1) = G_IMPLICIT_DEF
35 ; There should be no copy here, because the s1 can be selected to a GPR32.
36 G_BRCOND %narrow(s1), %bb.1
37 G_BR %bb.0
38 bb.1:
39 RET_ReallyLR
40 ...
41 ---
42 name: s16_no_copy
43 alignment: 4
44 legalized: true
45 regBankSelected: true
46 tracksRegLiveness: true
47 body: |
48 ; CHECK-LABEL: name: s16_no_copy
49 ; CHECK: bb.0:
50 ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
51 ; CHECK: %narrow:gpr32 = IMPLICIT_DEF
52 ; CHECK: TBNZW %narrow, 0, %bb.1
53 ; CHECK: B %bb.0
54 ; CHECK: bb.1:
55 ; CHECK: RET_ReallyLR
56 bb.0:
57 successors: %bb.0, %bb.1
58 %narrow:gpr(s16) = G_IMPLICIT_DEF
59 %trunc:gpr(s1) = G_TRUNC %narrow(s16)
61 ; Look through the G_TRUNC to get the G_IMPLICIT_DEF. We don't need a
62 ; SUBREG_TO_REG here, because the s16 will end up on a 32-bit register.
63 G_BRCOND %trunc(s1), %bb.1
64 G_BR %bb.0
65 bb.1:
66 RET_ReallyLR
67 ...
68 ---
69 name: p0_no_copy
70 alignment: 4
71 legalized: true
72 regBankSelected: true
73 tracksRegLiveness: true
74 body: |
75 ; CHECK-LABEL: name: p0_no_copy
76 ; CHECK: bb.0:
77 ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
78 ; CHECK: %glob:gpr64common = MOVaddr target-flags(aarch64-page) @glob, target-flags(aarch64-pageoff, aarch64-nc) @glob
79 ; CHECK: %load:gpr32 = LDRBBui %glob, 0 :: (dereferenceable load (s8) from @glob, align 4)
80 ; CHECK: TBNZW %load, 0, %bb.1
81 ; CHECK: B %bb.0
82 ; CHECK: bb.1:
83 ; CHECK: RET_ReallyLR
84 bb.0:
85 successors: %bb.0, %bb.1
86 %glob:gpr(p0) = G_GLOBAL_VALUE @glob
87 %load:gpr(s8) = G_LOAD %glob(p0) :: (dereferenceable load (s8) from @glob, align 4)
88 %trunc:gpr(s1) = G_TRUNC %load(s8)
90 ; Look through G_TRUNC to get the load. The load is into a s8, which will
91 ; be selected to a GPR32, so we don't need a copy.
92 G_BRCOND %trunc(s1), %bb.1
93 G_BR %bb.0
94 bb.1:
95 RET_ReallyLR
96 ...
97 ---
98 name: widen_s32_to_s64
99 alignment: 4
100 legalized: true
101 regBankSelected: true
102 tracksRegLiveness: true
103 body: |
104 ; CHECK-LABEL: name: widen_s32_to_s64
105 ; CHECK: bb.0:
106 ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
107 ; CHECK: liveins: $w0
108 ; CHECK: %reg:gpr32all = COPY $w0
109 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, %reg, %subreg.sub_32
110 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
111 ; CHECK: TBZX [[COPY]], 33, %bb.1
112 ; CHECK: B %bb.0
113 ; CHECK: bb.1:
114 ; CHECK: RET_ReallyLR
115 bb.0:
116 successors: %bb.0, %bb.1
117 liveins: $w0
118 %reg:gpr(s32) = COPY $w0
119 %zext:gpr(s64) = G_ZEXT %reg(s32)
120 %bit:gpr(s64) = G_CONSTANT i64 8589934592
121 %zero:gpr(s64) = G_CONSTANT i64 0
122 %and:gpr(s64) = G_AND %zext, %bit
123 %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
125 ; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
126 ; bit 33. The subregister should be sub_32.
127 %trunc:gpr(s1) = G_TRUNC %cmp(s32)
128 G_BRCOND %trunc(s1), %bb.1
129 G_BR %bb.0
130 bb.1:
131 RET_ReallyLR
132 ...
133 ---
134 name: widen_s16_to_s64
135 alignment: 4
136 legalized: true
137 regBankSelected: true
138 tracksRegLiveness: true
139 body: |
140 ; CHECK-LABEL: name: widen_s16_to_s64
141 ; CHECK: bb.0:
142 ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
143 ; CHECK: %reg:gpr32 = IMPLICIT_DEF
144 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, %reg, %subreg.sub_32
145 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
146 ; CHECK: TBZX [[COPY]], 33, %bb.1
147 ; CHECK: B %bb.0
148 ; CHECK: bb.1:
149 ; CHECK: RET_ReallyLR
150 bb.0:
151 successors: %bb.0, %bb.1
152 %reg:gpr(s16) = G_IMPLICIT_DEF
153 %zext:gpr(s64) = G_ZEXT %reg(s16)
154 %bit:gpr(s64) = G_CONSTANT i64 8589934592
155 %zero:gpr(s64) = G_CONSTANT i64 0
156 %and:gpr(s64) = G_AND %zext, %bit
157 %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
159 ; We should widen using a SUBREG_TO_REG here, because we need a TBZX to get
160 ; bit 33. The subregister should be sub_32, because s16 will end up on a
161 ; GPR32.
162 %trunc:gpr(s1) = G_TRUNC %cmp(s32)
163 G_BRCOND %trunc(s1), %bb.1
164 G_BR %bb.0
165 bb.1:
166 RET_ReallyLR
167 ...
168 ---
169 name: narrow_s64_to_s32
170 alignment: 4
171 legalized: true
172 regBankSelected: true
173 tracksRegLiveness: true
174 body: |
175 ; CHECK-LABEL: name: narrow_s64_to_s32
176 ; CHECK: bb.0:
177 ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
178 ; CHECK: liveins: $x0
179 ; CHECK: %wide:gpr64all = COPY $x0
180 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %wide.sub_32
181 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
182 ; CHECK: TBNZW [[COPY1]], 0, %bb.1
183 ; CHECK: B %bb.0
184 ; CHECK: bb.1:
185 ; CHECK: RET_ReallyLR
186 bb.0:
187 successors: %bb.0, %bb.1
188 liveins: $x0
189 %wide:gpr(s64) = COPY $x0
191 ; We should narrow using a subregister copy here.
192 %trunc:gpr(s1) = G_TRUNC %wide(s64)
193 G_BRCOND %trunc(s1), %bb.1
194 G_BR %bb.0
195 bb.1:
196 RET_ReallyLR