1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s
3 target triple = "arm64--"
5 ; AArch64InstrInfo::optimizeCondBranch() optimizes the
6 ; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction.
7 ; It forgot to clear the a flag resulting in a MachineVerifier complaint.
9 ; Writing a stable/simple test is tricky since most tbz instructions are already
10 ; formed in SelectionDAG, optimizeCondBranch() only triggers if the and
11 ; instruction is in a different block than the conditional jump.
16 ; CHECK-NEXT: mov w8, #1
17 ; CHECK-NEXT: cbnz w8, .LBB0_3
18 ; CHECK-NEXT: // %bb.1: // %b1
19 ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
20 ; CHECK-NEXT: .cfi_def_cfa_offset 16
21 ; CHECK-NEXT: .cfi_offset w30, -16
22 ; CHECK-NEXT: cbz wzr, .LBB0_4
23 ; CHECK-NEXT: // %bb.2: // %b3
24 ; CHECK-NEXT: ldr w8, [x8]
25 ; CHECK-NEXT: and w0, w8, #0x100
26 ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
27 ; CHECK-NEXT: cbz w0, .LBB0_5
28 ; CHECK-NEXT: .LBB0_3: // %common.ret.sink.split
29 ; CHECK-NEXT: b extfunc
30 ; CHECK-NEXT: .LBB0_4: // %b2
31 ; CHECK-NEXT: bl extfunc
32 ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
33 ; CHECK-NEXT: cbnz w0, .LBB0_3
34 ; CHECK-NEXT: .LBB0_5: // %common.ret
36 %c0 = icmp sgt i64 0, 0
37 br i1 %c0, label %b1, label %b6
40 br i1 undef, label %b3, label %b2
43 %v0 = tail call i32 @extfunc()
47 %v1 = load i32, i32* undef, align 4
48 %v2 = and i32 %v1, 256
52 %v3 = phi i32 [ %v2, %b3 ], [ %v0, %b2 ]
53 %c1 = icmp eq i32 %v3, 0
54 br i1 %c1, label %b8, label %b7
57 tail call i32 @extfunc()
61 tail call i32 @extfunc()
68 declare i32 @extfunc()