| blob | 0d63fa216bfde09e5acf512b73e81e72b82c3caf |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
4 define i1 @test_srem_odd(i29 %X) nounwind {
5 ; CHECK-LABEL: test_srem_odd:
6 ; CHECK: // %bb.0:
7 ; CHECK-NEXT: mov w8, #33099
8 ; CHECK-NEXT: mov w9, #24493
9 ; CHECK-NEXT: movk w8, #8026, lsl #16
10 ; CHECK-NEXT: movk w9, #41, lsl #16
11 ; CHECK-NEXT: madd w8, w0, w8, w9
12 ; CHECK-NEXT: mov w9, #48987
13 ; CHECK-NEXT: and w8, w8, #0x1fffffff
14 ; CHECK-NEXT: movk w9, #82, lsl #16
15 ; CHECK-NEXT: cmp w8, w9
16 ; CHECK-NEXT: cset w0, lo
17 ; CHECK-NEXT: ret
18 %srem = srem i29 %X, 99
19 %cmp = icmp eq i29 %srem, 0
20 ret i1 %cmp
21 }
23 define i1 @test_srem_even(i4 %X) nounwind {
24 ; CHECK-LABEL: test_srem_even:
25 ; CHECK: // %bb.0:
26 ; CHECK-NEXT: mov w9, #43691
27 ; CHECK-NEXT: sbfx w8, w0, #0, #4
28 ; CHECK-NEXT: movk w9, #10922, lsl #16
29 ; CHECK-NEXT: smull x9, w8, w9
30 ; CHECK-NEXT: lsr x10, x9, #63
31 ; CHECK-NEXT: lsr x9, x9, #32
32 ; CHECK-NEXT: add w9, w9, w10
33 ; CHECK-NEXT: mov w10, #6
34 ; CHECK-NEXT: msub w8, w9, w10, w8
35 ; CHECK-NEXT: cmp w8, #1
36 ; CHECK-NEXT: cset w0, eq
37 ; CHECK-NEXT: ret
38 %srem = srem i4 %X, 6
39 %cmp = icmp eq i4 %srem, 1
40 ret i1 %cmp
41 }
43 define i1 @test_srem_pow2_setne(i6 %X) nounwind {
44 ; CHECK-LABEL: test_srem_pow2_setne:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: sbfx w8, w0, #0, #6
47 ; CHECK-NEXT: ubfx w8, w8, #9, #2
48 ; CHECK-NEXT: add w8, w0, w8
49 ; CHECK-NEXT: and w8, w8, #0x3c
50 ; CHECK-NEXT: sub w8, w0, w8
51 ; CHECK-NEXT: tst w8, #0x3f
52 ; CHECK-NEXT: cset w0, ne
53 ; CHECK-NEXT: ret
54 %srem = srem i6 %X, 4
55 %cmp = icmp ne i6 %srem, 0
56 ret i1 %cmp
57 }
59 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
60 ; CHECK-LABEL: test_srem_vec:
61 ; CHECK: // %bb.0:
62 ; CHECK-NEXT: mov x10, #7281
63 ; CHECK-NEXT: movk x10, #29127, lsl #16
64 ; CHECK-NEXT: movk x10, #50972, lsl #32
65 ; CHECK-NEXT: sbfx x9, x2, #0, #33
66 ; CHECK-NEXT: movk x10, #7281, lsl #48
67 ; CHECK-NEXT: mov x11, #8589934591
68 ; CHECK-NEXT: mov x12, #7282
69 ; CHECK-NEXT: movk x12, #29127, lsl #16
70 ; CHECK-NEXT: dup v0.2d, x11
71 ; CHECK-NEXT: adrp x11, .LCPI3_0
72 ; CHECK-NEXT: smulh x10, x9, x10
73 ; CHECK-NEXT: movk x12, #50972, lsl #32
74 ; CHECK-NEXT: ldr q1, [x11, :lo12:.LCPI3_0]
75 ; CHECK-NEXT: adrp x11, .LCPI3_1
76 ; CHECK-NEXT: sub x10, x10, x9
77 ; CHECK-NEXT: sbfx x8, x1, #0, #33
78 ; CHECK-NEXT: movk x12, #7281, lsl #48
79 ; CHECK-NEXT: ldr q2, [x11, :lo12:.LCPI3_1]
80 ; CHECK-NEXT: asr x11, x10, #3
81 ; CHECK-NEXT: add x10, x11, x10, lsr #63
82 ; CHECK-NEXT: smulh x11, x8, x12
83 ; CHECK-NEXT: add x11, x11, x11, lsr #63
84 ; CHECK-NEXT: add x11, x11, x11, lsl #3
85 ; CHECK-NEXT: sub x8, x8, x11
86 ; CHECK-NEXT: sbfx x11, x0, #0, #33
87 ; CHECK-NEXT: smulh x12, x11, x12
88 ; CHECK-NEXT: add x12, x12, x12, lsr #63
89 ; CHECK-NEXT: add x12, x12, x12, lsl #3
90 ; CHECK-NEXT: sub x11, x11, x12
91 ; CHECK-NEXT: add x10, x10, x10, lsl #3
92 ; CHECK-NEXT: fmov d3, x11
93 ; CHECK-NEXT: add x9, x9, x10
94 ; CHECK-NEXT: mov v3.d[1], x8
95 ; CHECK-NEXT: fmov d4, x9
96 ; CHECK-NEXT: and v4.16b, v4.16b, v0.16b
97 ; CHECK-NEXT: and v0.16b, v3.16b, v0.16b
98 ; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d
99 ; CHECK-NEXT: cmeq v1.2d, v4.2d, v2.2d
100 ; CHECK-NEXT: mvn v0.16b, v0.16b
101 ; CHECK-NEXT: mvn v1.16b, v1.16b
102 ; CHECK-NEXT: xtn v0.2s, v0.2d
103 ; CHECK-NEXT: xtn v1.2s, v1.2d
104 ; CHECK-NEXT: mov w1, v0.s[1]
105 ; CHECK-NEXT: fmov w0, s0
106 ; CHECK-NEXT: fmov w2, s1
107 ; CHECK-NEXT: ret
108 %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
109 %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
110 ret <3 x i1> %cmp
111 }