| blob | 4b5a8a81a8c42ee245e50e9e70527cb9ece978ef |
1 ; RUN: llc -aarch64-sve-vector-bits-min=128 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=16 -check-prefix=NO_SVE
2 ; RUN: llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=32
3 ; RUN: llc -aarch64-sve-vector-bits-min=384 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=32
4 ; RUN: llc -aarch64-sve-vector-bits-min=512 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
5 ; RUN: llc -aarch64-sve-vector-bits-min=640 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
6 ; RUN: llc -aarch64-sve-vector-bits-min=768 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
7 ; RUN: llc -aarch64-sve-vector-bits-min=896 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
8 ; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
9 ; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
10 ; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
11 ; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
12 ; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
13 ; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
14 ; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
15 ; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
16 ; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -D#VBYTES=256 -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048
18 target triple = "aarch64-unknown-linux-gnu"
20 ; Don't use SVE when its registers are no bigger than NEON.
21 ; NO_SVE-NOT: ptrue
23 ; Don't use SVE for 64-bit vectors.
24 define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
25 ; CHECK: select_v8i8:
26 ; CHECK: bif v0.8b, v1.8b, v2.8b
27 ; CHECK: ret
28 %sel = select <8 x i1> %mask, <8 x i8> %op1, <8 x i8> %op2
29 ret <8 x i8> %sel
30 }
32 ; Don't use SVE for 128-bit vectors.
33 define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 {
34 ; CHECK: select_v16i8:
35 ; CHECK: bif v0.16b, v1.16b, v2.16b
36 ; CHECK: ret
37 %sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op2
38 ret <16 x i8> %sel
39 }
41 define void @select_v32i8(<32 x i8>* %a, <32 x i8>* %b, <32 x i1>* %c) #0 {
42 ; CHECK: select_v32i8:
43 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,32)]]
44 ; CHECK: ptrue [[PG1:p[0-9]+]].b
45 ; CHECK: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
46 ; CHECK-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
47 ; CHECK-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
48 ; CHECK-NEXT: and [[AND:z[0-9]+]].b, [[MASK]].b, #0x1
49 ; CHECK-NEXT: cmpne [[COND:p[0-9]+]].b, [[PG1]]/z, [[AND]].b, #0
50 ; CHECK-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
51 ; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
52 ; CHECK: ret
53 %mask = load <32 x i1>, <32 x i1>* %c
54 %op1 = load <32 x i8>, <32 x i8>* %a
55 %op2 = load <32 x i8>, <32 x i8>* %b
56 %sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op2
57 store <32 x i8> %sel, <32 x i8>* %a
58 ret void
59 }
61 define void @select_v64i8(<64 x i8>* %a, <64 x i8>* %b, <64 x i1>* %c) #0 {
62 ; CHECK: select_v64i8:
63 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,64)]]
64 ; CHECK: ptrue [[PG1:p[0-9]+]].b
65 ; VBITS_GE_512: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
66 ; VBITS_GE_512-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
67 ; VBITS_GE_512-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
68 ; VBITS_GE_512-NEXT: and [[AND:z[0-9]+]].b, [[MASK]].b, #0x1
69 ; VBITS_GE_512-NEXT: cmpne [[COND:p[0-9]+]].b, [[PG1]]/z, [[AND]].b, #0
70 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
71 ; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
72 ; VBITS_GE_512: ret
73 %mask = load <64 x i1>, <64 x i1>* %c
74 %op1 = load <64 x i8>, <64 x i8>* %a
75 %op2 = load <64 x i8>, <64 x i8>* %b
76 %sel = select <64 x i1> %mask, <64 x i8> %op1, <64 x i8> %op2
77 store <64 x i8> %sel, <64 x i8>* %a
78 ret void
79 }
81 define void @select_v128i8(<128 x i8>* %a, <128 x i8>* %b, <128 x i1>* %c) #0 {
82 ; CHECK: select_v128i8:
83 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,128)]]
84 ; CHECK: ptrue [[PG1:p[0-9]+]].b
85 ; VBITS_GE_1024: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
86 ; VBITS_GE_1024-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
87 ; VBITS_GE_1024-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
88 ; VBITS_GE_1024-NEXT: and [[AND:z[0-9]+]].b, [[MASK]].b, #0x1
89 ; VBITS_GE_1024-NEXT: cmpne [[COND:p[0-9]+]].b, [[PG1]]/z, [[AND]].b, #0
90 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
91 ; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
92 ; VBITS_GE_1024: ret
93 %mask = load <128 x i1>, <128 x i1>* %c
94 %op1 = load <128 x i8>, <128 x i8>* %a
95 %op2 = load <128 x i8>, <128 x i8>* %b
96 %sel = select <128 x i1> %mask, <128 x i8> %op1, <128 x i8> %op2
97 store <128 x i8> %sel, <128 x i8>* %a
98 ret void
99 }
101 define void @select_v256i8(<256 x i8>* %a, <256 x i8>* %b, <256 x i1>* %c) #0 {
102 ; CHECK: select_v256i8:
103 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,256)]]
104 ; CHECK: ptrue [[PG1:p[0-9]+]].b
105 ; VBITS_GE_2048: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
106 ; VBITS_GE_2048-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
107 ; VBITS_GE_2048-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
108 ; VBITS_GE_2048-NEXT: and [[AND:z[0-9]+]].b, [[MASK]].b, #0x1
109 ; VBITS_GE_2048-NEXT: cmpne [[COND:p[0-9]+]].b, [[PG1]]/z, [[AND]].b, #0
110 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].b, [[COND]], [[OP1]].b, [[OP2]].b
111 ; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
112 ; VBITS_GE_2048: ret
113 %mask = load <256 x i1>, <256 x i1>* %c
114 %op1 = load <256 x i8>, <256 x i8>* %a
115 %op2 = load <256 x i8>, <256 x i8>* %b
116 %sel = select <256 x i1> %mask, <256 x i8> %op1, <256 x i8> %op2
117 store <256 x i8> %sel, <256 x i8>* %a
118 ret void
119 }
121 ; Don't use SVE for 64-bit vectors.
122 define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #0 {
123 ; CHECK: select_v4i16:
124 ; CHECK: bif v0.8b, v1.8b, v2.8b
125 ; CHECK: ret
126 %sel = select <4 x i1> %mask, <4 x i16> %op1, <4 x i16> %op2
127 ret <4 x i16> %sel
128 }
130 ; Don't use SVE for 128-bit vectors.
131 define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 {
132 ; CHECK: select_v8i16:
133 ; CHECK: bif v0.16b, v1.16b, v2.16b
134 ; CHECK: ret
135 %sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2
136 ret <8 x i16> %sel
137 }
139 define void @select_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i1>* %c) #0 {
140 ; CHECK: select_v16i16:
141 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
142 ; CHECK: ptrue [[PG1:p[0-9]+]].h
143 ; CHECK: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
144 ; CHECK-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
145 ; CHECK-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
146 ; CHECK-NEXT: and [[AND:z[0-9]+]].h, [[MASK]].h, #0x1
147 ; CHECK-NEXT: cmpne [[COND:p[0-9]+]].h, [[PG1]]/z, [[AND]].h, #0
148 ; CHECK-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
149 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
150 ; CHECK: ret
151 %mask = load <16 x i1>, <16 x i1>* %c
152 %op1 = load <16 x i16>, <16 x i16>* %a
153 %op2 = load <16 x i16>, <16 x i16>* %b
154 %sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2
155 store <16 x i16> %sel, <16 x i16>* %a
156 ret void
157 }
159 define void @select_v32i16(<32 x i16>* %a, <32 x i16>* %b, <32 x i1>* %c) #0 {
160 ; CHECK: select_v32i16:
161 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
162 ; CHECK: ptrue [[PG1:p[0-9]+]].h
163 ; VBITS_GE_512: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
164 ; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
165 ; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
166 ; VBITS_GE_512-NEXT: and [[AND:z[0-9]+]].h, [[MASK]].h, #0x1
167 ; VBITS_GE_512-NEXT: cmpne [[COND:p[0-9]+]].h, [[PG1]]/z, [[AND]].h, #0
168 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
169 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
170 ; VBITS_GE_512: ret
171 %mask = load <32 x i1>, <32 x i1>* %c
172 %op1 = load <32 x i16>, <32 x i16>* %a
173 %op2 = load <32 x i16>, <32 x i16>* %b
174 %sel = select <32 x i1> %mask, <32 x i16> %op1, <32 x i16> %op2
175 store <32 x i16> %sel, <32 x i16>* %a
176 ret void
177 }
179 define void @select_v64i16(<64 x i16>* %a, <64 x i16>* %b, <64 x i1>* %c) #0 {
180 ; CHECK: select_v64i16:
181 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
182 ; CHECK: ptrue [[PG1:p[0-9]+]].h
183 ; VBITS_GE_1024: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
184 ; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
185 ; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
186 ; VBITS_GE_1024-NEXT: and [[AND:z[0-9]+]].h, [[MASK]].h, #0x1
187 ; VBITS_GE_1024-NEXT: cmpne [[COND:p[0-9]+]].h, [[PG1]]/z, [[AND]].h, #0
188 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
189 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
190 ; VBITS_GE_1024: ret
191 %mask = load <64 x i1>, <64 x i1>* %c
192 %op1 = load <64 x i16>, <64 x i16>* %a
193 %op2 = load <64 x i16>, <64 x i16>* %b
194 %sel = select <64 x i1> %mask, <64 x i16> %op1, <64 x i16> %op2
195 store <64 x i16> %sel, <64 x i16>* %a
196 ret void
197 }
199 define void @select_v128i16(<128 x i16>* %a, <128 x i16>* %b, <128 x i1>* %c) #0 {
200 ; CHECK: select_v128i16:
201 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
202 ; CHECK: ptrue [[PG1:p[0-9]+]].h
203 ; VBITS_GE_2048: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
204 ; VBITS_GE_2048-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
205 ; VBITS_GE_2048-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
206 ; VBITS_GE_2048-NEXT: and [[AND:z[0-9]+]].h, [[MASK]].h, #0x1
207 ; VBITS_GE_2048-NEXT: cmpne [[COND:p[0-9]+]].h, [[PG1]]/z, [[AND]].h, #0
208 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].h, [[COND]], [[OP1]].h, [[OP2]].h
209 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
210 ; VBITS_GE_2048: ret
211 %mask = load <128 x i1>, <128 x i1>* %c
212 %op1 = load <128 x i16>, <128 x i16>* %a
213 %op2 = load <128 x i16>, <128 x i16>* %b
214 %sel = select <128 x i1> %mask, <128 x i16> %op1, <128 x i16> %op2
215 store <128 x i16> %sel, <128 x i16>* %a
216 ret void
217 }
219 ; Don't use SVE for 64-bit vectors.
220 define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #0 {
221 ; CHECK: select_v2i32:
222 ; CHECK: bif v0.8b, v1.8b, v2.8b
223 ; CHECK: ret
224 %sel = select <2 x i1> %mask, <2 x i32> %op1, <2 x i32> %op2
225 ret <2 x i32> %sel
226 }
228 ; Don't use SVE for 128-bit vectors.
229 define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 {
230 ; CHECK: select_v4i32:
231 ; CHECK: bif v0.16b, v1.16b, v2.16b
232 ; CHECK: ret
233 %sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2
234 ret <4 x i32> %sel
235 }
237 define void @select_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %c) #0 {
238 ; CHECK: select_v8i32:
239 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
240 ; CHECK: ptrue [[PG1:p[0-9]+]].s
241 ; CHECK: ld1w { [[MASK:z[0-9]+]].s }, [[PG]]/z, [x9]
242 ; CHECK-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
243 ; CHECK-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
244 ; CHECK-NEXT: and [[AND:z[0-9]+]].s, [[MASK]].s, #0x1
245 ; CHECK-NEXT: cmpne [[COND:p[0-9]+]].s, [[PG1]]/z, [[AND]].s, #0
246 ; CHECK-NEXT: sel [[RES:z[0-9]+]].s, [[COND]], [[OP1]].s, [[OP2]].s
247 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
248 ; CHECK: ret
249 %mask = load <8 x i1>, <8 x i1>* %c
250 %op1 = load <8 x i32>, <8 x i32>* %a
251 %op2 = load <8 x i32>, <8 x i32>* %b
252 %sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2
253 store <8 x i32> %sel, <8 x i32>* %a
254 ret void
255 }
257 define void @select_v16i32(<16 x i32>* %a, <16 x i32>* %b, <16 x i1>* %c) #0 {
258 ; CHECK: select_v16i32:
259 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
260 ; CHECK: ptrue [[PG1:p[0-9]+]].s
261 ; VBITS_GE_512: ld1w { [[MASK:z[0-9]+]].s }, [[PG]]/z, [x9]
262 ; VBITS_GE_512-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
263 ; VBITS_GE_512-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
264 ; VBITS_GE_512-NEXT: and [[AND:z[0-9]+]].s, [[MASK]].s, #0x1
265 ; VBITS_GE_512-NEXT: cmpne [[COND:p[0-9]+]].s, [[PG1]]/z, [[AND]].s, #0
266 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].s, [[COND]], [[OP1]].s, [[OP2]].s
267 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
268 ; VBITS_GE_512: ret
269 %mask = load <16 x i1>, <16 x i1>* %c
270 %op1 = load <16 x i32>, <16 x i32>* %a
271 %op2 = load <16 x i32>, <16 x i32>* %b
272 %sel = select <16 x i1> %mask, <16 x i32> %op1, <16 x i32> %op2
273 store <16 x i32> %sel, <16 x i32>* %a
274 ret void
275 }
277 define void @select_v32i32(<32 x i32>* %a, <32 x i32>* %b, <32 x i1>* %c) #0 {
278 ; CHECK: select_v32i32:
279 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
280 ; CHECK: ptrue [[PG1:p[0-9]+]].s
281 ; VBITS_GE_1024: ld1w { [[MASK:z[0-9]+]].s }, [[PG]]/z, [x9]
282 ; VBITS_GE_1024-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
283 ; VBITS_GE_1024-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
284 ; VBITS_GE_1024-NEXT: and [[AND:z[0-9]+]].s, [[MASK]].s, #0x1
285 ; VBITS_GE_1024-NEXT: cmpne [[COND:p[0-9]+]].s, [[PG1]]/z, [[AND]].s, #0
286 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].s, [[COND]], [[OP1]].s, [[OP2]].s
287 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
288 ; VBITS_GE_1024: ret
289 %mask = load <32 x i1>, <32 x i1>* %c
290 %op1 = load <32 x i32>, <32 x i32>* %a
291 %op2 = load <32 x i32>, <32 x i32>* %b
292 %sel = select <32 x i1> %mask, <32 x i32> %op1, <32 x i32> %op2
293 store <32 x i32> %sel, <32 x i32>* %a
294 ret void
295 }
297 define void @select_v64i32(<64 x i32>* %a, <64 x i32>* %b, <64 x i1>* %c) #0 {
298 ; CHECK: select_v64i32:
299 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
300 ; CHECK: ptrue [[PG1:p[0-9]+]].s
301 ; VBITS_GE_2048: ld1w { [[MASK:z[0-9]+]].s }, [[PG]]/z, [x9]
302 ; VBITS_GE_2048-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
303 ; VBITS_GE_2048-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
304 ; VBITS_GE_2048-NEXT: and [[AND:z[0-9]+]].s, [[MASK]].s, #0x1
305 ; VBITS_GE_2048-NEXT: cmpne [[COND:p[0-9]+]].s, [[PG1]]/z, [[AND]].s, #0
306 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].s, [[COND]], [[OP1]].s, [[OP2]].s
307 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
308 ; VBITS_GE_2048: ret
309 %mask = load <64 x i1>, <64 x i1>* %c
310 %op1 = load <64 x i32>, <64 x i32>* %a
311 %op2 = load <64 x i32>, <64 x i32>* %b
312 %sel = select <64 x i1> %mask, <64 x i32> %op1, <64 x i32> %op2
313 store <64 x i32> %sel, <64 x i32>* %a
314 ret void
315 }
317 ; Don't use SVE for 64-bit vectors.
318 define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #0 {
319 ; CHECK: select_v1i64:
320 ; CHECK: bif v0.8b, v1.8b, v2.8b
321 ; CHECK: ret
322 %sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2
323 ret <1 x i64> %sel
324 }
326 ; Don't use SVE for 128-bit vectors.
327 define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 {
328 ; CHECK: select_v2i64:
329 ; CHECK: bif v0.16b, v1.16b, v2.16b
330 ; CHECK: ret
331 %sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2
332 ret <2 x i64> %sel
333 }
335 define void @select_v4i64(<4 x i64>* %a, <4 x i64>* %b, <4 x i1>* %c) #0 {
336 ; CHECK: select_v4i64:
337 ; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
338 ; CHECK: ptrue [[PG1:p[0-9]+]].d
339 ; CHECK: ld1d { [[MASK:z[0-9]+]].d }, [[PG]]/z, [x9]
340 ; CHECK-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
341 ; CHECK-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
342 ; CHECK-NEXT: and [[AND:z[0-9]+]].d, [[MASK]].d, #0x1
343 ; CHECK-NEXT: cmpne [[COND:p[0-9]+]].d, [[PG1]]/z, [[AND]].d, #0
344 ; CHECK-NEXT: sel [[RES:z[0-9]+]].d, [[COND]], [[OP1]].d, [[OP2]].d
345 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
346 ; CHECK: ret
347 %mask = load <4 x i1>, <4 x i1>* %c
348 %op1 = load <4 x i64>, <4 x i64>* %a
349 %op2 = load <4 x i64>, <4 x i64>* %b
350 %sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2
351 store <4 x i64> %sel, <4 x i64>* %a
352 ret void
353 }
355 define void @select_v8i64(<8 x i64>* %a, <8 x i64>* %b, <8 x i1>* %c) #0 {
356 ; CHECK: select_v8i64:
357 ; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
358 ; CHECK: ptrue [[PG1:p[0-9]+]].d
359 ; VBITS_GE_512: ld1d { [[MASK:z[0-9]+]].d }, [[PG]]/z, [x9]
360 ; VBITS_GE_512-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
361 ; VBITS_GE_512-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
362 ; VBITS_GE_512-NEXT: and [[AND:z[0-9]+]].d, [[MASK]].d, #0x1
363 ; VBITS_GE_512-NEXT: cmpne [[COND:p[0-9]+]].d, [[PG1]]/z, [[AND]].d, #0
364 ; VBITS_GE_512-NEXT: sel [[RES:z[0-9]+]].d, [[COND]], [[OP1]].d, [[OP2]].d
365 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
366 ; VBITS_GE_512: ret
367 %mask = load <8 x i1>, <8 x i1>* %c
368 %op1 = load <8 x i64>, <8 x i64>* %a
369 %op2 = load <8 x i64>, <8 x i64>* %b
370 %sel = select <8 x i1> %mask, <8 x i64> %op1, <8 x i64> %op2
371 store <8 x i64> %sel, <8 x i64>* %a
372 ret void
373 }
375 define void @select_v16i64(<16 x i64>* %a, <16 x i64>* %b, <16 x i1>* %c) #0 {
376 ; CHECK: select_v16i64:
377 ; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
378 ; CHECK: ptrue [[PG1:p[0-9]+]].d
379 ; VBITS_GE_1024: ld1d { [[MASK:z[0-9]+]].d }, [[PG]]/z, [x9]
380 ; VBITS_GE_1024-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
381 ; VBITS_GE_1024-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
382 ; VBITS_GE_1024-NEXT: and [[AND:z[0-9]+]].d, [[MASK]].d, #0x1
383 ; VBITS_GE_1024-NEXT: cmpne [[COND:p[0-9]+]].d, [[PG1]]/z, [[AND]].d, #0
384 ; VBITS_GE_1024-NEXT: sel [[RES:z[0-9]+]].d, [[COND]], [[OP1]].d, [[OP2]].d
385 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
386 ; VBITS_GE_1024: ret
387 %mask = load <16 x i1>, <16 x i1>* %c
388 %op1 = load <16 x i64>, <16 x i64>* %a
389 %op2 = load <16 x i64>, <16 x i64>* %b
390 %sel = select <16 x i1> %mask, <16 x i64> %op1, <16 x i64> %op2
391 store <16 x i64> %sel, <16 x i64>* %a
392 ret void
393 }
395 define void @select_v32i64(<32 x i64>* %a, <32 x i64>* %b, <32 x i1>* %c) #0 {
396 ; CHECK: select_v32i64:
397 ; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
398 ; CHECK: ptrue [[PG1:p[0-9]+]].d
399 ; VBITS_GE_2048: ld1d { [[MASK:z[0-9]+]].d }, [[PG]]/z, [x9]
400 ; VBITS_GE_2048-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
401 ; VBITS_GE_2048-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
402 ; VBITS_GE_2048-NEXT: and [[AND:z[0-9]+]].d, [[MASK]].d, #0x1
403 ; VBITS_GE_2048-NEXT: cmpne [[COND:p[0-9]+]].d, [[PG1]]/z, [[AND]].d, #0
404 ; VBITS_GE_2048-NEXT: sel [[RES:z[0-9]+]].d, [[COND]], [[OP1]].d, [[OP2]].d
405 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
406 ; VBITS_GE_2048: ret
407 %mask = load <32 x i1>, <32 x i1>* %c
408 %op1 = load <32 x i64>, <32 x i64>* %a
409 %op2 = load <32 x i64>, <32 x i64>* %b
410 %sel = select <32 x i1> %mask, <32 x i64> %op1, <32 x i64> %op2
411 store <32 x i64> %sel, <32 x i64>* %a
412 ret void
413 }
415 attributes #0 = { "target-features"="+sve" }