| blob | 9900e5d54558ba9c6568dc872bb1e8f4ab13688b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
4 ; ANDV
6 define i1 @reduce_and_nxv16i1(<vscale x 16 x i1> %vec) {
7 ; CHECK-LABEL: reduce_and_nxv16i1:
8 ; CHECK: // %bb.0:
9 ; CHECK-NEXT: ptrue p1.b
10 ; CHECK-NEXT: not p0.b, p1/z, p0.b
11 ; CHECK-NEXT: ptest p1, p0.b
12 ; CHECK-NEXT: cset w0, eq
13 ; CHECK-NEXT: ret
14 %res = call i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)
15 ret i1 %res
16 }
18 define i1 @reduce_and_nxv8i1(<vscale x 8 x i1> %vec) {
19 ; CHECK-LABEL: reduce_and_nxv8i1:
20 ; CHECK: // %bb.0:
21 ; CHECK-NEXT: ptrue p1.h
22 ; CHECK-NEXT: not p0.b, p1/z, p0.b
23 ; CHECK-NEXT: ptest p1, p0.b
24 ; CHECK-NEXT: cset w0, eq
25 ; CHECK-NEXT: ret
26 %res = call i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)
27 ret i1 %res
28 }
30 define i1 @reduce_and_nxv4i1(<vscale x 4 x i1> %vec) {
31 ; CHECK-LABEL: reduce_and_nxv4i1:
32 ; CHECK: // %bb.0:
33 ; CHECK-NEXT: ptrue p1.s
34 ; CHECK-NEXT: not p0.b, p1/z, p0.b
35 ; CHECK-NEXT: ptest p1, p0.b
36 ; CHECK-NEXT: cset w0, eq
37 ; CHECK-NEXT: ret
38 %res = call i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)
39 ret i1 %res
40 }
42 define i1 @reduce_and_nxv2i1(<vscale x 2 x i1> %vec) {
43 ; CHECK-LABEL: reduce_and_nxv2i1:
44 ; CHECK: // %bb.0:
45 ; CHECK-NEXT: ptrue p1.d
46 ; CHECK-NEXT: not p0.b, p1/z, p0.b
47 ; CHECK-NEXT: ptest p1, p0.b
48 ; CHECK-NEXT: cset w0, eq
49 ; CHECK-NEXT: ret
50 %res = call i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)
51 ret i1 %res
52 }
54 ; ORV
56 define i1 @reduce_or_nxv16i1(<vscale x 16 x i1> %vec) {
57 ; CHECK-LABEL: reduce_or_nxv16i1:
58 ; CHECK: // %bb.0:
59 ; CHECK-NEXT: ptrue p1.b
60 ; CHECK-NEXT: ptest p1, p0.b
61 ; CHECK-NEXT: cset w0, ne
62 ; CHECK-NEXT: ret
63 %res = call i1 @llvm.vector.reduce.or.i1.nxv16i1(<vscale x 16 x i1> %vec)
64 ret i1 %res
65 }
67 define i1 @reduce_or_nxv8i1(<vscale x 8 x i1> %vec) {
68 ; CHECK-LABEL: reduce_or_nxv8i1:
69 ; CHECK: // %bb.0:
70 ; CHECK-NEXT: ptrue p1.h
71 ; CHECK-NEXT: ptest p1, p0.b
72 ; CHECK-NEXT: cset w0, ne
73 ; CHECK-NEXT: ret
74 %res = call i1 @llvm.vector.reduce.or.i1.nxv8i1(<vscale x 8 x i1> %vec)
75 ret i1 %res
76 }
78 define i1 @reduce_or_nxv4i1(<vscale x 4 x i1> %vec) {
79 ; CHECK-LABEL: reduce_or_nxv4i1:
80 ; CHECK: // %bb.0:
81 ; CHECK-NEXT: ptrue p1.s
82 ; CHECK-NEXT: ptest p1, p0.b
83 ; CHECK-NEXT: cset w0, ne
84 ; CHECK-NEXT: ret
85 %res = call i1 @llvm.vector.reduce.or.i1.nxv4i1(<vscale x 4 x i1> %vec)
86 ret i1 %res
87 }
89 define i1 @reduce_or_nxv2i1(<vscale x 2 x i1> %vec) {
90 ; CHECK-LABEL: reduce_or_nxv2i1:
91 ; CHECK: // %bb.0:
92 ; CHECK-NEXT: ptrue p1.d
93 ; CHECK-NEXT: ptest p1, p0.b
94 ; CHECK-NEXT: cset w0, ne
95 ; CHECK-NEXT: ret
96 %res = call i1 @llvm.vector.reduce.or.i1.nxv2i1(<vscale x 2 x i1> %vec)
97 ret i1 %res
98 }
100 ; XORV
102 define i1 @reduce_xor_nxv16i1(<vscale x 16 x i1> %vec) {
103 ; CHECK-LABEL: reduce_xor_nxv16i1:
104 ; CHECK: // %bb.0:
105 ; CHECK-NEXT: ptrue p1.b
106 ; CHECK-NEXT: cntp x8, p1, p0.b
107 ; CHECK-NEXT: and w0, w8, #0x1
108 ; CHECK-NEXT: ret
109 %res = call i1 @llvm.vector.reduce.xor.i1.nxv16i1(<vscale x 16 x i1> %vec)
110 ret i1 %res
111 }
113 define i1 @reduce_xor_nxv8i1(<vscale x 8 x i1> %vec) {
114 ; CHECK-LABEL: reduce_xor_nxv8i1:
115 ; CHECK: // %bb.0:
116 ; CHECK-NEXT: ptrue p1.h
117 ; CHECK-NEXT: cntp x8, p1, p0.h
118 ; CHECK-NEXT: and w0, w8, #0x1
119 ; CHECK-NEXT: ret
120 %res = call i1 @llvm.vector.reduce.xor.i1.nxv8i1(<vscale x 8 x i1> %vec)
121 ret i1 %res
122 }
124 define i1 @reduce_xor_nxv4i1(<vscale x 4 x i1> %vec) {
125 ; CHECK-LABEL: reduce_xor_nxv4i1:
126 ; CHECK: // %bb.0:
127 ; CHECK-NEXT: ptrue p1.s
128 ; CHECK-NEXT: cntp x8, p1, p0.s
129 ; CHECK-NEXT: and w0, w8, #0x1
130 ; CHECK-NEXT: ret
131 %res = call i1 @llvm.vector.reduce.xor.i1.nxv4i1(<vscale x 4 x i1> %vec)
132 ret i1 %res
133 }
135 define i1 @reduce_xor_nxv2i1(<vscale x 2 x i1> %vec) {
136 ; CHECK-LABEL: reduce_xor_nxv2i1:
137 ; CHECK: // %bb.0:
138 ; CHECK-NEXT: ptrue p1.d
139 ; CHECK-NEXT: cntp x8, p1, p0.d
140 ; CHECK-NEXT: and w0, w8, #0x1
141 ; CHECK-NEXT: ret
142 %res = call i1 @llvm.vector.reduce.xor.i1.nxv2i1(<vscale x 2 x i1> %vec)
143 ret i1 %res
144 }
146 ; SMAXV
148 define i1 @reduce_smax_nxv16i1(<vscale x 16 x i1> %vec) {
149 ; CHECK-LABEL: reduce_smax_nxv16i1:
150 ; CHECK: // %bb.0:
151 ; CHECK-NEXT: ptrue p1.b
152 ; CHECK-NEXT: not p0.b, p1/z, p0.b
153 ; CHECK-NEXT: ptest p1, p0.b
154 ; CHECK-NEXT: cset w0, eq
155 ; CHECK-NEXT: ret
156 %res = call i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)
157 ret i1 %res
158 }
160 define i1 @reduce_smax_nxv8i1(<vscale x 8 x i1> %vec) {
161 ; CHECK-LABEL: reduce_smax_nxv8i1:
162 ; CHECK: // %bb.0:
163 ; CHECK-NEXT: ptrue p1.h
164 ; CHECK-NEXT: not p0.b, p1/z, p0.b
165 ; CHECK-NEXT: ptest p1, p0.b
166 ; CHECK-NEXT: cset w0, eq
167 ; CHECK-NEXT: ret
168 %res = call i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)
169 ret i1 %res
170 }
172 define i1 @reduce_smax_nxv4i1(<vscale x 4 x i1> %vec) {
173 ; CHECK-LABEL: reduce_smax_nxv4i1:
174 ; CHECK: // %bb.0:
175 ; CHECK-NEXT: ptrue p1.s
176 ; CHECK-NEXT: not p0.b, p1/z, p0.b
177 ; CHECK-NEXT: ptest p1, p0.b
178 ; CHECK-NEXT: cset w0, eq
179 ; CHECK-NEXT: ret
180 %res = call i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)
181 ret i1 %res
182 }
184 define i1 @reduce_smax_nxv2i1(<vscale x 2 x i1> %vec) {
185 ; CHECK-LABEL: reduce_smax_nxv2i1:
186 ; CHECK: // %bb.0:
187 ; CHECK-NEXT: ptrue p1.d
188 ; CHECK-NEXT: not p0.b, p1/z, p0.b
189 ; CHECK-NEXT: ptest p1, p0.b
190 ; CHECK-NEXT: cset w0, eq
191 ; CHECK-NEXT: ret
192 %res = call i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)
193 ret i1 %res
194 }
196 ; SMINV
198 define i1 @reduce_smin_nxv16i1(<vscale x 16 x i1> %vec) {
199 ; CHECK-LABEL: reduce_smin_nxv16i1:
200 ; CHECK: // %bb.0:
201 ; CHECK-NEXT: ptrue p1.b
202 ; CHECK-NEXT: ptest p1, p0.b
203 ; CHECK-NEXT: cset w0, ne
204 ; CHECK-NEXT: ret
205 %res = call i1 @llvm.vector.reduce.smin.i1.nxv16i1(<vscale x 16 x i1> %vec)
206 ret i1 %res
207 }
209 define i1 @reduce_smin_nxv8i1(<vscale x 8 x i1> %vec) {
210 ; CHECK-LABEL: reduce_smin_nxv8i1:
211 ; CHECK: // %bb.0:
212 ; CHECK-NEXT: ptrue p1.h
213 ; CHECK-NEXT: ptest p1, p0.b
214 ; CHECK-NEXT: cset w0, ne
215 ; CHECK-NEXT: ret
216 %res = call i1 @llvm.vector.reduce.smin.i1.nxv8i1(<vscale x 8 x i1> %vec)
217 ret i1 %res
218 }
220 define i1 @reduce_smin_nxv4i1(<vscale x 4 x i1> %vec) {
221 ; CHECK-LABEL: reduce_smin_nxv4i1:
222 ; CHECK: // %bb.0:
223 ; CHECK-NEXT: ptrue p1.s
224 ; CHECK-NEXT: ptest p1, p0.b
225 ; CHECK-NEXT: cset w0, ne
226 ; CHECK-NEXT: ret
227 %res = call i1 @llvm.vector.reduce.smin.i1.nxv4i1(<vscale x 4 x i1> %vec)
228 ret i1 %res
229 }
231 define i1 @reduce_smin_nxv2i1(<vscale x 2 x i1> %vec) {
232 ; CHECK-LABEL: reduce_smin_nxv2i1:
233 ; CHECK: // %bb.0:
234 ; CHECK-NEXT: ptrue p1.d
235 ; CHECK-NEXT: ptest p1, p0.b
236 ; CHECK-NEXT: cset w0, ne
237 ; CHECK-NEXT: ret
238 %res = call i1 @llvm.vector.reduce.smin.i1.nxv2i1(<vscale x 2 x i1> %vec)
239 ret i1 %res
240 }
242 ; UMAXV
244 define i1 @reduce_umax_nxv16i1(<vscale x 16 x i1> %vec) {
245 ; CHECK-LABEL: reduce_umax_nxv16i1:
246 ; CHECK: // %bb.0:
247 ; CHECK-NEXT: ptrue p1.b
248 ; CHECK-NEXT: ptest p1, p0.b
249 ; CHECK-NEXT: cset w0, ne
250 ; CHECK-NEXT: ret
251 %res = call i1 @llvm.vector.reduce.umax.i1.nxv16i1(<vscale x 16 x i1> %vec)
252 ret i1 %res
253 }
255 define i1 @reduce_umax_nxv8i1(<vscale x 8 x i1> %vec) {
256 ; CHECK-LABEL: reduce_umax_nxv8i1:
257 ; CHECK: // %bb.0:
258 ; CHECK-NEXT: ptrue p1.h
259 ; CHECK-NEXT: ptest p1, p0.b
260 ; CHECK-NEXT: cset w0, ne
261 ; CHECK-NEXT: ret
262 %res = call i1 @llvm.vector.reduce.umax.i1.nxv8i1(<vscale x 8 x i1> %vec)
263 ret i1 %res
264 }
266 define i1 @reduce_umax_nxv4i1(<vscale x 4 x i1> %vec) {
267 ; CHECK-LABEL: reduce_umax_nxv4i1:
268 ; CHECK: // %bb.0:
269 ; CHECK-NEXT: ptrue p1.s
270 ; CHECK-NEXT: ptest p1, p0.b
271 ; CHECK-NEXT: cset w0, ne
272 ; CHECK-NEXT: ret
273 %res = call i1 @llvm.vector.reduce.umax.i1.nxv4i1(<vscale x 4 x i1> %vec)
274 ret i1 %res
275 }
277 define i1 @reduce_umax_nxv2i1(<vscale x 2 x i1> %vec) {
278 ; CHECK-LABEL: reduce_umax_nxv2i1:
279 ; CHECK: // %bb.0:
280 ; CHECK-NEXT: ptrue p1.d
281 ; CHECK-NEXT: ptest p1, p0.b
282 ; CHECK-NEXT: cset w0, ne
283 ; CHECK-NEXT: ret
284 %res = call i1 @llvm.vector.reduce.umax.i1.nxv2i1(<vscale x 2 x i1> %vec)
285 ret i1 %res
286 }
288 ; UMINV
290 define i1 @reduce_umin_nxv16i1(<vscale x 16 x i1> %vec) {
291 ; CHECK-LABEL: reduce_umin_nxv16i1:
292 ; CHECK: // %bb.0:
293 ; CHECK-NEXT: ptrue p1.b
294 ; CHECK-NEXT: not p0.b, p1/z, p0.b
295 ; CHECK-NEXT: ptest p1, p0.b
296 ; CHECK-NEXT: cset w0, eq
297 ; CHECK-NEXT: ret
298 %res = call i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)
299 ret i1 %res
300 }
302 define i1 @reduce_umin_nxv8i1(<vscale x 8 x i1> %vec) {
303 ; CHECK-LABEL: reduce_umin_nxv8i1:
304 ; CHECK: // %bb.0:
305 ; CHECK-NEXT: ptrue p1.h
306 ; CHECK-NEXT: not p0.b, p1/z, p0.b
307 ; CHECK-NEXT: ptest p1, p0.b
308 ; CHECK-NEXT: cset w0, eq
309 ; CHECK-NEXT: ret
310 %res = call i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)
311 ret i1 %res
312 }
314 define i1 @reduce_umin_nxv4i1(<vscale x 4 x i1> %vec) {
315 ; CHECK-LABEL: reduce_umin_nxv4i1:
316 ; CHECK: // %bb.0:
317 ; CHECK-NEXT: ptrue p1.s
318 ; CHECK-NEXT: not p0.b, p1/z, p0.b
319 ; CHECK-NEXT: ptest p1, p0.b
320 ; CHECK-NEXT: cset w0, eq
321 ; CHECK-NEXT: ret
322 %res = call i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)
323 ret i1 %res
324 }
326 define i1 @reduce_umin_nxv2i1(<vscale x 2 x i1> %vec) {
327 ; CHECK-LABEL: reduce_umin_nxv2i1:
328 ; CHECK: // %bb.0:
329 ; CHECK-NEXT: ptrue p1.d
330 ; CHECK-NEXT: not p0.b, p1/z, p0.b
331 ; CHECK-NEXT: ptest p1, p0.b
332 ; CHECK-NEXT: cset w0, eq
333 ; CHECK-NEXT: ret
334 %res = call i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)
335 ret i1 %res
336 }
338 declare i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)
339 declare i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)
340 declare i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)
341 declare i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)
343 declare i1 @llvm.vector.reduce.or.i1.nxv16i1(<vscale x 16 x i1> %vec)
344 declare i1 @llvm.vector.reduce.or.i1.nxv8i1(<vscale x 8 x i1> %vec)
345 declare i1 @llvm.vector.reduce.or.i1.nxv4i1(<vscale x 4 x i1> %vec)
346 declare i1 @llvm.vector.reduce.or.i1.nxv2i1(<vscale x 2 x i1> %vec)
348 declare i1 @llvm.vector.reduce.xor.i1.nxv16i1(<vscale x 16 x i1> %vec)
349 declare i1 @llvm.vector.reduce.xor.i1.nxv8i1(<vscale x 8 x i1> %vec)
350 declare i1 @llvm.vector.reduce.xor.i1.nxv4i1(<vscale x 4 x i1> %vec)
351 declare i1 @llvm.vector.reduce.xor.i1.nxv2i1(<vscale x 2 x i1> %vec)
353 declare i1 @llvm.vector.reduce.smin.i1.nxv16i1(<vscale x 16 x i1> %vec)
354 declare i1 @llvm.vector.reduce.smin.i1.nxv8i1(<vscale x 8 x i1> %vec)
355 declare i1 @llvm.vector.reduce.smin.i1.nxv4i1(<vscale x 4 x i1> %vec)
356 declare i1 @llvm.vector.reduce.smin.i1.nxv2i1(<vscale x 2 x i1> %vec)
358 declare i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)
359 declare i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)
360 declare i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)
361 declare i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)
363 declare i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)
364 declare i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)
365 declare i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)
366 declare i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)
368 declare i1 @llvm.vector.reduce.umax.i1.nxv16i1(<vscale x 16 x i1> %vec)
369 declare i1 @llvm.vector.reduce.umax.i1.nxv8i1(<vscale x 8 x i1> %vec)
370 declare i1 @llvm.vector.reduce.umax.i1.nxv4i1(<vscale x 4 x i1> %vec)
371 declare i1 @llvm.vector.reduce.umax.i1.nxv2i1(<vscale x 2 x i1> %vec)