| blob | 9afdb48c053e9dcb4335552f298f312644cfeaa6 |
1 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 < %s | FileCheck %s
3 ;
4 ; SABA
5 ;
7 define <vscale x 16 x i8> @saba_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
8 ; CHECK-LABEL: saba_i8:
9 ; CHECK: saba z0.b, z1.b, z2.b
10 ; CHECK-NEXT: ret
11 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.saba.nxv16i8(<vscale x 16 x i8> %a,
12 <vscale x 16 x i8> %b,
13 <vscale x 16 x i8> %c)
14 ret <vscale x 16 x i8> %out
15 }
17 define <vscale x 8 x i16> @saba_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
18 ; CHECK-LABEL: saba_i16:
19 ; CHECK: saba z0.h, z1.h, z2.h
20 ; CHECK-NEXT: ret
21 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.saba.nxv8i16(<vscale x 8 x i16> %a,
22 <vscale x 8 x i16> %b,
23 <vscale x 8 x i16> %c)
24 ret <vscale x 8 x i16> %out
25 }
27 define <vscale x 4 x i32> @saba_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
28 ; CHECK-LABEL: saba_i32:
29 ; CHECK: saba z0.s, z1.s, z2.s
30 ; CHECK-NEXT: ret
31 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.saba.nxv4i32(<vscale x 4 x i32> %a,
32 <vscale x 4 x i32> %b,
33 <vscale x 4 x i32> %c)
34 ret <vscale x 4 x i32> %out
35 }
37 define <vscale x 2 x i64> @saba_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
38 ; CHECK-LABEL: saba_i64:
39 ; CHECK: saba z0.d, z1.d, z2.d
40 ; CHECK-NEXT: ret
41 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.saba.nxv2i64(<vscale x 2 x i64> %a,
42 <vscale x 2 x i64> %b,
43 <vscale x 2 x i64> %c)
44 ret <vscale x 2 x i64> %out
45 }
47 ;
48 ; SHADD
49 ;
51 define <vscale x 16 x i8> @shadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
52 ; CHECK-LABEL: shadd_i8:
53 ; CHECK: shadd z0.b, p0/m, z0.b, z1.b
54 ; CHECK-NEXT: ret
55 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1> %pg,
56 <vscale x 16 x i8> %a,
57 <vscale x 16 x i8> %b)
58 ret <vscale x 16 x i8> %out
59 }
61 define <vscale x 8 x i16> @shadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
62 ; CHECK-LABEL: shadd_i16:
63 ; CHECK: shadd z0.h, p0/m, z0.h, z1.h
64 ; CHECK-NEXT: ret
65 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1> %pg,
66 <vscale x 8 x i16> %a,
67 <vscale x 8 x i16> %b)
68 ret <vscale x 8 x i16> %out
69 }
71 define <vscale x 4 x i32> @shadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
72 ; CHECK-LABEL: shadd_i32:
73 ; CHECK: shadd z0.s, p0/m, z0.s, z1.s
74 ; CHECK-NEXT: ret
75 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> %pg,
76 <vscale x 4 x i32> %a,
77 <vscale x 4 x i32> %b)
78 ret <vscale x 4 x i32> %out
79 }
81 define <vscale x 2 x i64> @shadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
82 ; CHECK-LABEL: shadd_i64:
83 ; CHECK: shadd z0.d, p0/m, z0.d, z1.d
84 ; CHECK-NEXT: ret
85 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1> %pg,
86 <vscale x 2 x i64> %a,
87 <vscale x 2 x i64> %b)
88 ret <vscale x 2 x i64> %out
89 }
91 ;
92 ; SHSUB
93 ;
95 define <vscale x 16 x i8> @shsub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
96 ; CHECK-LABEL: shsub_i8:
97 ; CHECK: shsub z0.b, p0/m, z0.b, z1.b
98 ; CHECK-NEXT: ret
99 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1> %pg,
100 <vscale x 16 x i8> %a,
101 <vscale x 16 x i8> %b)
102 ret <vscale x 16 x i8> %out
103 }
105 define <vscale x 8 x i16> @shsub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
106 ; CHECK-LABEL: shsub_i16:
107 ; CHECK: shsub z0.h, p0/m, z0.h, z1.h
108 ; CHECK-NEXT: ret
109 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1> %pg,
110 <vscale x 8 x i16> %a,
111 <vscale x 8 x i16> %b)
112 ret <vscale x 8 x i16> %out
113 }
115 define <vscale x 4 x i32> @shsub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
116 ; CHECK-LABEL: shsub_i32:
117 ; CHECK: shsub z0.s, p0/m, z0.s, z1.s
118 ; CHECK-NEXT: ret
119 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> %pg,
120 <vscale x 4 x i32> %a,
121 <vscale x 4 x i32> %b)
122 ret <vscale x 4 x i32> %out
123 }
125 define <vscale x 2 x i64> @shsub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
126 ; CHECK-LABEL: shsub_i64:
127 ; CHECK: shsub z0.d, p0/m, z0.d, z1.d
128 ; CHECK-NEXT: ret
129 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1> %pg,
130 <vscale x 2 x i64> %a,
131 <vscale x 2 x i64> %b)
132 ret <vscale x 2 x i64> %out
133 }
135 ;
136 ; SHSUBR
137 ;
139 define <vscale x 16 x i8> @shsubr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
140 ; CHECK-LABEL: shsubr_i8:
141 ; CHECK: shsubr z0.b, p0/m, z0.b, z1.b
142 ; CHECK-NEXT: ret
143 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1> %pg,
144 <vscale x 16 x i8> %a,
145 <vscale x 16 x i8> %b)
146 ret <vscale x 16 x i8> %out
147 }
149 define <vscale x 8 x i16> @shsubr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
150 ; CHECK-LABEL: shsubr_i16:
151 ; CHECK: shsubr z0.h, p0/m, z0.h, z1.h
152 ; CHECK-NEXT: ret
153 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1> %pg,
154 <vscale x 8 x i16> %a,
155 <vscale x 8 x i16> %b)
156 ret <vscale x 8 x i16> %out
157 }
159 define <vscale x 4 x i32> @shsubr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
160 ; CHECK-LABEL: shsubr_i32:
161 ; CHECK: shsubr z0.s, p0/m, z0.s, z1.s
162 ; CHECK-NEXT: ret
163 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> %pg,
164 <vscale x 4 x i32> %a,
165 <vscale x 4 x i32> %b)
166 ret <vscale x 4 x i32> %out
167 }
169 define <vscale x 2 x i64> @shsubr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
170 ; CHECK-LABEL: shsubr_i64:
171 ; CHECK: shsubr z0.d, p0/m, z0.d, z1.d
172 ; CHECK-NEXT: ret
173 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1> %pg,
174 <vscale x 2 x i64> %a,
175 <vscale x 2 x i64> %b)
176 ret <vscale x 2 x i64> %out
177 }
179 ;
180 ; SLI
181 ;
183 define <vscale x 16 x i8> @sli_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
184 ; CHECK-LABEL: sli_i8:
185 ; CHECK: sli z0.b, z1.b, #0
186 ; CHECK-NEXT: ret
187 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sli.nxv16i8(<vscale x 16 x i8> %a,
188 <vscale x 16 x i8> %b,
189 i32 0)
190 ret <vscale x 16 x i8> %out
191 }
193 define <vscale x 8 x i16> @sli_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
194 ; CHECK-LABEL: sli_i16:
195 ; CHECK: sli z0.h, z1.h, #1
196 ; CHECK-NEXT: ret
197 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sli.nxv8i16(<vscale x 8 x i16> %a,
198 <vscale x 8 x i16> %b,
199 i32 1)
200 ret <vscale x 8 x i16> %out
201 }
203 define <vscale x 4 x i32> @sli_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
204 ; CHECK-LABEL: sli_i32:
205 ; CHECK: sli z0.s, z1.s, #30
206 ; CHECK-NEXT: ret
207 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sli.nxv4i32(<vscale x 4 x i32> %a,
208 <vscale x 4 x i32> %b,
209 i32 30);
210 ret <vscale x 4 x i32> %out
211 }
213 define <vscale x 2 x i64> @sli_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
214 ; CHECK-LABEL: sli_i64:
215 ; CHECK: sli z0.d, z1.d, #63
216 ; CHECK-NEXT: ret
217 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sli.nxv2i64(<vscale x 2 x i64> %a,
218 <vscale x 2 x i64> %b,
219 i32 63)
220 ret <vscale x 2 x i64> %out
221 }
223 ;
224 ; SQABS
225 ;
227 define <vscale x 16 x i8> @sqabs_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
228 ; CHECK-LABEL: sqabs_i8:
229 ; CHECK: sqabs z0.b, p0/m, z1.b
230 ; CHECK-NEXT: ret
231 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqabs.nxv16i8(<vscale x 16 x i8> %a,
232 <vscale x 16 x i1> %pg,
233 <vscale x 16 x i8> %b)
234 ret <vscale x 16 x i8> %out
235 }
237 define <vscale x 8 x i16> @sqabs_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
238 ; CHECK-LABEL: sqabs_i16:
239 ; CHECK: sqabs z0.h, p0/m, z1.h
240 ; CHECK-NEXT: ret
241 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqabs.nxv8i16(<vscale x 8 x i16> %a,
242 <vscale x 8 x i1> %pg,
243 <vscale x 8 x i16> %b)
244 ret <vscale x 8 x i16> %out
245 }
247 define <vscale x 4 x i32> @sqabs_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
248 ; CHECK-LABEL: sqabs_i32:
249 ; CHECK: sqabs z0.s, p0/m, z1.s
250 ; CHECK-NEXT: ret
251 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32> %a,
252 <vscale x 4 x i1> %pg,
253 <vscale x 4 x i32> %b)
254 ret <vscale x 4 x i32> %out
255 }
257 define <vscale x 2 x i64> @sqabs_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
258 ; CHECK-LABEL: sqabs_i64:
259 ; CHECK: sqabs z0.d, p0/m, z1.d
260 ; CHECK-NEXT: ret
261 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqabs.nxv2i64(<vscale x 2 x i64> %a,
262 <vscale x 2 x i1> %pg,
263 <vscale x 2 x i64> %b)
264 ret <vscale x 2 x i64> %out
265 }
267 ;
268 ; SQADD
269 ;
271 define <vscale x 16 x i8> @sqadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
272 ; CHECK-LABEL: sqadd_i8:
273 ; CHECK: sqadd z0.b, p0/m, z0.b, z1.b
274 ; CHECK-NEXT: ret
275 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1> %pg,
276 <vscale x 16 x i8> %a,
277 <vscale x 16 x i8> %b)
278 ret <vscale x 16 x i8> %out
279 }
281 define <vscale x 8 x i16> @sqadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
282 ; CHECK-LABEL: sqadd_i16:
283 ; CHECK: sqadd z0.h, p0/m, z0.h, z1.h
284 ; CHECK-NEXT: ret
285 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1> %pg,
286 <vscale x 8 x i16> %a,
287 <vscale x 8 x i16> %b)
288 ret <vscale x 8 x i16> %out
289 }
291 define <vscale x 4 x i32> @sqadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
292 ; CHECK-LABEL: sqadd_i32:
293 ; CHECK: sqadd z0.s, p0/m, z0.s, z1.s
294 ; CHECK-NEXT: ret
295 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> %pg,
296 <vscale x 4 x i32> %a,
297 <vscale x 4 x i32> %b)
298 ret <vscale x 4 x i32> %out
299 }
301 define <vscale x 2 x i64> @sqadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
302 ; CHECK-LABEL: sqadd_i64:
303 ; CHECK: sqadd z0.d, p0/m, z0.d, z1.d
304 ; CHECK-NEXT: ret
305 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1> %pg,
306 <vscale x 2 x i64> %a,
307 <vscale x 2 x i64> %b)
308 ret <vscale x 2 x i64> %out
309 }
311 ;
312 ; SQDMULH (Vector)
313 ;
315 define <vscale x 16 x i8> @sqdmulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
316 ; CHECK-LABEL: sqdmulh_i8:
317 ; CHECK: sqdmulh z0.b, z0.b, z1.b
318 ; CHECK-NEXT: ret
319 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqdmulh.nxv16i8(<vscale x 16 x i8> %a,
320 <vscale x 16 x i8> %b)
321 ret <vscale x 16 x i8> %out
322 }
324 define <vscale x 8 x i16> @sqdmulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
325 ; CHECK-LABEL: sqdmulh_i16:
326 ; CHECK: sqdmulh z0.h, z0.h, z1.h
327 ; CHECK-NEXT: ret
328 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmulh.nxv8i16(<vscale x 8 x i16> %a,
329 <vscale x 8 x i16> %b)
330 ret <vscale x 8 x i16> %out
331 }
333 define <vscale x 4 x i32> @sqdmulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
334 ; CHECK-LABEL: sqdmulh_i32:
335 ; CHECK: sqdmulh z0.s, z0.s, z1.s
336 ; CHECK-NEXT: ret
337 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmulh.nxv4i32(<vscale x 4 x i32> %a,
338 <vscale x 4 x i32> %b)
339 ret <vscale x 4 x i32> %out
340 }
342 define <vscale x 2 x i64> @sqdmulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
343 ; CHECK-LABEL: sqdmulh_i64:
344 ; CHECK: sqdmulh z0.d, z0.d, z1.d
345 ; CHECK-NEXT: ret
346 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmulh.nxv2i64(<vscale x 2 x i64> %a,
347 <vscale x 2 x i64> %b)
348 ret <vscale x 2 x i64> %out
349 }
351 ;
352 ; SQDMULH (Indexed)
353 ;
355 define <vscale x 8 x i16> @sqdmulh_lane_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
356 ; CHECK-LABEL: sqdmulh_lane_i16:
357 ; CHECK: sqdmulh z0.h, z0.h, z1.h[7]
358 ; CHECK-NEXT: ret
359 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmulh.lane.nxv8i16(<vscale x 8 x i16> %a,
360 <vscale x 8 x i16> %b,
361 i32 7)
362 ret <vscale x 8 x i16> %out
363 }
365 define <vscale x 4 x i32> @sqdmulh_lane_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
366 ; CHECK-LABEL: sqdmulh_lane_i32:
367 ; CHECK: sqdmulh z0.s, z0.s, z1.s[3]
368 ; CHECK-NEXT: ret
369 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmulh.lane.nxv4i32(<vscale x 4 x i32> %a,
370 <vscale x 4 x i32> %b,
371 i32 3);
372 ret <vscale x 4 x i32> %out
373 }
375 define <vscale x 2 x i64> @sqdmulh_lane_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
376 ; CHECK-LABEL: sqdmulh_lane_i64:
377 ; CHECK: sqdmulh z0.d, z0.d, z1.d[1]
378 ; CHECK-NEXT: ret
379 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmulh.lane.nxv2i64(<vscale x 2 x i64> %a,
380 <vscale x 2 x i64> %b,
381 i32 1)
382 ret <vscale x 2 x i64> %out
383 }
385 ;
386 ; SQNEG
387 ;
389 define <vscale x 16 x i8> @sqneg_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
390 ; CHECK-LABEL: sqneg_i8:
391 ; CHECK: sqneg z0.b, p0/m, z1.b
392 ; CHECK-NEXT: ret
393 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqneg.nxv16i8(<vscale x 16 x i8> %a,
394 <vscale x 16 x i1> %pg,
395 <vscale x 16 x i8> %b)
396 ret <vscale x 16 x i8> %out
397 }
399 define <vscale x 8 x i16> @sqneg_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
400 ; CHECK-LABEL: sqneg_i16:
401 ; CHECK: sqneg z0.h, p0/m, z1.h
402 ; CHECK-NEXT: ret
403 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqneg.nxv8i16(<vscale x 8 x i16> %a,
404 <vscale x 8 x i1> %pg,
405 <vscale x 8 x i16> %b)
406 ret <vscale x 8 x i16> %out
407 }
409 define <vscale x 4 x i32> @sqneg_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
410 ; CHECK-LABEL: sqneg_i32:
411 ; CHECK: sqneg z0.s, p0/m, z1.s
412 ; CHECK-NEXT: ret
413 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32> %a,
414 <vscale x 4 x i1> %pg,
415 <vscale x 4 x i32> %b)
416 ret <vscale x 4 x i32> %out
417 }
419 define <vscale x 2 x i64> @sqneg_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
420 ; CHECK-LABEL: sqneg_i64:
421 ; CHECK: sqneg z0.d, p0/m, z1.d
422 ; CHECK-NEXT: ret
423 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqneg.nxv2i64(<vscale x 2 x i64> %a,
424 <vscale x 2 x i1> %pg,
425 <vscale x 2 x i64> %b)
426 ret <vscale x 2 x i64> %out
427 }
429 ;
430 ; SQRDMALH (Vectors)
431 ;
433 define <vscale x 16 x i8> @sqrdmlah_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
434 ; CHECK-LABEL: sqrdmlah_i8:
435 ; CHECK: sqrdmlah z0.b, z1.b, z2.b
436 ; CHECK-NEXT: ret
437 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlah.nxv16i8(<vscale x 16 x i8> %a,
438 <vscale x 16 x i8> %b,
439 <vscale x 16 x i8> %c)
440 ret <vscale x 16 x i8> %out
441 }
443 define <vscale x 8 x i16> @sqrdmlah_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
444 ; CHECK-LABEL: sqrdmlah_i16:
445 ; CHECK: sqrdmlah z0.h, z1.h, z2.h
446 ; CHECK-NEXT: ret
447 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.nxv8i16(<vscale x 8 x i16> %a,
448 <vscale x 8 x i16> %b,
449 <vscale x 8 x i16> %c)
450 ret <vscale x 8 x i16> %out
451 }
453 define <vscale x 4 x i32> @sqrdmlah_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
454 ; CHECK-LABEL: sqrdmlah_i32:
455 ; CHECK: sqrdmlah z0.s, z1.s, z2.s
456 ; CHECK-NEXT: ret
457 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.nxv4i32(<vscale x 4 x i32> %a,
458 <vscale x 4 x i32> %b,
459 <vscale x 4 x i32> %c)
460 ret <vscale x 4 x i32> %out
461 }
463 define <vscale x 2 x i64> @sqrdmlah_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
464 ; CHECK-LABEL: sqrdmlah_i64:
465 ; CHECK: sqrdmlah z0.d, z1.d, z2.d
466 ; CHECK-NEXT: ret
467 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.nxv2i64(<vscale x 2 x i64> %a,
468 <vscale x 2 x i64> %b,
469 <vscale x 2 x i64> %c)
470 ret <vscale x 2 x i64> %out
471 }
473 ;
474 ; SQRDMALH (Indexed)
475 ;
477 define <vscale x 8 x i16> @sqrdmlah_lane_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
478 ; CHECK-LABEL: sqrdmlah_lane_i16:
479 ; CHECK: sqrdmlah z0.h, z1.h, z2.h[5]
480 ; CHECK-NEXT: ret
481 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16(<vscale x 8 x i16> %a,
482 <vscale x 8 x i16> %b,
483 <vscale x 8 x i16> %c,
484 i32 5)
485 ret <vscale x 8 x i16> %out
486 }
488 define <vscale x 4 x i32> @sqrdmlah_lane_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
489 ; CHECK-LABEL: sqrdmlah_lane_i32:
490 ; CHECK: sqrdmlah z0.s, z1.s, z2.s[1]
491 ; CHECK-NEXT: ret
492 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32(<vscale x 4 x i32> %a,
493 <vscale x 4 x i32> %b,
494 <vscale x 4 x i32> %c,
495 i32 1);
496 ret <vscale x 4 x i32> %out
497 }
499 define <vscale x 2 x i64> @sqrdmlah_lane_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
500 ; CHECK-LABEL: sqrdmlah_lane_i64:
501 ; CHECK: sqrdmlah z0.d, z1.d, z2.d[1]
502 ; CHECK-NEXT: ret
503 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64(<vscale x 2 x i64> %a,
504 <vscale x 2 x i64> %b,
505 <vscale x 2 x i64> %c,
506 i32 1)
507 ret <vscale x 2 x i64> %out
508 }
510 ;
511 ; SQRDMSLH (Vectors)
512 ;
514 define <vscale x 16 x i8> @sqrdmlsh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
515 ; CHECK-LABEL: sqrdmlsh_i8:
516 ; CHECK: sqrdmlsh z0.b, z1.b, z2.b
517 ; CHECK-NEXT: ret
518 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlsh.nxv16i8(<vscale x 16 x i8> %a,
519 <vscale x 16 x i8> %b,
520 <vscale x 16 x i8> %c)
521 ret <vscale x 16 x i8> %out
522 }
524 define <vscale x 8 x i16> @sqrdmlsh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
525 ; CHECK-LABEL: sqrdmlsh_i16:
526 ; CHECK: sqrdmlsh z0.h, z1.h, z2.h
527 ; CHECK-NEXT: ret
528 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlsh.nxv8i16(<vscale x 8 x i16> %a,
529 <vscale x 8 x i16> %b,
530 <vscale x 8 x i16> %c)
531 ret <vscale x 8 x i16> %out
532 }
534 define <vscale x 4 x i32> @sqrdmlsh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
535 ; CHECK-LABEL: sqrdmlsh_i32:
536 ; CHECK: sqrdmlsh z0.s, z1.s, z2.s
537 ; CHECK-NEXT: ret
538 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlsh.nxv4i32(<vscale x 4 x i32> %a,
539 <vscale x 4 x i32> %b,
540 <vscale x 4 x i32> %c)
541 ret <vscale x 4 x i32> %out
542 }
544 define <vscale x 2 x i64> @sqrdmlsh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
545 ; CHECK-LABEL: sqrdmlsh_i64:
546 ; CHECK: sqrdmlsh z0.d, z1.d, z2.d
547 ; CHECK-NEXT: ret
548 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlsh.nxv2i64(<vscale x 2 x i64> %a,
549 <vscale x 2 x i64> %b,
550 <vscale x 2 x i64> %c)
551 ret <vscale x 2 x i64> %out
552 }
554 ;
555 ; SQRDMSLH (Indexed)
556 ;
558 define <vscale x 8 x i16> @sqrdmlsh_lane_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
559 ; CHECK-LABEL: sqrdmlsh_lane_i16:
560 ; CHECK: sqrdmlsh z0.h, z1.h, z2.h[4]
561 ; CHECK-NEXT: ret
562 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16(<vscale x 8 x i16> %a,
563 <vscale x 8 x i16> %b,
564 <vscale x 8 x i16> %c,
565 i32 4)
566 ret <vscale x 8 x i16> %out
567 }
569 define <vscale x 4 x i32> @sqrdmlsh_lane_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
570 ; CHECK-LABEL: sqrdmlsh_lane_i32:
571 ; CHECK: sqrdmlsh z0.s, z1.s, z2.s[0]
572 ; CHECK-NEXT: ret
573 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32(<vscale x 4 x i32> %a,
574 <vscale x 4 x i32> %b,
575 <vscale x 4 x i32> %c,
576 i32 0);
577 ret <vscale x 4 x i32> %out
578 }
580 define <vscale x 2 x i64> @sqrdmlsh_lane_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
581 ; CHECK-LABEL: sqrdmlsh_lane_i64:
582 ; CHECK: sqrdmlsh z0.d, z1.d, z2.d[1]
583 ; CHECK-NEXT: ret
584 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64(<vscale x 2 x i64> %a,
585 <vscale x 2 x i64> %b,
586 <vscale x 2 x i64> %c,
587 i32 1)
588 ret <vscale x 2 x i64> %out
589 }
591 ;
592 ; SQRDMULH (Vectors)
593 ;
595 define <vscale x 16 x i8> @sqrdmulh_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
596 ; CHECK-LABEL: sqrdmulh_i8:
597 ; CHECK: sqrdmulh z0.b, z0.b, z1.b
598 ; CHECK-NEXT: ret
599 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmulh.nxv16i8(<vscale x 16 x i8> %a,
600 <vscale x 16 x i8> %b)
601 ret <vscale x 16 x i8> %out
602 }
604 define <vscale x 8 x i16> @sqrdmulh_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
605 ; CHECK-LABEL: sqrdmulh_i16:
606 ; CHECK: sqrdmulh z0.h, z0.h, z1.h
607 ; CHECK-NEXT: ret
608 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmulh.nxv8i16(<vscale x 8 x i16> %a,
609 <vscale x 8 x i16> %b)
610 ret <vscale x 8 x i16> %out
611 }
613 define <vscale x 4 x i32> @sqrdmulh_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
614 ; CHECK-LABEL: sqrdmulh_i32:
615 ; CHECK: sqrdmulh z0.s, z0.s, z1.s
616 ; CHECK-NEXT: ret
617 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmulh.nxv4i32(<vscale x 4 x i32> %a,
618 <vscale x 4 x i32> %b)
619 ret <vscale x 4 x i32> %out
620 }
622 define <vscale x 2 x i64> @sqrdmulh_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
623 ; CHECK-LABEL: sqrdmulh_i64:
624 ; CHECK: sqrdmulh z0.d, z0.d, z1.d
625 ; CHECK-NEXT: ret
626 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmulh.nxv2i64(<vscale x 2 x i64> %a,
627 <vscale x 2 x i64> %b)
628 ret <vscale x 2 x i64> %out
629 }
631 ;
632 ; SQRDMULH (Indexed)
633 ;
635 define <vscale x 8 x i16> @sqrdmulh_lane_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
636 ; CHECK-LABEL: sqrdmulh_lane_i16:
637 ; CHECK: sqrdmulh z0.h, z0.h, z1.h[6]
638 ; CHECK-NEXT: ret
639 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmulh.lane.nxv8i16(<vscale x 8 x i16> %a,
640 <vscale x 8 x i16> %b,
641 i32 6)
642 ret <vscale x 8 x i16> %out
643 }
645 define <vscale x 4 x i32> @sqrdmulh_lane_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
646 ; CHECK-LABEL: sqrdmulh_lane_i32:
647 ; CHECK: sqrdmulh z0.s, z0.s, z1.s[2]
648 ; CHECK-NEXT: ret
649 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmulh.lane.nxv4i32(<vscale x 4 x i32> %a,
650 <vscale x 4 x i32> %b,
651 i32 2);
652 ret <vscale x 4 x i32> %out
653 }
655 define <vscale x 2 x i64> @sqrdmulh_lane_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
656 ; CHECK-LABEL: sqrdmulh_lane_i64:
657 ; CHECK: sqrdmulh z0.d, z0.d, z1.d[1]
658 ; CHECK-NEXT: ret
659 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmulh.lane.nxv2i64(<vscale x 2 x i64> %a,
660 <vscale x 2 x i64> %b,
661 i32 1)
662 ret <vscale x 2 x i64> %out
663 }
665 ;
666 ; SQRSHL
667 ;
669 define <vscale x 16 x i8> @sqrshl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
670 ; CHECK-LABEL: sqrshl_i8:
671 ; CHECK: sqrshl z0.b, p0/m, z0.b, z1.b
672 ; CHECK-NEXT: ret
673 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshl.nxv16i8(<vscale x 16 x i1> %pg,
674 <vscale x 16 x i8> %a,
675 <vscale x 16 x i8> %b)
676 ret <vscale x 16 x i8> %out
677 }
679 define <vscale x 8 x i16> @sqrshl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
680 ; CHECK-LABEL: sqrshl_i16:
681 ; CHECK: sqrshl z0.h, p0/m, z0.h, z1.h
682 ; CHECK-NEXT: ret
683 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshl.nxv8i16(<vscale x 8 x i1> %pg,
684 <vscale x 8 x i16> %a,
685 <vscale x 8 x i16> %b)
686 ret <vscale x 8 x i16> %out
687 }
689 define <vscale x 4 x i32> @sqrshl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
690 ; CHECK-LABEL: sqrshl_i32:
691 ; CHECK: sqrshl z0.s, p0/m, z0.s, z1.s
692 ; CHECK-NEXT: ret
693 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshl.nxv4i32(<vscale x 4 x i1> %pg,
694 <vscale x 4 x i32> %a,
695 <vscale x 4 x i32> %b)
696 ret <vscale x 4 x i32> %out
697 }
699 define <vscale x 2 x i64> @sqrshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
700 ; CHECK-LABEL: sqrshl_i64:
701 ; CHECK: sqrshl z0.d, p0/m, z0.d, z1.d
702 ; CHECK-NEXT: ret
703 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrshl.nxv2i64(<vscale x 2 x i1> %pg,
704 <vscale x 2 x i64> %a,
705 <vscale x 2 x i64> %b)
706 ret <vscale x 2 x i64> %out
707 }
709 ;
710 ; SQRSHLR
711 ;
713 define <vscale x 16 x i8> @sqrshlr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
714 ; CHECK-LABEL: sqrshlr_i8:
715 ; CHECK: ptrue p0.b
716 ; CHECK-NEXT: sqrshlr z0.b, p0/m, z0.b, z1.b
717 ; CHECK-NEXT: ret
718 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
719 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshl.nxv16i8(<vscale x 16 x i1> %pg,
720 <vscale x 16 x i8> %b,
721 <vscale x 16 x i8> %a)
722 ret <vscale x 16 x i8> %out
723 }
725 define <vscale x 8 x i16> @sqrshlr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
726 ; CHECK-LABEL: sqrshlr_i16:
727 ; CHECK: ptrue p0.h
728 ; CHECK-NEXT: sqrshlr z0.h, p0/m, z0.h, z1.h
729 ; CHECK-NEXT: ret
730 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
731 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshl.nxv8i16(<vscale x 8 x i1> %pg,
732 <vscale x 8 x i16> %b,
733 <vscale x 8 x i16> %a)
734 ret <vscale x 8 x i16> %out
735 }
737 define <vscale x 4 x i32> @sqrshlr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
738 ; CHECK-LABEL: sqrshlr_i32:
739 ; CHECK: ptrue p0.s
740 ; CHECK-NEXT: sqrshlr z0.s, p0/m, z0.s, z1.s
741 ; CHECK-NEXT: ret
742 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
743 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshl.nxv4i32(<vscale x 4 x i1> %pg,
744 <vscale x 4 x i32> %b,
745 <vscale x 4 x i32> %a)
746 ret <vscale x 4 x i32> %out
747 }
749 define <vscale x 2 x i64> @sqrshlr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
750 ; CHECK-LABEL: sqrshlr_i64:
751 ; CHECK: ptrue p0.d
752 ; CHECK-NEXT: sqrshlr z0.d, p0/m, z0.d, z1.d
753 ; CHECK-NEXT: ret
754 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
755 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrshl.nxv2i64(<vscale x 2 x i1> %pg,
756 <vscale x 2 x i64> %b,
757 <vscale x 2 x i64> %a)
758 ret <vscale x 2 x i64> %out
759 }
761 define <vscale x 2 x i64> @sqrshlr_i64_noptrue(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
762 ; CHECK-LABEL: sqrshlr_i64_noptrue:
763 ; CHECK: sqrshl z1.d, p0/m, z1.d, z0.d
764 ; CHECK-NEXT: mov z0.d, z1.d
765 ; CHECK-NEXT: ret
766 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqrshl.nxv2i64(<vscale x 2 x i1> %pg,
767 <vscale x 2 x i64> %b,
768 <vscale x 2 x i64> %a)
769 ret <vscale x 2 x i64> %out
770 }
772 ;
773 ; SQSHL (Vectors)
774 ;
776 define <vscale x 16 x i8> @sqshl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
777 ; CHECK-LABEL: sqshl_i8:
778 ; CHECK: sqshl z0.b, p0/m, z0.b, z1.b
779 ; CHECK-NEXT: ret
780 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshl.nxv16i8(<vscale x 16 x i1> %pg,
781 <vscale x 16 x i8> %a,
782 <vscale x 16 x i8> %b)
783 ret <vscale x 16 x i8> %out
784 }
786 define <vscale x 8 x i16> @sqshl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
787 ; CHECK-LABEL: sqshl_i16:
788 ; CHECK: sqshl z0.h, p0/m, z0.h, z1.h
789 ; CHECK-NEXT: ret
790 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshl.nxv8i16(<vscale x 8 x i1> %pg,
791 <vscale x 8 x i16> %a,
792 <vscale x 8 x i16> %b)
793 ret <vscale x 8 x i16> %out
794 }
796 define <vscale x 4 x i32> @sqshl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
797 ; CHECK-LABEL: sqshl_i32:
798 ; CHECK: sqshl z0.s, p0/m, z0.s, z1.s
799 ; CHECK-NEXT: ret
800 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1> %pg,
801 <vscale x 4 x i32> %a,
802 <vscale x 4 x i32> %b)
803 ret <vscale x 4 x i32> %out
804 }
806 define <vscale x 2 x i64> @sqshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
807 ; CHECK-LABEL: sqshl_i64:
808 ; CHECK: sqshl z0.d, p0/m, z0.d, z1.d
809 ; CHECK-NEXT: ret
810 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshl.nxv2i64(<vscale x 2 x i1> %pg,
811 <vscale x 2 x i64> %a,
812 <vscale x 2 x i64> %b)
813 ret <vscale x 2 x i64> %out
814 }
816 ;
817 ; SQSHLR
818 ;
820 define <vscale x 16 x i8> @sqshlr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
821 ; CHECK-LABEL: sqshlr_i8:
822 ; CHECK: ptrue p0.b
823 ; CHECK-NEXT: sqshlr z0.b, p0/m, z0.b, z1.b
824 ; CHECK-NEXT: ret
825 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
826 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshl.nxv16i8(<vscale x 16 x i1> %pg,
827 <vscale x 16 x i8> %b,
828 <vscale x 16 x i8> %a)
829 ret <vscale x 16 x i8> %out
830 }
832 define <vscale x 8 x i16> @sqshlr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
833 ; CHECK-LABEL: sqshlr_i16:
834 ; CHECK: ptrue p0.h
835 ; CHECK-NEXT: sqshlr z0.h, p0/m, z0.h, z1.h
836 ; CHECK-NEXT: ret
837 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
838 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshl.nxv8i16(<vscale x 8 x i1> %pg,
839 <vscale x 8 x i16> %b,
840 <vscale x 8 x i16> %a)
841 ret <vscale x 8 x i16> %out
842 }
844 define <vscale x 4 x i32> @sqshlr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
845 ; CHECK-LABEL: sqshlr_i32:
846 ; CHECK: ptrue p0.s
847 ; CHECK-NEXT: sqshlr z0.s, p0/m, z0.s, z1.s
848 ; CHECK-NEXT: ret
849 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
850 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1> %pg,
851 <vscale x 4 x i32> %b,
852 <vscale x 4 x i32> %a)
853 ret <vscale x 4 x i32> %out
854 }
856 define <vscale x 2 x i64> @sqshlr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
857 ; CHECK-LABEL: sqshlr_i64:
858 ; CHECK: ptrue p0.d
859 ; CHECK-NEXT: sqshlr z0.d, p0/m, z0.d, z1.d
860 ; CHECK-NEXT: ret
861 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
862 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshl.nxv2i64(<vscale x 2 x i1> %pg,
863 <vscale x 2 x i64> %b,
864 <vscale x 2 x i64> %a)
865 ret <vscale x 2 x i64> %out
866 }
868 define <vscale x 2 x i64> @sqshlr_i64_noptrue(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
869 ; CHECK-LABEL: sqshlr_i64_noptrue:
870 ; CHECK: sqshl z1.d, p0/m, z1.d, z0.d
871 ; CHECK-NEXT: mov z0.d, z1.d
872 ; CHECK-NEXT: ret
873 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshl.nxv2i64(<vscale x 2 x i1> %pg,
874 <vscale x 2 x i64> %b,
875 <vscale x 2 x i64> %a)
876 ret <vscale x 2 x i64> %out
877 }
879 ;
880 ; SQSHL (Scalar)
881 ;
883 define <vscale x 16 x i8> @sqshl_n_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
884 ; CHECK-LABEL: sqshl_n_i8:
885 ; CHECK: sqshl z0.b, p0/m, z0.b, #7
886 ; CHECK-NEXT: ret
887 %dup = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 7)
888 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshl.nxv16i8(<vscale x 16 x i1> %pg,
889 <vscale x 16 x i8> %a,
890 <vscale x 16 x i8> %dup)
891 ret <vscale x 16 x i8> %out
892 }
894 define <vscale x 8 x i16> @sqshl_n_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
895 ; CHECK-LABEL: sqshl_n_i16:
896 ; CHECK: sqshl z0.h, p0/m, z0.h, #15
897 ; CHECK-NEXT: ret
898 %dup = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 15)
899 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshl.nxv8i16(<vscale x 8 x i1> %pg,
900 <vscale x 8 x i16> %a,
901 <vscale x 8 x i16> %dup)
902 ret <vscale x 8 x i16> %out
903 }
905 define <vscale x 4 x i32> @sqshl_n_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
906 ; CHECK-LABEL: sqshl_n_i32:
907 ; CHECK: sqshl z0.s, p0/m, z0.s, #31
908 ; CHECK-NEXT: ret
909 %dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 31)
910 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1> %pg,
911 <vscale x 4 x i32> %a,
912 <vscale x 4 x i32> %dup)
913 ret <vscale x 4 x i32> %out
914 }
916 define <vscale x 2 x i64> @sqshl_n_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
917 ; CHECK-LABEL: sqshl_n_i64:
918 ; CHECK: sqshl z0.d, p0/m, z0.d, #63
919 ; CHECK-NEXT: ret
920 %dup = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 63)
921 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshl.nxv2i64(<vscale x 2 x i1> %pg,
922 <vscale x 2 x i64> %a,
923 <vscale x 2 x i64> %dup)
924 ret <vscale x 2 x i64> %out
925 }
927 define <vscale x 16 x i8> @sqshl_n_i8_range(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
928 ; CHECK-LABEL: sqshl_n_i8_range:
929 ; CHECK: mov z1.b, #8
930 ; CHECK: sqshl z0.b, p0/m, z0.b, z1.b
931 ; CHECK-NEXT: ret
932 %dup = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 8)
933 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshl.nxv16i8(<vscale x 16 x i1> %pg,
934 <vscale x 16 x i8> %a,
935 <vscale x 16 x i8> %dup)
936 ret <vscale x 16 x i8> %out
937 }
939 define <vscale x 8 x i16> @sqshl_n_i16_range(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
940 ; CHECK-LABEL: sqshl_n_i16_range:
941 ; CHECK: mov z1.h, #16
942 ; CHECK: sqshl z0.h, p0/m, z0.h, z1.h
943 ; CHECK-NEXT: ret
944 %dup = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 16)
945 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshl.nxv8i16(<vscale x 8 x i1> %pg,
946 <vscale x 8 x i16> %a,
947 <vscale x 8 x i16> %dup)
948 ret <vscale x 8 x i16> %out
949 }
951 define <vscale x 4 x i32> @sqshl_n_i32_range(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
952 ; CHECK-LABEL: sqshl_n_i32_range:
953 ; CHECK: mov z1.s, #32
954 ; CHECK: sqshl z0.s, p0/m, z0.s, z1.s
955 ; CHECK-NEXT: ret
956 %dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 32)
957 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1> %pg,
958 <vscale x 4 x i32> %a,
959 <vscale x 4 x i32> %dup)
960 ret <vscale x 4 x i32> %out
961 }
963 define <vscale x 2 x i64> @sqshl_n_i64_range(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
964 ; CHECK-LABEL: sqshl_n_i64_range:
965 ; CHECK: mov z1.d, #64
966 ; CHECK: sqshl z0.d, p0/m, z0.d, z1.d
967 ; CHECK-NEXT: ret
968 %dup = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 64)
969 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshl.nxv2i64(<vscale x 2 x i1> %pg,
970 <vscale x 2 x i64> %a,
971 <vscale x 2 x i64> %dup)
972 ret <vscale x 2 x i64> %out
973 }
975 ;
976 ; SQSHLU
977 ;
979 define <vscale x 16 x i8> @sqshlu_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
980 ; CHECK-LABEL: sqshlu_i8:
981 ; CHECK: sqshlu z0.b, p0/m, z0.b, #2
982 ; CHECK-NEXT: ret
983 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1> %pg,
984 <vscale x 16 x i8> %a,
985 i32 2)
986 ret <vscale x 16 x i8> %out
987 }
989 define <vscale x 8 x i16> @sqshlu_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
990 ; CHECK-LABEL: sqshlu_i16:
991 ; CHECK: sqshlu z0.h, p0/m, z0.h, #3
992 ; CHECK-NEXT: ret
993 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1> %pg,
994 <vscale x 8 x i16> %a,
995 i32 3)
996 ret <vscale x 8 x i16> %out
997 }
999 define <vscale x 4 x i32> @sqshlu_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
1000 ; CHECK-LABEL: sqshlu_i32:
1001 ; CHECK: sqshlu z0.s, p0/m, z0.s, #29
1002 ; CHECK-NEXT: ret
1003 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1> %pg,
1004 <vscale x 4 x i32> %a,
1005 i32 29)
1006 ret <vscale x 4 x i32> %out
1007 }
1009 define <vscale x 2 x i64> @sqshlu_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
1010 ; CHECK-LABEL: sqshlu_i64:
1011 ; CHECK: sqshlu z0.d, p0/m, z0.d, #62
1012 ; CHECK-NEXT: ret
1013 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1> %pg,
1014 <vscale x 2 x i64> %a,
1015 i32 62)
1016 ret <vscale x 2 x i64> %out
1017 }
1019 ;
1020 ; SQSUB
1021 ;
1023 define <vscale x 16 x i8> @sqsub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1024 ; CHECK-LABEL: sqsub_i8:
1025 ; CHECK: sqsub z0.b, p0/m, z0.b, z1.b
1026 ; CHECK-NEXT: ret
1027 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1> %pg,
1028 <vscale x 16 x i8> %a,
1029 <vscale x 16 x i8> %b)
1030 ret <vscale x 16 x i8> %out
1031 }
1033 define <vscale x 8 x i16> @sqsub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1034 ; CHECK-LABEL: sqsub_i16:
1035 ; CHECK: sqsub z0.h, p0/m, z0.h, z1.h
1036 ; CHECK-NEXT: ret
1037 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1> %pg,
1038 <vscale x 8 x i16> %a,
1039 <vscale x 8 x i16> %b)
1040 ret <vscale x 8 x i16> %out
1041 }
1043 define <vscale x 4 x i32> @sqsub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1044 ; CHECK-LABEL: sqsub_i32:
1045 ; CHECK: sqsub z0.s, p0/m, z0.s, z1.s
1046 ; CHECK-NEXT: ret
1047 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> %pg,
1048 <vscale x 4 x i32> %a,
1049 <vscale x 4 x i32> %b)
1050 ret <vscale x 4 x i32> %out
1051 }
1053 define <vscale x 2 x i64> @sqsub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1054 ; CHECK-LABEL: sqsub_i64:
1055 ; CHECK: sqsub z0.d, p0/m, z0.d, z1.d
1056 ; CHECK-NEXT: ret
1057 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1> %pg,
1058 <vscale x 2 x i64> %a,
1059 <vscale x 2 x i64> %b)
1060 ret <vscale x 2 x i64> %out
1061 }
1063 ;
1064 ; SQSUBR
1065 ;
1067 define <vscale x 16 x i8> @sqsubr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1068 ; CHECK-LABEL: sqsubr_i8:
1069 ; CHECK: sqsubr z0.b, p0/m, z0.b, z1.b
1070 ; CHECK-NEXT: ret
1071 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1> %pg,
1072 <vscale x 16 x i8> %a,
1073 <vscale x 16 x i8> %b)
1074 ret <vscale x 16 x i8> %out
1075 }
1077 define <vscale x 8 x i16> @sqsubr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1078 ; CHECK-LABEL: sqsubr_i16:
1079 ; CHECK: sqsubr z0.h, p0/m, z0.h, z1.h
1080 ; CHECK-NEXT: ret
1081 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1> %pg,
1082 <vscale x 8 x i16> %a,
1083 <vscale x 8 x i16> %b)
1084 ret <vscale x 8 x i16> %out
1085 }
1087 define <vscale x 4 x i32> @sqsubr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1088 ; CHECK-LABEL: sqsubr_i32:
1089 ; CHECK: sqsubr z0.s, p0/m, z0.s, z1.s
1090 ; CHECK-NEXT: ret
1091 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> %pg,
1092 <vscale x 4 x i32> %a,
1093 <vscale x 4 x i32> %b)
1094 ret <vscale x 4 x i32> %out
1095 }
1097 define <vscale x 2 x i64> @sqsubr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1098 ; CHECK-LABEL: sqsubr_i64:
1099 ; CHECK: sqsubr z0.d, p0/m, z0.d, z1.d
1100 ; CHECK-NEXT: ret
1101 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1> %pg,
1102 <vscale x 2 x i64> %a,
1103 <vscale x 2 x i64> %b)
1104 ret <vscale x 2 x i64> %out
1105 }
1107 ;
1108 ; SRHADD
1109 ;
1111 define <vscale x 16 x i8> @srhadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1112 ; CHECK-LABEL: srhadd_i8:
1113 ; CHECK: srhadd z0.b, p0/m, z0.b, z1.b
1114 ; CHECK-NEXT: ret
1115 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1> %pg,
1116 <vscale x 16 x i8> %a,
1117 <vscale x 16 x i8> %b)
1118 ret <vscale x 16 x i8> %out
1119 }
1121 define <vscale x 8 x i16> @srhadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1122 ; CHECK-LABEL: srhadd_i16:
1123 ; CHECK: srhadd z0.h, p0/m, z0.h, z1.h
1124 ; CHECK-NEXT: ret
1125 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1> %pg,
1126 <vscale x 8 x i16> %a,
1127 <vscale x 8 x i16> %b)
1128 ret <vscale x 8 x i16> %out
1129 }
1131 define <vscale x 4 x i32> @srhadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1132 ; CHECK-LABEL: srhadd_i32:
1133 ; CHECK: srhadd z0.s, p0/m, z0.s, z1.s
1134 ; CHECK-NEXT: ret
1135 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> %pg,
1136 <vscale x 4 x i32> %a,
1137 <vscale x 4 x i32> %b)
1138 ret <vscale x 4 x i32> %out
1139 }
1141 define <vscale x 2 x i64> @srhadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1142 ; CHECK-LABEL: srhadd_i64:
1143 ; CHECK: srhadd z0.d, p0/m, z0.d, z1.d
1144 ; CHECK-NEXT: ret
1145 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1> %pg,
1146 <vscale x 2 x i64> %a,
1147 <vscale x 2 x i64> %b)
1148 ret <vscale x 2 x i64> %out
1149 }
1151 ;
1152 ; SRI
1153 ;
1155 define <vscale x 16 x i8> @sri_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1156 ; CHECK-LABEL: sri_i8:
1157 ; CHECK: sri z0.b, z1.b, #1
1158 ; CHECK-NEXT: ret
1159 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sri.nxv16i8(<vscale x 16 x i8> %a,
1160 <vscale x 16 x i8> %b,
1161 i32 1)
1162 ret <vscale x 16 x i8> %out
1163 }
1165 define <vscale x 8 x i16> @sri_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1166 ; CHECK-LABEL: sri_i16:
1167 ; CHECK: sri z0.h, z1.h, #16
1168 ; CHECK-NEXT: ret
1169 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sri.nxv8i16(<vscale x 8 x i16> %a,
1170 <vscale x 8 x i16> %b,
1171 i32 16)
1172 ret <vscale x 8 x i16> %out
1173 }
1175 define <vscale x 4 x i32> @sri_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1176 ; CHECK-LABEL: sri_i32:
1177 ; CHECK: sri z0.s, z1.s, #32
1178 ; CHECK-NEXT: ret
1179 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sri.nxv4i32(<vscale x 4 x i32> %a,
1180 <vscale x 4 x i32> %b,
1181 i32 32);
1182 ret <vscale x 4 x i32> %out
1183 }
1185 define <vscale x 2 x i64> @sri_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1186 ; CHECK-LABEL: sri_i64:
1187 ; CHECK: sri z0.d, z1.d, #64
1188 ; CHECK-NEXT: ret
1189 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sri.nxv2i64(<vscale x 2 x i64> %a,
1190 <vscale x 2 x i64> %b,
1191 i32 64)
1192 ret <vscale x 2 x i64> %out
1193 }
1195 ;
1196 ; SRSHL
1197 ;
1199 define <vscale x 16 x i8> @srshl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1200 ; CHECK-LABEL: srshl_i8:
1201 ; CHECK: srshl z0.b, p0/m, z0.b, z1.b
1202 ; CHECK-NEXT: ret
1203 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.srshl.nxv16i8(<vscale x 16 x i1> %pg,
1204 <vscale x 16 x i8> %a,
1205 <vscale x 16 x i8> %b)
1206 ret <vscale x 16 x i8> %out
1207 }
1209 define <vscale x 8 x i16> @srshl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1210 ; CHECK-LABEL: srshl_i16:
1211 ; CHECK: srshl z0.h, p0/m, z0.h, z1.h
1212 ; CHECK-NEXT: ret
1213 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale x 8 x i1> %pg,
1214 <vscale x 8 x i16> %a,
1215 <vscale x 8 x i16> %b)
1216 ret <vscale x 8 x i16> %out
1217 }
1219 define <vscale x 4 x i32> @srshl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1220 ; CHECK-LABEL: srshl_i32:
1221 ; CHECK: srshl z0.s, p0/m, z0.s, z1.s
1222 ; CHECK-NEXT: ret
1223 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.srshl.nxv4i32(<vscale x 4 x i1> %pg,
1224 <vscale x 4 x i32> %a,
1225 <vscale x 4 x i32> %b)
1226 ret <vscale x 4 x i32> %out
1227 }
1229 define <vscale x 2 x i64> @srshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1230 ; CHECK-LABEL: srshl_i64:
1231 ; CHECK: srshl z0.d, p0/m, z0.d, z1.d
1232 ; CHECK-NEXT: ret
1233 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.srshl.nxv2i64(<vscale x 2 x i1> %pg,
1234 <vscale x 2 x i64> %a,
1235 <vscale x 2 x i64> %b)
1236 ret <vscale x 2 x i64> %out
1237 }
1239 ;
1240 ; SRSHLR
1241 ;
1243 define <vscale x 16 x i8> @srshlr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1244 ; CHECK-LABEL: srshlr_i8:
1245 ; CHECK: ptrue p0.b
1246 ; CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.b
1247 ; CHECK-NEXT: ret
1248 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
1249 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.srshl.nxv16i8(<vscale x 16 x i1> %pg,
1250 <vscale x 16 x i8> %b,
1251 <vscale x 16 x i8> %a)
1252 ret <vscale x 16 x i8> %out
1253 }
1255 define <vscale x 8 x i16> @srshlr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1256 ; CHECK-LABEL: srshlr_i16:
1257 ; CHECK: ptrue p0.h
1258 ; CHECK-NEXT: srshlr z0.h, p0/m, z0.h, z1.h
1259 ; CHECK-NEXT: ret
1260 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
1261 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale x 8 x i1> %pg,
1262 <vscale x 8 x i16> %b,
1263 <vscale x 8 x i16> %a)
1264 ret <vscale x 8 x i16> %out
1265 }
1267 define <vscale x 4 x i32> @srshlr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1268 ; CHECK-LABEL: srshlr_i32:
1269 ; CHECK: ptrue p0.s
1270 ; CHECK-NEXT: srshlr z0.s, p0/m, z0.s, z1.s
1271 ; CHECK-NEXT: ret
1272 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
1273 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.srshl.nxv4i32(<vscale x 4 x i1> %pg,
1274 <vscale x 4 x i32> %b,
1275 <vscale x 4 x i32> %a)
1276 ret <vscale x 4 x i32> %out
1277 }
1279 define <vscale x 2 x i64> @srshlr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1280 ; CHECK-LABEL: srshlr_i64:
1281 ; CHECK: ptrue p0.d
1282 ; CHECK-NEXT: srshlr z0.d, p0/m, z0.d, z1.d
1283 ; CHECK-NEXT: ret
1284 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
1285 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.srshl.nxv2i64(<vscale x 2 x i1> %pg,
1286 <vscale x 2 x i64> %b,
1287 <vscale x 2 x i64> %a)
1288 ret <vscale x 2 x i64> %out
1289 }
1291 define <vscale x 2 x i64> @srshlr_i64_noptrue(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1292 ; CHECK-LABEL: srshlr_i64_noptrue:
1293 ; CHECK: srshl z1.d, p0/m, z1.d, z0.d
1294 ; CHECK-NEXT: mov z0.d, z1.d
1295 ; CHECK-NEXT: ret
1296 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.srshl.nxv2i64(<vscale x 2 x i1> %pg,
1297 <vscale x 2 x i64> %b,
1298 <vscale x 2 x i64> %a)
1299 ret <vscale x 2 x i64> %out
1300 }
1302 ;
1303 ; SRSHR
1304 ;
1306 define <vscale x 16 x i8> @srshr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
1307 ; CHECK-LABEL: srshr_i8:
1308 ; CHECK: srshr z0.b, p0/m, z0.b, #8
1309 ; CHECK-NEXT: ret
1310 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.srshr.nxv16i8(<vscale x 16 x i1> %pg,
1311 <vscale x 16 x i8> %a,
1312 i32 8)
1313 ret <vscale x 16 x i8> %out
1314 }
1316 define <vscale x 8 x i16> @srshr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
1317 ; CHECK-LABEL: srshr_i16:
1318 ; CHECK: srshr z0.h, p0/m, z0.h, #1
1319 ; CHECK-NEXT: ret
1320 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1> %pg,
1321 <vscale x 8 x i16> %a,
1322 i32 1)
1323 ret <vscale x 8 x i16> %out
1324 }
1326 define <vscale x 4 x i32> @srshr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
1327 ; CHECK-LABEL: srshr_i32:
1328 ; CHECK: srshr z0.s, p0/m, z0.s, #22
1329 ; CHECK-NEXT: ret
1330 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1> %pg,
1331 <vscale x 4 x i32> %a,
1332 i32 22)
1333 ret <vscale x 4 x i32> %out
1334 }
1336 define <vscale x 2 x i64> @srshr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
1337 ; CHECK-LABEL: srshr_i64:
1338 ; CHECK: srshr z0.d, p0/m, z0.d, #54
1339 ; CHECK-NEXT: ret
1340 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.srshr.nxv2i64(<vscale x 2 x i1> %pg,
1341 <vscale x 2 x i64> %a,
1342 i32 54)
1343 ret <vscale x 2 x i64> %out
1344 }
1346 ;
1347 ; SRSRA
1348 ;
1350 define <vscale x 16 x i8> @srsra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1351 ; CHECK-LABEL: srsra_i8:
1352 ; CHECK: srsra z0.b, z1.b, #2
1353 ; CHECK-NEXT: ret
1354 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.srsra.nxv16i8(<vscale x 16 x i8> %a,
1355 <vscale x 16 x i8> %b,
1356 i32 2)
1357 ret <vscale x 16 x i8> %out
1358 }
1360 define <vscale x 8 x i16> @srsra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1361 ; CHECK-LABEL: srsra_i16:
1362 ; CHECK: srsra z0.h, z1.h, #15
1363 ; CHECK-NEXT: ret
1364 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.srsra.nxv8i16(<vscale x 8 x i16> %a,
1365 <vscale x 8 x i16> %b,
1366 i32 15)
1367 ret <vscale x 8 x i16> %out
1368 }
1370 define <vscale x 4 x i32> @srsra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1371 ; CHECK-LABEL: srsra_i32:
1372 ; CHECK: srsra z0.s, z1.s, #12
1373 ; CHECK-NEXT: ret
1374 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.srsra.nxv4i32(<vscale x 4 x i32> %a,
1375 <vscale x 4 x i32> %b,
1376 i32 12)
1377 ret <vscale x 4 x i32> %out
1378 }
1380 define <vscale x 2 x i64> @srsra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1381 ; CHECK-LABEL: srsra_i64:
1382 ; CHECK: srsra z0.d, z1.d, #44
1383 ; CHECK-NEXT: ret
1384 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.srsra.nxv2i64(<vscale x 2 x i64> %a,
1385 <vscale x 2 x i64> %b,
1386 i32 44)
1387 ret <vscale x 2 x i64> %out
1388 }
1390 ;
1391 ; SSRA
1392 ;
1394 define <vscale x 16 x i8> @ssra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1395 ; CHECK-LABEL: ssra_i8:
1396 ; CHECK: ssra z0.b, z1.b, #3
1397 ; CHECK-NEXT: ret
1398 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.ssra.nxv16i8(<vscale x 16 x i8> %a,
1399 <vscale x 16 x i8> %b,
1400 i32 3)
1401 ret <vscale x 16 x i8> %out
1402 }
1404 define <vscale x 8 x i16> @ssra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1405 ; CHECK-LABEL: ssra_i16:
1406 ; CHECK: ssra z0.h, z1.h, #14
1407 ; CHECK-NEXT: ret
1408 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssra.nxv8i16(<vscale x 8 x i16> %a,
1409 <vscale x 8 x i16> %b,
1410 i32 14)
1411 ret <vscale x 8 x i16> %out
1412 }
1414 define <vscale x 4 x i32> @ssra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1415 ; CHECK-LABEL: ssra_i32:
1416 ; CHECK: ssra z0.s, z1.s, #2
1417 ; CHECK-NEXT: ret
1418 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssra.nxv4i32(<vscale x 4 x i32> %a,
1419 <vscale x 4 x i32> %b,
1420 i32 2)
1421 ret <vscale x 4 x i32> %out
1422 }
1424 define <vscale x 2 x i64> @ssra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1425 ; CHECK-LABEL: ssra_i64:
1426 ; CHECK: ssra z0.d, z1.d, #34
1427 ; CHECK-NEXT: ret
1428 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssra.nxv2i64(<vscale x 2 x i64> %a,
1429 <vscale x 2 x i64> %b,
1430 i32 34)
1431 ret <vscale x 2 x i64> %out
1432 }
1434 ;
1435 ; SUQADD
1436 ;
1438 define <vscale x 16 x i8> @suqadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1439 ; CHECK-LABEL: suqadd_i8:
1440 ; CHECK: suqadd z0.b, p0/m, z0.b, z1.b
1441 ; CHECK-NEXT: ret
1442 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.suqadd.nxv16i8(<vscale x 16 x i1> %pg,
1443 <vscale x 16 x i8> %a,
1444 <vscale x 16 x i8> %b)
1445 ret <vscale x 16 x i8> %out
1446 }
1448 define <vscale x 8 x i16> @suqadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1449 ; CHECK-LABEL: suqadd_i16:
1450 ; CHECK: suqadd z0.h, p0/m, z0.h, z1.h
1451 ; CHECK-NEXT: ret
1452 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.suqadd.nxv8i16(<vscale x 8 x i1> %pg,
1453 <vscale x 8 x i16> %a,
1454 <vscale x 8 x i16> %b)
1455 ret <vscale x 8 x i16> %out
1456 }
1458 define <vscale x 4 x i32> @suqadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1459 ; CHECK-LABEL: suqadd_i32:
1460 ; CHECK: suqadd z0.s, p0/m, z0.s, z1.s
1461 ; CHECK-NEXT: ret
1462 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.suqadd.nxv4i32(<vscale x 4 x i1> %pg,
1463 <vscale x 4 x i32> %a,
1464 <vscale x 4 x i32> %b)
1465 ret <vscale x 4 x i32> %out
1466 }
1468 define <vscale x 2 x i64> @suqadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1469 ; CHECK-LABEL: suqadd_i64:
1470 ; CHECK: suqadd z0.d, p0/m, z0.d, z1.d
1471 ; CHECK-NEXT: ret
1472 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.suqadd.nxv2i64(<vscale x 2 x i1> %pg,
1473 <vscale x 2 x i64> %a,
1474 <vscale x 2 x i64> %b)
1475 ret <vscale x 2 x i64> %out
1476 }
1478 ;
1479 ; UABA
1480 ;
1482 define <vscale x 16 x i8> @uaba_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
1483 ; CHECK-LABEL: uaba_i8:
1484 ; CHECK: uaba z0.b, z1.b, z2.b
1485 ; CHECK-NEXT: ret
1486 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uaba.nxv16i8(<vscale x 16 x i8> %a,
1487 <vscale x 16 x i8> %b,
1488 <vscale x 16 x i8> %c)
1489 ret <vscale x 16 x i8> %out
1490 }
1492 define <vscale x 8 x i16> @uaba_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
1493 ; CHECK-LABEL: uaba_i16:
1494 ; CHECK: uaba z0.h, z1.h, z2.h
1495 ; CHECK-NEXT: ret
1496 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uaba.nxv8i16(<vscale x 8 x i16> %a,
1497 <vscale x 8 x i16> %b,
1498 <vscale x 8 x i16> %c)
1499 ret <vscale x 8 x i16> %out
1500 }
1502 define <vscale x 4 x i32> @uaba_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
1503 ; CHECK-LABEL: uaba_i32:
1504 ; CHECK: uaba z0.s, z1.s, z2.s
1505 ; CHECK-NEXT: ret
1506 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uaba.nxv4i32(<vscale x 4 x i32> %a,
1507 <vscale x 4 x i32> %b,
1508 <vscale x 4 x i32> %c)
1509 ret <vscale x 4 x i32> %out
1510 }
1512 define <vscale x 2 x i64> @uaba_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
1513 ; CHECK-LABEL: uaba_i64:
1514 ; CHECK: uaba z0.d, z1.d, z2.d
1515 ; CHECK-NEXT: ret
1516 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uaba.nxv2i64(<vscale x 2 x i64> %a,
1517 <vscale x 2 x i64> %b,
1518 <vscale x 2 x i64> %c)
1519 ret <vscale x 2 x i64> %out
1520 }
1522 ;
1523 ; UHADD
1524 ;
1526 define <vscale x 16 x i8> @uhadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1527 ; CHECK-LABEL: uhadd_i8:
1528 ; CHECK: uhadd z0.b, p0/m, z0.b, z1.b
1529 ; CHECK-NEXT: ret
1530 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1> %pg,
1531 <vscale x 16 x i8> %a,
1532 <vscale x 16 x i8> %b)
1533 ret <vscale x 16 x i8> %out
1534 }
1536 define <vscale x 8 x i16> @uhadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1537 ; CHECK-LABEL: uhadd_i16:
1538 ; CHECK: uhadd z0.h, p0/m, z0.h, z1.h
1539 ; CHECK-NEXT: ret
1540 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1> %pg,
1541 <vscale x 8 x i16> %a,
1542 <vscale x 8 x i16> %b)
1543 ret <vscale x 8 x i16> %out
1544 }
1546 define <vscale x 4 x i32> @uhadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1547 ; CHECK-LABEL: uhadd_i32:
1548 ; CHECK: uhadd z0.s, p0/m, z0.s, z1.s
1549 ; CHECK-NEXT: ret
1550 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> %pg,
1551 <vscale x 4 x i32> %a,
1552 <vscale x 4 x i32> %b)
1553 ret <vscale x 4 x i32> %out
1554 }
1556 define <vscale x 2 x i64> @uhadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1557 ; CHECK-LABEL: uhadd_i64:
1558 ; CHECK: uhadd z0.d, p0/m, z0.d, z1.d
1559 ; CHECK-NEXT: ret
1560 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1> %pg,
1561 <vscale x 2 x i64> %a,
1562 <vscale x 2 x i64> %b)
1563 ret <vscale x 2 x i64> %out
1564 }
1566 ;
1567 ; UHSUB
1568 ;
1570 define <vscale x 16 x i8> @uhsub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1571 ; CHECK-LABEL: uhsub_i8:
1572 ; CHECK: uhsub z0.b, p0/m, z0.b, z1.b
1573 ; CHECK-NEXT: ret
1574 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1> %pg,
1575 <vscale x 16 x i8> %a,
1576 <vscale x 16 x i8> %b)
1577 ret <vscale x 16 x i8> %out
1578 }
1580 define <vscale x 8 x i16> @uhsub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1581 ; CHECK-LABEL: uhsub_i16:
1582 ; CHECK: uhsub z0.h, p0/m, z0.h, z1.h
1583 ; CHECK-NEXT: ret
1584 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1> %pg,
1585 <vscale x 8 x i16> %a,
1586 <vscale x 8 x i16> %b)
1587 ret <vscale x 8 x i16> %out
1588 }
1590 define <vscale x 4 x i32> @uhsub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1591 ; CHECK-LABEL: uhsub_i32:
1592 ; CHECK: uhsub z0.s, p0/m, z0.s, z1.s
1593 ; CHECK-NEXT: ret
1594 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> %pg,
1595 <vscale x 4 x i32> %a,
1596 <vscale x 4 x i32> %b)
1597 ret <vscale x 4 x i32> %out
1598 }
1600 define <vscale x 2 x i64> @uhsub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1601 ; CHECK-LABEL: uhsub_i64:
1602 ; CHECK: uhsub z0.d, p0/m, z0.d, z1.d
1603 ; CHECK-NEXT: ret
1604 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1> %pg,
1605 <vscale x 2 x i64> %a,
1606 <vscale x 2 x i64> %b)
1607 ret <vscale x 2 x i64> %out
1608 }
1610 ;
1611 ; UHSUBR
1612 ;
1614 define <vscale x 16 x i8> @uhsubr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1615 ; CHECK-LABEL: uhsubr_i8:
1616 ; CHECK: uhsubr z0.b, p0/m, z0.b, z1.b
1617 ; CHECK-NEXT: ret
1618 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1> %pg,
1619 <vscale x 16 x i8> %a,
1620 <vscale x 16 x i8> %b)
1621 ret <vscale x 16 x i8> %out
1622 }
1624 define <vscale x 8 x i16> @uhsubr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1625 ; CHECK-LABEL: uhsubr_i16:
1626 ; CHECK: uhsubr z0.h, p0/m, z0.h, z1.h
1627 ; CHECK-NEXT: ret
1628 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1> %pg,
1629 <vscale x 8 x i16> %a,
1630 <vscale x 8 x i16> %b)
1631 ret <vscale x 8 x i16> %out
1632 }
1634 define <vscale x 4 x i32> @uhsubr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1635 ; CHECK-LABEL: uhsubr_i32:
1636 ; CHECK: uhsubr z0.s, p0/m, z0.s, z1.s
1637 ; CHECK-NEXT: ret
1638 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> %pg,
1639 <vscale x 4 x i32> %a,
1640 <vscale x 4 x i32> %b)
1641 ret <vscale x 4 x i32> %out
1642 }
1644 define <vscale x 2 x i64> @uhsubr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1645 ; CHECK-LABEL: uhsubr_i64:
1646 ; CHECK: uhsubr z0.d, p0/m, z0.d, z1.d
1647 ; CHECK-NEXT: ret
1648 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1> %pg,
1649 <vscale x 2 x i64> %a,
1650 <vscale x 2 x i64> %b)
1651 ret <vscale x 2 x i64> %out
1652 }
1654 ;
1655 ; UQADD
1656 ;
1658 define <vscale x 16 x i8> @uqadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1659 ; CHECK-LABEL: uqadd_i8:
1660 ; CHECK: uqadd z0.b, p0/m, z0.b, z1.b
1661 ; CHECK-NEXT: ret
1662 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1> %pg,
1663 <vscale x 16 x i8> %a,
1664 <vscale x 16 x i8> %b)
1665 ret <vscale x 16 x i8> %out
1666 }
1668 define <vscale x 8 x i16> @uqadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1669 ; CHECK-LABEL: uqadd_i16:
1670 ; CHECK: uqadd z0.h, p0/m, z0.h, z1.h
1671 ; CHECK-NEXT: ret
1672 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1> %pg,
1673 <vscale x 8 x i16> %a,
1674 <vscale x 8 x i16> %b)
1675 ret <vscale x 8 x i16> %out
1676 }
1678 define <vscale x 4 x i32> @uqadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1679 ; CHECK-LABEL: uqadd_i32:
1680 ; CHECK: uqadd z0.s, p0/m, z0.s, z1.s
1681 ; CHECK-NEXT: ret
1682 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> %pg,
1683 <vscale x 4 x i32> %a,
1684 <vscale x 4 x i32> %b)
1685 ret <vscale x 4 x i32> %out
1686 }
1688 define <vscale x 2 x i64> @uqadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1689 ; CHECK-LABEL: uqadd_i64:
1690 ; CHECK: uqadd z0.d, p0/m, z0.d, z1.d
1691 ; CHECK-NEXT: ret
1692 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1> %pg,
1693 <vscale x 2 x i64> %a,
1694 <vscale x 2 x i64> %b)
1695 ret <vscale x 2 x i64> %out
1696 }
1698 ;
1699 ; UQRSHL
1700 ;
1702 define <vscale x 16 x i8> @uqrshl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1703 ; CHECK-LABEL: uqrshl_i8:
1704 ; CHECK: uqrshl z0.b, p0/m, z0.b, z1.b
1705 ; CHECK-NEXT: ret
1706 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshl.nxv16i8(<vscale x 16 x i1> %pg,
1707 <vscale x 16 x i8> %a,
1708 <vscale x 16 x i8> %b)
1709 ret <vscale x 16 x i8> %out
1710 }
1712 define <vscale x 8 x i16> @uqrshl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1713 ; CHECK-LABEL: uqrshl_i16:
1714 ; CHECK: uqrshl z0.h, p0/m, z0.h, z1.h
1715 ; CHECK-NEXT: ret
1716 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshl.nxv8i16(<vscale x 8 x i1> %pg,
1717 <vscale x 8 x i16> %a,
1718 <vscale x 8 x i16> %b)
1719 ret <vscale x 8 x i16> %out
1720 }
1722 define <vscale x 4 x i32> @uqrshl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1723 ; CHECK-LABEL: uqrshl_i32:
1724 ; CHECK: uqrshl z0.s, p0/m, z0.s, z1.s
1725 ; CHECK-NEXT: ret
1726 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.nxv4i32(<vscale x 4 x i1> %pg,
1727 <vscale x 4 x i32> %a,
1728 <vscale x 4 x i32> %b)
1729 ret <vscale x 4 x i32> %out
1730 }
1732 define <vscale x 2 x i64> @uqrshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1733 ; CHECK-LABEL: uqrshl_i64:
1734 ; CHECK: uqrshl z0.d, p0/m, z0.d, z1.d
1735 ; CHECK-NEXT: ret
1736 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqrshl.nxv2i64(<vscale x 2 x i1> %pg,
1737 <vscale x 2 x i64> %a,
1738 <vscale x 2 x i64> %b)
1739 ret <vscale x 2 x i64> %out
1740 }
1742 ;
1743 ; UQRSHLR
1744 ;
1746 define <vscale x 16 x i8> @uqrshlr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1747 ; CHECK-LABEL: uqrshlr_i8:
1748 ; CHECK: ptrue p0.b
1749 ; CHECK-NEXT: uqrshlr z0.b, p0/m, z0.b, z1.b
1750 ; CHECK-NEXT: ret
1751 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
1752 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshl.nxv16i8(<vscale x 16 x i1> %pg,
1753 <vscale x 16 x i8> %b,
1754 <vscale x 16 x i8> %a)
1755 ret <vscale x 16 x i8> %out
1756 }
1758 define <vscale x 8 x i16> @uqrshlr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1759 ; CHECK-LABEL: uqrshlr_i16:
1760 ; CHECK: ptrue p0.h
1761 ; CHECK-NEXT: uqrshlr z0.h, p0/m, z0.h, z1.h
1762 ; CHECK-NEXT: ret
1763 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
1764 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshl.nxv8i16(<vscale x 8 x i1> %pg,
1765 <vscale x 8 x i16> %b,
1766 <vscale x 8 x i16> %a)
1767 ret <vscale x 8 x i16> %out
1768 }
1770 define <vscale x 4 x i32> @uqrshlr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1771 ; CHECK-LABEL: uqrshlr_i32:
1772 ; CHECK: ptrue p0.s
1773 ; CHECK-NEXT: uqrshlr z0.s, p0/m, z0.s, z1.s
1774 ; CHECK-NEXT: ret
1775 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
1776 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.nxv4i32(<vscale x 4 x i1> %pg,
1777 <vscale x 4 x i32> %b,
1778 <vscale x 4 x i32> %a)
1779 ret <vscale x 4 x i32> %out
1780 }
1782 define <vscale x 2 x i64> @uqrshlr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1783 ; CHECK-LABEL: uqrshlr_i64:
1784 ; CHECK: ptrue p0.d
1785 ; CHECK-NEXT: uqrshlr z0.d, p0/m, z0.d, z1.d
1786 ; CHECK-NEXT: ret
1787 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
1788 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqrshl.nxv2i64(<vscale x 2 x i1> %pg,
1789 <vscale x 2 x i64> %b,
1790 <vscale x 2 x i64> %a)
1791 ret <vscale x 2 x i64> %out
1792 }
1794 define <vscale x 2 x i64> @uqrshlr_i64_noptrue(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1795 ; CHECK-LABEL: uqrshlr_i64_noptrue:
1796 ; CHECK: uqrshl z1.d, p0/m, z1.d, z0.d
1797 ; CHECK-NEXT: mov z0.d, z1.d
1798 ; CHECK-NEXT: ret
1799 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqrshl.nxv2i64(<vscale x 2 x i1> %pg,
1800 <vscale x 2 x i64> %b,
1801 <vscale x 2 x i64> %a)
1802 ret <vscale x 2 x i64> %out
1803 }
1805 ;
1806 ; UQSHL (Vectors)
1807 ;
1809 define <vscale x 16 x i8> @uqshl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1810 ; CHECK-LABEL: uqshl_i8:
1811 ; CHECK: uqshl z0.b, p0/m, z0.b, z1.b
1812 ; CHECK-NEXT: ret
1813 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshl.nxv16i8(<vscale x 16 x i1> %pg,
1814 <vscale x 16 x i8> %a,
1815 <vscale x 16 x i8> %b)
1816 ret <vscale x 16 x i8> %out
1817 }
1819 define <vscale x 8 x i16> @uqshl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1820 ; CHECK-LABEL: uqshl_i16:
1821 ; CHECK: uqshl z0.h, p0/m, z0.h, z1.h
1822 ; CHECK-NEXT: ret
1823 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshl.nxv8i16(<vscale x 8 x i1> %pg,
1824 <vscale x 8 x i16> %a,
1825 <vscale x 8 x i16> %b)
1826 ret <vscale x 8 x i16> %out
1827 }
1829 define <vscale x 4 x i32> @uqshl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1830 ; CHECK-LABEL: uqshl_i32:
1831 ; CHECK: uqshl z0.s, p0/m, z0.s, z1.s
1832 ; CHECK-NEXT: ret
1833 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1> %pg,
1834 <vscale x 4 x i32> %a,
1835 <vscale x 4 x i32> %b)
1836 ret <vscale x 4 x i32> %out
1837 }
1839 define <vscale x 2 x i64> @uqshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1840 ; CHECK-LABEL: uqshl_i64:
1841 ; CHECK: uqshl z0.d, p0/m, z0.d, z1.d
1842 ; CHECK-NEXT: ret
1843 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.nxv2i64(<vscale x 2 x i1> %pg,
1844 <vscale x 2 x i64> %a,
1845 <vscale x 2 x i64> %b)
1846 ret <vscale x 2 x i64> %out
1847 }
1849 ;
1850 ; UQSHLR
1851 ;
1853 define <vscale x 16 x i8> @uqshlr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1854 ; CHECK-LABEL: uqshlr_i8:
1855 ; CHECK: ptrue p0.b
1856 ; CHECK-NEXT: uqshlr z0.b, p0/m, z0.b, z1.b
1857 ; CHECK-NEXT: ret
1858 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
1859 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshl.nxv16i8(<vscale x 16 x i1> %pg,
1860 <vscale x 16 x i8> %b,
1861 <vscale x 16 x i8> %a)
1862 ret <vscale x 16 x i8> %out
1863 }
1865 define <vscale x 8 x i16> @uqshlr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1866 ; CHECK-LABEL: uqshlr_i16:
1867 ; CHECK: ptrue p0.h
1868 ; CHECK-NEXT: uqshlr z0.h, p0/m, z0.h, z1.h
1869 ; CHECK-NEXT: ret
1870 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
1871 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshl.nxv8i16(<vscale x 8 x i1> %pg,
1872 <vscale x 8 x i16> %b,
1873 <vscale x 8 x i16> %a)
1874 ret <vscale x 8 x i16> %out
1875 }
1877 define <vscale x 4 x i32> @uqshlr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1878 ; CHECK-LABEL: uqshlr_i32:
1879 ; CHECK: ptrue p0.s
1880 ; CHECK-NEXT: uqshlr z0.s, p0/m, z0.s, z1.s
1881 ; CHECK-NEXT: ret
1882 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
1883 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1> %pg,
1884 <vscale x 4 x i32> %b,
1885 <vscale x 4 x i32> %a)
1886 ret <vscale x 4 x i32> %out
1887 }
1889 define <vscale x 2 x i64> @uqshlr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1890 ; CHECK-LABEL: uqshlr_i64:
1891 ; CHECK: ptrue p0.d
1892 ; CHECK-NEXT: uqshlr z0.d, p0/m, z0.d, z1.d
1893 ; CHECK-NEXT: ret
1894 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
1895 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.nxv2i64(<vscale x 2 x i1> %pg,
1896 <vscale x 2 x i64> %b,
1897 <vscale x 2 x i64> %a)
1898 ret <vscale x 2 x i64> %out
1899 }
1901 define <vscale x 2 x i64> @uqshlr_i64_noptrue(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1902 ; CHECK-LABEL: uqshlr_i64_noptrue:
1903 ; CHECK: uqshl z1.d, p0/m, z1.d, z0.d
1904 ; CHECK-NEXT: mov z0.d, z1.d
1905 ; CHECK-NEXT: ret
1906 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.nxv2i64(<vscale x 2 x i1> %pg,
1907 <vscale x 2 x i64> %b,
1908 <vscale x 2 x i64> %a)
1909 ret <vscale x 2 x i64> %out
1910 }
1912 ;
1913 ; UQSHL (Scalar)
1914 ;
1916 define <vscale x 16 x i8> @uqshl_n_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
1917 ; CHECK-LABEL: uqshl_n_i8:
1918 ; CHECK: uqshl z0.b, p0/m, z0.b, #7
1919 ; CHECK-NEXT: ret
1920 %dup = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 7)
1921 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshl.nxv16i8(<vscale x 16 x i1> %pg,
1922 <vscale x 16 x i8> %a,
1923 <vscale x 16 x i8> %dup)
1924 ret <vscale x 16 x i8> %out
1925 }
1927 define <vscale x 8 x i16> @uqshl_n_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
1928 ; CHECK-LABEL: uqshl_n_i16:
1929 ; CHECK: uqshl z0.h, p0/m, z0.h, #15
1930 ; CHECK-NEXT: ret
1931 %dup = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 15)
1932 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshl.nxv8i16(<vscale x 8 x i1> %pg,
1933 <vscale x 8 x i16> %a,
1934 <vscale x 8 x i16> %dup)
1935 ret <vscale x 8 x i16> %out
1936 }
1938 define <vscale x 4 x i32> @uqshl_n_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
1939 ; CHECK-LABEL: uqshl_n_i32:
1940 ; CHECK: uqshl z0.s, p0/m, z0.s, #31
1941 ; CHECK-NEXT: ret
1942 %dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 31)
1943 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1> %pg,
1944 <vscale x 4 x i32> %a,
1945 <vscale x 4 x i32> %dup)
1946 ret <vscale x 4 x i32> %out
1947 }
1949 define <vscale x 2 x i64> @uqshl_n_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
1950 ; CHECK-LABEL: uqshl_n_i64:
1951 ; CHECK: uqshl z0.d, p0/m, z0.d, #63
1952 ; CHECK-NEXT: ret
1953 %dup = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 63)
1954 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.nxv2i64(<vscale x 2 x i1> %pg,
1955 <vscale x 2 x i64> %a,
1956 <vscale x 2 x i64> %dup)
1957 ret <vscale x 2 x i64> %out
1958 }
1960 define <vscale x 16 x i8> @uqshl_n_i8_range(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
1961 ; CHECK-LABEL: uqshl_n_i8_range:
1962 ; CHECK: mov z1.b, #8
1963 ; CHECK: uqshl z0.b, p0/m, z0.b, z1.b
1964 ; CHECK-NEXT: ret
1965 %dup = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 8)
1966 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshl.nxv16i8(<vscale x 16 x i1> %pg,
1967 <vscale x 16 x i8> %a,
1968 <vscale x 16 x i8> %dup)
1969 ret <vscale x 16 x i8> %out
1970 }
1972 define <vscale x 8 x i16> @uqshl_n_i16_range(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
1973 ; CHECK-LABEL: uqshl_n_i16_range:
1974 ; CHECK: mov z1.h, #16
1975 ; CHECK: uqshl z0.h, p0/m, z0.h, z1.h
1976 ; CHECK-NEXT: ret
1977 %dup = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 16)
1978 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshl.nxv8i16(<vscale x 8 x i1> %pg,
1979 <vscale x 8 x i16> %a,
1980 <vscale x 8 x i16> %dup)
1981 ret <vscale x 8 x i16> %out
1982 }
1984 define <vscale x 4 x i32> @uqshl_n_i32_range(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
1985 ; CHECK-LABEL: uqshl_n_i32_range:
1986 ; CHECK: mov z1.s, #32
1987 ; CHECK: uqshl z0.s, p0/m, z0.s, z1.s
1988 ; CHECK-NEXT: ret
1989 %dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 32)
1990 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1> %pg,
1991 <vscale x 4 x i32> %a,
1992 <vscale x 4 x i32> %dup)
1993 ret <vscale x 4 x i32> %out
1994 }
1996 define <vscale x 2 x i64> @uqshl_n_i64_range(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
1997 ; CHECK-LABEL: uqshl_n_i64_range:
1998 ; CHECK: mov z1.d, #64
1999 ; CHECK: uqshl z0.d, p0/m, z0.d, z1.d
2000 ; CHECK-NEXT: ret
2001 %dup = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 64)
2002 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.nxv2i64(<vscale x 2 x i1> %pg,
2003 <vscale x 2 x i64> %a,
2004 <vscale x 2 x i64> %dup)
2005 ret <vscale x 2 x i64> %out
2006 }
2008 ;
2009 ; UQSUB
2010 ;
2012 define <vscale x 16 x i8> @uqsub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2013 ; CHECK-LABEL: uqsub_i8:
2014 ; CHECK: uqsub z0.b, p0/m, z0.b, z1.b
2015 ; CHECK-NEXT: ret
2016 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1> %pg,
2017 <vscale x 16 x i8> %a,
2018 <vscale x 16 x i8> %b)
2019 ret <vscale x 16 x i8> %out
2020 }
2022 define <vscale x 8 x i16> @uqsub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2023 ; CHECK-LABEL: uqsub_i16:
2024 ; CHECK: uqsub z0.h, p0/m, z0.h, z1.h
2025 ; CHECK-NEXT: ret
2026 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1> %pg,
2027 <vscale x 8 x i16> %a,
2028 <vscale x 8 x i16> %b)
2029 ret <vscale x 8 x i16> %out
2030 }
2032 define <vscale x 4 x i32> @uqsub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2033 ; CHECK-LABEL: uqsub_i32:
2034 ; CHECK: uqsub z0.s, p0/m, z0.s, z1.s
2035 ; CHECK-NEXT: ret
2036 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> %pg,
2037 <vscale x 4 x i32> %a,
2038 <vscale x 4 x i32> %b)
2039 ret <vscale x 4 x i32> %out
2040 }
2042 define <vscale x 2 x i64> @uqsub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2043 ; CHECK-LABEL: uqsub_i64:
2044 ; CHECK: uqsub z0.d, p0/m, z0.d, z1.d
2045 ; CHECK-NEXT: ret
2046 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1> %pg,
2047 <vscale x 2 x i64> %a,
2048 <vscale x 2 x i64> %b)
2049 ret <vscale x 2 x i64> %out
2050 }
2052 ;
2053 ; UQSUBR
2054 ;
2056 define <vscale x 16 x i8> @uqsubr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2057 ; CHECK-LABEL: uqsubr_i8:
2058 ; CHECK: uqsubr z0.b, p0/m, z0.b, z1.b
2059 ; CHECK-NEXT: ret
2060 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1> %pg,
2061 <vscale x 16 x i8> %a,
2062 <vscale x 16 x i8> %b)
2063 ret <vscale x 16 x i8> %out
2064 }
2066 define <vscale x 8 x i16> @uqsubr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2067 ; CHECK-LABEL: uqsubr_i16:
2068 ; CHECK: uqsubr z0.h, p0/m, z0.h, z1.h
2069 ; CHECK-NEXT: ret
2070 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1> %pg,
2071 <vscale x 8 x i16> %a,
2072 <vscale x 8 x i16> %b)
2073 ret <vscale x 8 x i16> %out
2074 }
2076 define <vscale x 4 x i32> @uqsubr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2077 ; CHECK-LABEL: uqsubr_i32:
2078 ; CHECK: uqsubr z0.s, p0/m, z0.s, z1.s
2079 ; CHECK-NEXT: ret
2080 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> %pg,
2081 <vscale x 4 x i32> %a,
2082 <vscale x 4 x i32> %b)
2083 ret <vscale x 4 x i32> %out
2084 }
2086 define <vscale x 2 x i64> @uqsubr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2087 ; CHECK-LABEL: uqsubr_i64:
2088 ; CHECK: uqsubr z0.d, p0/m, z0.d, z1.d
2089 ; CHECK-NEXT: ret
2090 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1> %pg,
2091 <vscale x 2 x i64> %a,
2092 <vscale x 2 x i64> %b)
2093 ret <vscale x 2 x i64> %out
2094 }
2096 ;
2097 ; URECPE
2098 ;
2100 define <vscale x 4 x i32> @urecpe_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
2101 ; CHECK-LABEL: urecpe_i32:
2102 ; CHECK: urecpe z0.s, p0/m, z1.s
2103 ; CHECK-NEXT: ret
2104 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> %a,
2105 <vscale x 4 x i1> %pg,
2106 <vscale x 4 x i32> %b)
2107 ret <vscale x 4 x i32> %out
2108 }
2110 ;
2111 ; URHADD
2112 ;
2114 define <vscale x 16 x i8> @urhadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2115 ; CHECK-LABEL: urhadd_i8:
2116 ; CHECK: urhadd z0.b, p0/m, z0.b, z1.b
2117 ; CHECK-NEXT: ret
2118 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1> %pg,
2119 <vscale x 16 x i8> %a,
2120 <vscale x 16 x i8> %b)
2121 ret <vscale x 16 x i8> %out
2122 }
2124 define <vscale x 8 x i16> @urhadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2125 ; CHECK-LABEL: urhadd_i16:
2126 ; CHECK: urhadd z0.h, p0/m, z0.h, z1.h
2127 ; CHECK-NEXT: ret
2128 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1> %pg,
2129 <vscale x 8 x i16> %a,
2130 <vscale x 8 x i16> %b)
2131 ret <vscale x 8 x i16> %out
2132 }
2134 define <vscale x 4 x i32> @urhadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2135 ; CHECK-LABEL: urhadd_i32:
2136 ; CHECK: urhadd z0.s, p0/m, z0.s, z1.s
2137 ; CHECK-NEXT: ret
2138 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> %pg,
2139 <vscale x 4 x i32> %a,
2140 <vscale x 4 x i32> %b)
2141 ret <vscale x 4 x i32> %out
2142 }
2144 define <vscale x 2 x i64> @urhadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2145 ; CHECK-LABEL: urhadd_i64:
2146 ; CHECK: urhadd z0.d, p0/m, z0.d, z1.d
2147 ; CHECK-NEXT: ret
2148 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1> %pg,
2149 <vscale x 2 x i64> %a,
2150 <vscale x 2 x i64> %b)
2151 ret <vscale x 2 x i64> %out
2152 }
2154 ;
2155 ; URSHL
2156 ;
2158 define <vscale x 16 x i8> @urshl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2159 ; CHECK-LABEL: urshl_i8:
2160 ; CHECK: urshl z0.b, p0/m, z0.b, z1.b
2161 ; CHECK-NEXT: ret
2162 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.urshl.nxv16i8(<vscale x 16 x i1> %pg,
2163 <vscale x 16 x i8> %a,
2164 <vscale x 16 x i8> %b)
2165 ret <vscale x 16 x i8> %out
2166 }
2168 define <vscale x 8 x i16> @urshl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2169 ; CHECK-LABEL: urshl_i16:
2170 ; CHECK: urshl z0.h, p0/m, z0.h, z1.h
2171 ; CHECK-NEXT: ret
2172 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.urshl.nxv8i16(<vscale x 8 x i1> %pg,
2173 <vscale x 8 x i16> %a,
2174 <vscale x 8 x i16> %b)
2175 ret <vscale x 8 x i16> %out
2176 }
2178 define <vscale x 4 x i32> @urshl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2179 ; CHECK-LABEL: urshl_i32:
2180 ; CHECK: urshl z0.s, p0/m, z0.s, z1.s
2181 ; CHECK-NEXT: ret
2182 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.urshl.nxv4i32(<vscale x 4 x i1> %pg,
2183 <vscale x 4 x i32> %a,
2184 <vscale x 4 x i32> %b)
2185 ret <vscale x 4 x i32> %out
2186 }
2188 define <vscale x 2 x i64> @urshl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2189 ; CHECK-LABEL: urshl_i64:
2190 ; CHECK: urshl z0.d, p0/m, z0.d, z1.d
2191 ; CHECK-NEXT: ret
2192 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.urshl.nxv2i64(<vscale x 2 x i1> %pg,
2193 <vscale x 2 x i64> %a,
2194 <vscale x 2 x i64> %b)
2195 ret <vscale x 2 x i64> %out
2196 }
2198 ;
2199 ; URSHLR
2200 ;
2202 define <vscale x 16 x i8> @urshlr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2203 ; CHECK-LABEL: urshlr_i8:
2204 ; CHECK: ptrue p0.b
2205 ; CHECK-NEXT: urshlr z0.b, p0/m, z0.b, z1.b
2206 ; CHECK-NEXT: ret
2207 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
2208 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.urshl.nxv16i8(<vscale x 16 x i1> %pg,
2209 <vscale x 16 x i8> %b,
2210 <vscale x 16 x i8> %a)
2211 ret <vscale x 16 x i8> %out
2212 }
2214 define <vscale x 8 x i16> @urshlr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2215 ; CHECK-LABEL: urshlr_i16:
2216 ; CHECK: ptrue p0.h
2217 ; CHECK-NEXT: urshlr z0.h, p0/m, z0.h, z1.h
2218 ; CHECK-NEXT: ret
2219 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
2220 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.urshl.nxv8i16(<vscale x 8 x i1> %pg,
2221 <vscale x 8 x i16> %b,
2222 <vscale x 8 x i16> %a)
2223 ret <vscale x 8 x i16> %out
2224 }
2226 define <vscale x 4 x i32> @urshlr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2227 ; CHECK-LABEL: urshlr_i32:
2228 ; CHECK: ptrue p0.s
2229 ; CHECK-NEXT: urshlr z0.s, p0/m, z0.s, z1.s
2230 ; CHECK-NEXT: ret
2231 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
2232 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.urshl.nxv4i32(<vscale x 4 x i1> %pg,
2233 <vscale x 4 x i32> %b,
2234 <vscale x 4 x i32> %a)
2235 ret <vscale x 4 x i32> %out
2236 }
2238 define <vscale x 2 x i64> @urshlr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2239 ; CHECK-LABEL: urshlr_i64:
2240 ; CHECK: ptrue p0.d
2241 ; CHECK-NEXT: urshlr z0.d, p0/m, z0.d, z1.d
2242 ; CHECK-NEXT: ret
2243 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
2244 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.urshl.nxv2i64(<vscale x 2 x i1> %pg,
2245 <vscale x 2 x i64> %b,
2246 <vscale x 2 x i64> %a)
2247 ret <vscale x 2 x i64> %out
2248 }
2250 define <vscale x 2 x i64> @urshlr_i64_noptrue(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2251 ; CHECK-LABEL: urshlr_i64_noptrue:
2252 ; CHECK: urshl z1.d, p0/m, z1.d, z0.d
2253 ; CHECK-NEXT: mov z0.d, z1.d
2254 ; CHECK-NEXT: ret
2255 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.urshl.nxv2i64(<vscale x 2 x i1> %pg,
2256 <vscale x 2 x i64> %b,
2257 <vscale x 2 x i64> %a)
2258 ret <vscale x 2 x i64> %out
2259 }
2261 ;
2262 ; URSHR
2263 ;
2265 define <vscale x 16 x i8> @urshr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
2266 ; CHECK-LABEL: urshr_i8:
2267 ; CHECK: urshr z0.b, p0/m, z0.b, #4
2268 ; CHECK-NEXT: ret
2269 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.urshr.nxv16i8(<vscale x 16 x i1> %pg,
2270 <vscale x 16 x i8> %a,
2271 i32 4)
2272 ret <vscale x 16 x i8> %out
2273 }
2275 define <vscale x 8 x i16> @urshr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
2276 ; CHECK-LABEL: urshr_i16:
2277 ; CHECK: urshr z0.h, p0/m, z0.h, #13
2278 ; CHECK-NEXT: ret
2279 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.urshr.nxv8i16(<vscale x 8 x i1> %pg,
2280 <vscale x 8 x i16> %a,
2281 i32 13)
2282 ret <vscale x 8 x i16> %out
2283 }
2285 define <vscale x 4 x i32> @urshr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
2286 ; CHECK-LABEL: urshr_i32:
2287 ; CHECK: urshr z0.s, p0/m, z0.s, #1
2288 ; CHECK-NEXT: ret
2289 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.urshr.nxv4i32(<vscale x 4 x i1> %pg,
2290 <vscale x 4 x i32> %a,
2291 i32 1)
2292 ret <vscale x 4 x i32> %out
2293 }
2295 define <vscale x 2 x i64> @urshr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
2296 ; CHECK-LABEL: urshr_i64:
2297 ; CHECK: urshr z0.d, p0/m, z0.d, #24
2298 ; CHECK-NEXT: ret
2299 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.urshr.nxv2i64(<vscale x 2 x i1> %pg,
2300 <vscale x 2 x i64> %a,
2301 i32 24)
2302 ret <vscale x 2 x i64> %out
2303 }
2305 ;
2306 ; URSQRTE
2307 ;
2309 define <vscale x 4 x i32> @ursqrte_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
2310 ; CHECK-LABEL: ursqrte_i32:
2311 ; CHECK: ursqrte z0.s, p0/m, z1.s
2312 ; CHECK-NEXT: ret
2313 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32> %a,
2314 <vscale x 4 x i1> %pg,
2315 <vscale x 4 x i32> %b)
2316 ret <vscale x 4 x i32> %out
2317 }
2319 ;
2320 ; URSRA
2321 ;
2323 define <vscale x 16 x i8> @ursra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2324 ; CHECK-LABEL: ursra_i8:
2325 ; CHECK: ursra z0.b, z1.b, #5
2326 ; CHECK-NEXT: ret
2327 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.ursra.nxv16i8(<vscale x 16 x i8> %a,
2328 <vscale x 16 x i8> %b,
2329 i32 5)
2330 ret <vscale x 16 x i8> %out
2331 }
2333 define <vscale x 8 x i16> @ursra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2334 ; CHECK-LABEL: ursra_i16:
2335 ; CHECK: ursra z0.h, z1.h, #12
2336 ; CHECK-NEXT: ret
2337 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ursra.nxv8i16(<vscale x 8 x i16> %a,
2338 <vscale x 8 x i16> %b,
2339 i32 12)
2340 ret <vscale x 8 x i16> %out
2341 }
2343 define <vscale x 4 x i32> @ursra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2344 ; CHECK-LABEL: ursra_i32:
2345 ; CHECK: ursra z0.s, z1.s, #31
2346 ; CHECK-NEXT: ret
2347 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ursra.nxv4i32(<vscale x 4 x i32> %a,
2348 <vscale x 4 x i32> %b,
2349 i32 31)
2350 ret <vscale x 4 x i32> %out
2351 }
2353 define <vscale x 2 x i64> @ursra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2354 ; CHECK-LABEL: ursra_i64:
2355 ; CHECK: ursra z0.d, z1.d, #14
2356 ; CHECK-NEXT: ret
2357 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ursra.nxv2i64(<vscale x 2 x i64> %a,
2358 <vscale x 2 x i64> %b,
2359 i32 14)
2360 ret <vscale x 2 x i64> %out
2361 }
2363 ;
2364 ; USQADD
2365 ;
2367 define <vscale x 16 x i8> @usqadd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2368 ; CHECK-LABEL: usqadd_i8:
2369 ; CHECK: usqadd z0.b, p0/m, z0.b, z1.b
2370 ; CHECK-NEXT: ret
2371 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.usqadd.nxv16i8(<vscale x 16 x i1> %pg,
2372 <vscale x 16 x i8> %a,
2373 <vscale x 16 x i8> %b)
2374 ret <vscale x 16 x i8> %out
2375 }
2377 define <vscale x 8 x i16> @usqadd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2378 ; CHECK-LABEL: usqadd_i16:
2379 ; CHECK: usqadd z0.h, p0/m, z0.h, z1.h
2380 ; CHECK-NEXT: ret
2381 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.usqadd.nxv8i16(<vscale x 8 x i1> %pg,
2382 <vscale x 8 x i16> %a,
2383 <vscale x 8 x i16> %b)
2384 ret <vscale x 8 x i16> %out
2385 }
2387 define <vscale x 4 x i32> @usqadd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2388 ; CHECK-LABEL: usqadd_i32:
2389 ; CHECK: usqadd z0.s, p0/m, z0.s, z1.s
2390 ; CHECK-NEXT: ret
2391 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.usqadd.nxv4i32(<vscale x 4 x i1> %pg,
2392 <vscale x 4 x i32> %a,
2393 <vscale x 4 x i32> %b)
2394 ret <vscale x 4 x i32> %out
2395 }
2397 define <vscale x 2 x i64> @usqadd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2398 ; CHECK-LABEL: usqadd_i64:
2399 ; CHECK: usqadd z0.d, p0/m, z0.d, z1.d
2400 ; CHECK-NEXT: ret
2401 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.usqadd.nxv2i64(<vscale x 2 x i1> %pg,
2402 <vscale x 2 x i64> %a,
2403 <vscale x 2 x i64> %b)
2404 ret <vscale x 2 x i64> %out
2405 }
2407 ;
2408 ; USRA
2409 ;
2411 define <vscale x 16 x i8> @usra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
2412 ; CHECK-LABEL: usra_i8:
2413 ; CHECK: usra z0.b, z1.b, #6
2414 ; CHECK-NEXT: ret
2415 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.usra.nxv16i8(<vscale x 16 x i8> %a,
2416 <vscale x 16 x i8> %b,
2417 i32 6)
2418 ret <vscale x 16 x i8> %out
2419 }
2421 define <vscale x 8 x i16> @usra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
2422 ; CHECK-LABEL: usra_i16:
2423 ; CHECK: usra z0.h, z1.h, #11
2424 ; CHECK-NEXT: ret
2425 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.usra.nxv8i16(<vscale x 8 x i16> %a,
2426 <vscale x 8 x i16> %b,
2427 i32 11)
2428 ret <vscale x 8 x i16> %out
2429 }
2431 define <vscale x 4 x i32> @usra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
2432 ; CHECK-LABEL: usra_i32:
2433 ; CHECK: usra z0.s, z1.s, #21
2434 ; CHECK-NEXT: ret
2435 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.usra.nxv4i32(<vscale x 4 x i32> %a,
2436 <vscale x 4 x i32> %b,
2437 i32 21)
2438 ret <vscale x 4 x i32> %out
2439 }
2441 define <vscale x 2 x i64> @usra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
2442 ; CHECK-LABEL: usra_i64:
2443 ; CHECK: usra z0.d, z1.d, #4
2444 ; CHECK-NEXT: ret
2445 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.usra.nxv2i64(<vscale x 2 x i64> %a,
2446 <vscale x 2 x i64> %b,
2447 i32 4)
2448 ret <vscale x 2 x i64> %out
2449 }
2451 declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8)
2452 declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16)
2453 declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32)
2454 declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64)
2456 declare <vscale x 16 x i8> @llvm.aarch64.sve.saba.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2457 declare <vscale x 8 x i16> @llvm.aarch64.sve.saba.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2458 declare <vscale x 4 x i32> @llvm.aarch64.sve.saba.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2459 declare <vscale x 2 x i64> @llvm.aarch64.sve.saba.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2461 declare <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2462 declare <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2463 declare <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2464 declare <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2466 declare <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2467 declare <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2468 declare <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2469 declare <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2471 declare <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2472 declare <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2473 declare <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2474 declare <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2476 declare <vscale x 16 x i8> @llvm.aarch64.sve.sli.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
2477 declare <vscale x 8 x i16> @llvm.aarch64.sve.sli.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2478 declare <vscale x 4 x i32> @llvm.aarch64.sve.sli.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2479 declare <vscale x 2 x i64> @llvm.aarch64.sve.sli.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2481 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqabs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
2482 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqabs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
2483 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
2484 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqabs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
2486 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2487 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2488 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2489 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2491 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqdmulh.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
2492 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmulh.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
2493 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmulh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
2494 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmulh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
2496 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmulh.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2497 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmulh.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2498 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmulh.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2500 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqneg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
2501 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqneg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
2502 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
2503 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqneg.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
2505 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlah.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2506 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2507 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2508 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2510 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlah.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2511 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlah.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2512 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlah.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2514 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmlsh.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2515 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlsh.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2516 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlsh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2517 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlsh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2519 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmlsh.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2520 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmlsh.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2521 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmlsh.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2523 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrdmulh.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
2524 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmulh.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
2525 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmulh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
2526 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmulh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
2528 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrdmulh.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2529 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrdmulh.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2530 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrdmulh.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2532 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2533 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2534 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2535 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqrshl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2537 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2538 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2539 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2540 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqshl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2542 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
2543 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
2544 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
2545 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
2547 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2548 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2549 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2550 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2552 declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2553 declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2554 declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2555 declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2557 declare <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2558 declare <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2559 declare <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2560 declare <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2562 declare <vscale x 16 x i8> @llvm.aarch64.sve.sri.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
2563 declare <vscale x 8 x i16> @llvm.aarch64.sve.sri.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2564 declare <vscale x 4 x i32> @llvm.aarch64.sve.sri.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2565 declare <vscale x 2 x i64> @llvm.aarch64.sve.sri.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2567 declare <vscale x 16 x i8> @llvm.aarch64.sve.srshl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2568 declare <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2569 declare <vscale x 4 x i32> @llvm.aarch64.sve.srshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2570 declare <vscale x 2 x i64> @llvm.aarch64.sve.srshl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2572 declare <vscale x 16 x i8> @llvm.aarch64.sve.srshr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
2573 declare <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
2574 declare <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
2575 declare <vscale x 2 x i64> @llvm.aarch64.sve.srshr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
2577 declare <vscale x 16 x i8> @llvm.aarch64.sve.srsra.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
2578 declare <vscale x 8 x i16> @llvm.aarch64.sve.srsra.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2579 declare <vscale x 4 x i32> @llvm.aarch64.sve.srsra.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2580 declare <vscale x 2 x i64> @llvm.aarch64.sve.srsra.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2582 declare <vscale x 16 x i8> @llvm.aarch64.sve.ssra.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
2583 declare <vscale x 8 x i16> @llvm.aarch64.sve.ssra.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2584 declare <vscale x 4 x i32> @llvm.aarch64.sve.ssra.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2585 declare <vscale x 2 x i64> @llvm.aarch64.sve.ssra.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2587 declare <vscale x 16 x i8> @llvm.aarch64.sve.suqadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2588 declare <vscale x 8 x i16> @llvm.aarch64.sve.suqadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2589 declare <vscale x 4 x i32> @llvm.aarch64.sve.suqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2590 declare <vscale x 2 x i64> @llvm.aarch64.sve.suqadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2592 declare <vscale x 16 x i8> @llvm.aarch64.sve.uaba.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2593 declare <vscale x 8 x i16> @llvm.aarch64.sve.uaba.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2594 declare <vscale x 4 x i32> @llvm.aarch64.sve.uaba.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2595 declare <vscale x 2 x i64> @llvm.aarch64.sve.uaba.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2597 declare <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2598 declare <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2599 declare <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2600 declare <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2602 declare <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2603 declare <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2604 declare <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2605 declare <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2607 declare <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2608 declare <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2609 declare <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2610 declare <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2612 declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2613 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2614 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2615 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2617 declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2618 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2619 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2620 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqrshl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2622 declare <vscale x 16 x i8> @llvm.aarch64.sve.uqshl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2623 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqshl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2624 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2625 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqshl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2627 declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2628 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2629 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2630 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2632 declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2633 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2634 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2635 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2637 declare <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
2639 declare <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2640 declare <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2641 declare <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2642 declare <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2644 declare <vscale x 16 x i8> @llvm.aarch64.sve.urshl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2645 declare <vscale x 8 x i16> @llvm.aarch64.sve.urshl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2646 declare <vscale x 4 x i32> @llvm.aarch64.sve.urshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2647 declare <vscale x 2 x i64> @llvm.aarch64.sve.urshl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2649 declare <vscale x 16 x i8> @llvm.aarch64.sve.urshr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
2650 declare <vscale x 8 x i16> @llvm.aarch64.sve.urshr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
2651 declare <vscale x 4 x i32> @llvm.aarch64.sve.urshr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
2652 declare <vscale x 2 x i64> @llvm.aarch64.sve.urshr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
2654 declare <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
2656 declare <vscale x 16 x i8> @llvm.aarch64.sve.ursra.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
2657 declare <vscale x 8 x i16> @llvm.aarch64.sve.ursra.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2658 declare <vscale x 4 x i32> @llvm.aarch64.sve.ursra.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2659 declare <vscale x 2 x i64> @llvm.aarch64.sve.ursra.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2661 declare <vscale x 16 x i8> @llvm.aarch64.sve.usqadd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
2662 declare <vscale x 8 x i16> @llvm.aarch64.sve.usqadd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
2663 declare <vscale x 4 x i32> @llvm.aarch64.sve.usqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
2664 declare <vscale x 2 x i64> @llvm.aarch64.sve.usqadd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
2666 declare <vscale x 16 x i8> @llvm.aarch64.sve.usra.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
2667 declare <vscale x 8 x i16> @llvm.aarch64.sve.usra.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
2668 declare <vscale x 4 x i32> @llvm.aarch64.sve.usra.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
2669 declare <vscale x 2 x i64> @llvm.aarch64.sve.usra.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
2671 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
2672 declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
2673 declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
2674 declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)