| blob | b4b08e60e06d1a5a42aa6fcacdc39164d02b6751 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.uadd.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128>, <2 x i128>)
35 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
36 ; CHECK-LABEL: v16i8:
37 ; CHECK: // %bb.0:
38 ; CHECK-NEXT: uqadd v0.16b, v0.16b, v1.16b
39 ; CHECK-NEXT: ret
40 %z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
41 ret <16 x i8> %z
42 }
44 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
45 ; CHECK-LABEL: v32i8:
46 ; CHECK: // %bb.0:
47 ; CHECK-NEXT: uqadd v0.16b, v0.16b, v2.16b
48 ; CHECK-NEXT: uqadd v1.16b, v1.16b, v3.16b
49 ; CHECK-NEXT: ret
50 %z = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
51 ret <32 x i8> %z
52 }
54 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
55 ; CHECK-LABEL: v64i8:
56 ; CHECK: // %bb.0:
57 ; CHECK-NEXT: uqadd v0.16b, v0.16b, v4.16b
58 ; CHECK-NEXT: uqadd v1.16b, v1.16b, v5.16b
59 ; CHECK-NEXT: uqadd v2.16b, v2.16b, v6.16b
60 ; CHECK-NEXT: uqadd v3.16b, v3.16b, v7.16b
61 ; CHECK-NEXT: ret
62 %z = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
63 ret <64 x i8> %z
64 }
66 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
67 ; CHECK-LABEL: v8i16:
68 ; CHECK: // %bb.0:
69 ; CHECK-NEXT: uqadd v0.8h, v0.8h, v1.8h
70 ; CHECK-NEXT: ret
71 %z = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
72 ret <8 x i16> %z
73 }
75 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
76 ; CHECK-LABEL: v16i16:
77 ; CHECK: // %bb.0:
78 ; CHECK-NEXT: uqadd v0.8h, v0.8h, v2.8h
79 ; CHECK-NEXT: uqadd v1.8h, v1.8h, v3.8h
80 ; CHECK-NEXT: ret
81 %z = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
82 ret <16 x i16> %z
83 }
85 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
86 ; CHECK-LABEL: v32i16:
87 ; CHECK: // %bb.0:
88 ; CHECK-NEXT: uqadd v0.8h, v0.8h, v4.8h
89 ; CHECK-NEXT: uqadd v1.8h, v1.8h, v5.8h
90 ; CHECK-NEXT: uqadd v2.8h, v2.8h, v6.8h
91 ; CHECK-NEXT: uqadd v3.8h, v3.8h, v7.8h
92 ; CHECK-NEXT: ret
93 %z = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
94 ret <32 x i16> %z
95 }
97 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
98 ; CHECK-LABEL: v8i8:
99 ; CHECK: // %bb.0:
100 ; CHECK-NEXT: ldr d0, [x0]
101 ; CHECK-NEXT: ldr d1, [x1]
102 ; CHECK-NEXT: uqadd v0.8b, v0.8b, v1.8b
103 ; CHECK-NEXT: str d0, [x2]
104 ; CHECK-NEXT: ret
105 %x = load <8 x i8>, <8 x i8>* %px
106 %y = load <8 x i8>, <8 x i8>* %py
107 %z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
108 store <8 x i8> %z, <8 x i8>* %pz
109 ret void
110 }
112 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
113 ; CHECK-LABEL: v4i8:
114 ; CHECK: // %bb.0:
115 ; CHECK-NEXT: ldr s0, [x0]
116 ; CHECK-NEXT: ldr s1, [x1]
117 ; CHECK-NEXT: movi d2, #0xff00ff00ff00ff
118 ; CHECK-NEXT: ushll v0.8h, v0.8b, #0
119 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0
120 ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
121 ; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h
122 ; CHECK-NEXT: xtn v0.8b, v0.8h
123 ; CHECK-NEXT: str s0, [x2]
124 ; CHECK-NEXT: ret
125 %x = load <4 x i8>, <4 x i8>* %px
126 %y = load <4 x i8>, <4 x i8>* %py
127 %z = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
128 store <4 x i8> %z, <4 x i8>* %pz
129 ret void
130 }
132 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
133 ; CHECK-LABEL: v2i8:
134 ; CHECK: // %bb.0:
135 ; CHECK-NEXT: ldrb w8, [x0]
136 ; CHECK-NEXT: ldrb w9, [x1]
137 ; CHECK-NEXT: ldrb w10, [x0, #1]
138 ; CHECK-NEXT: ldrb w11, [x1, #1]
139 ; CHECK-NEXT: fmov s0, w8
140 ; CHECK-NEXT: fmov s2, w9
141 ; CHECK-NEXT: mov v0.s[1], w10
142 ; CHECK-NEXT: mov v2.s[1], w11
143 ; CHECK-NEXT: movi d1, #0x0000ff000000ff
144 ; CHECK-NEXT: add v0.2s, v0.2s, v2.2s
145 ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
146 ; CHECK-NEXT: mov w8, v0.s[1]
147 ; CHECK-NEXT: fmov w9, s0
148 ; CHECK-NEXT: strb w9, [x2]
149 ; CHECK-NEXT: strb w8, [x2, #1]
150 ; CHECK-NEXT: ret
151 %x = load <2 x i8>, <2 x i8>* %px
152 %y = load <2 x i8>, <2 x i8>* %py
153 %z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
154 store <2 x i8> %z, <2 x i8>* %pz
155 ret void
156 }
158 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
159 ; CHECK-LABEL: v4i16:
160 ; CHECK: // %bb.0:
161 ; CHECK-NEXT: ldr d0, [x0]
162 ; CHECK-NEXT: ldr d1, [x1]
163 ; CHECK-NEXT: uqadd v0.4h, v0.4h, v1.4h
164 ; CHECK-NEXT: str d0, [x2]
165 ; CHECK-NEXT: ret
166 %x = load <4 x i16>, <4 x i16>* %px
167 %y = load <4 x i16>, <4 x i16>* %py
168 %z = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
169 store <4 x i16> %z, <4 x i16>* %pz
170 ret void
171 }
173 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
174 ; CHECK-LABEL: v2i16:
175 ; CHECK: // %bb.0:
176 ; CHECK-NEXT: ldrh w8, [x0]
177 ; CHECK-NEXT: ldrh w9, [x1]
178 ; CHECK-NEXT: ldrh w10, [x0, #2]
179 ; CHECK-NEXT: ldrh w11, [x1, #2]
180 ; CHECK-NEXT: fmov s0, w8
181 ; CHECK-NEXT: fmov s2, w9
182 ; CHECK-NEXT: mov v0.s[1], w10
183 ; CHECK-NEXT: mov v2.s[1], w11
184 ; CHECK-NEXT: movi d1, #0x00ffff0000ffff
185 ; CHECK-NEXT: add v0.2s, v0.2s, v2.2s
186 ; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
187 ; CHECK-NEXT: mov w8, v0.s[1]
188 ; CHECK-NEXT: fmov w9, s0
189 ; CHECK-NEXT: strh w9, [x2]
190 ; CHECK-NEXT: strh w8, [x2, #2]
191 ; CHECK-NEXT: ret
192 %x = load <2 x i16>, <2 x i16>* %px
193 %y = load <2 x i16>, <2 x i16>* %py
194 %z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
195 store <2 x i16> %z, <2 x i16>* %pz
196 ret void
197 }
199 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
200 ; CHECK-LABEL: v12i8:
201 ; CHECK: // %bb.0:
202 ; CHECK-NEXT: uqadd v0.16b, v0.16b, v1.16b
203 ; CHECK-NEXT: ret
204 %z = call <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
205 ret <12 x i8> %z
206 }
208 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
209 ; CHECK-LABEL: v12i16:
210 ; CHECK: // %bb.0:
211 ; CHECK-NEXT: ldp q0, q1, [x0]
212 ; CHECK-NEXT: ldp q3, q2, [x1]
213 ; CHECK-NEXT: uqadd v1.8h, v1.8h, v2.8h
214 ; CHECK-NEXT: uqadd v0.8h, v0.8h, v3.8h
215 ; CHECK-NEXT: str q0, [x2]
216 ; CHECK-NEXT: str d1, [x2, #16]
217 ; CHECK-NEXT: ret
218 %x = load <12 x i16>, <12 x i16>* %px
219 %y = load <12 x i16>, <12 x i16>* %py
220 %z = call <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
221 store <12 x i16> %z, <12 x i16>* %pz
222 ret void
223 }
225 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
226 ; CHECK-LABEL: v1i8:
227 ; CHECK: // %bb.0:
228 ; CHECK-NEXT: ldr b0, [x0]
229 ; CHECK-NEXT: ldr b1, [x1]
230 ; CHECK-NEXT: uqadd v0.8b, v0.8b, v1.8b
231 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
232 ; CHECK-NEXT: ret
233 %x = load <1 x i8>, <1 x i8>* %px
234 %y = load <1 x i8>, <1 x i8>* %py
235 %z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
236 store <1 x i8> %z, <1 x i8>* %pz
237 ret void
238 }
240 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
241 ; CHECK-LABEL: v1i16:
242 ; CHECK: // %bb.0:
243 ; CHECK-NEXT: ldr h0, [x0]
244 ; CHECK-NEXT: ldr h1, [x1]
245 ; CHECK-NEXT: uqadd v0.4h, v0.4h, v1.4h
246 ; CHECK-NEXT: str h0, [x2]
247 ; CHECK-NEXT: ret
248 %x = load <1 x i16>, <1 x i16>* %px
249 %y = load <1 x i16>, <1 x i16>* %py
250 %z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
251 store <1 x i16> %z, <1 x i16>* %pz
252 ret void
253 }
255 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
256 ; CHECK-LABEL: v16i4:
257 ; CHECK: // %bb.0:
258 ; CHECK-NEXT: movi v2.16b, #15
259 ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
260 ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
261 ; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
262 ; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
263 ; CHECK-NEXT: ret
264 %z = call <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
265 ret <16 x i4> %z
266 }
268 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
269 ; CHECK-LABEL: v16i1:
270 ; CHECK: // %bb.0:
271 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
272 ; CHECK-NEXT: ret
273 %z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
274 ret <16 x i1> %z
275 }
277 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
278 ; CHECK-LABEL: v2i32:
279 ; CHECK: // %bb.0:
280 ; CHECK-NEXT: uqadd v0.2s, v0.2s, v1.2s
281 ; CHECK-NEXT: ret
282 %z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
283 ret <2 x i32> %z
284 }
286 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
287 ; CHECK-LABEL: v4i32:
288 ; CHECK: // %bb.0:
289 ; CHECK-NEXT: uqadd v0.4s, v0.4s, v1.4s
290 ; CHECK-NEXT: ret
291 %z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
292 ret <4 x i32> %z
293 }
295 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
296 ; CHECK-LABEL: v8i32:
297 ; CHECK: // %bb.0:
298 ; CHECK-NEXT: uqadd v0.4s, v0.4s, v2.4s
299 ; CHECK-NEXT: uqadd v1.4s, v1.4s, v3.4s
300 ; CHECK-NEXT: ret
301 %z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
302 ret <8 x i32> %z
303 }
305 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
306 ; CHECK-LABEL: v16i32:
307 ; CHECK: // %bb.0:
308 ; CHECK-NEXT: uqadd v0.4s, v0.4s, v4.4s
309 ; CHECK-NEXT: uqadd v1.4s, v1.4s, v5.4s
310 ; CHECK-NEXT: uqadd v2.4s, v2.4s, v6.4s
311 ; CHECK-NEXT: uqadd v3.4s, v3.4s, v7.4s
312 ; CHECK-NEXT: ret
313 %z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
314 ret <16 x i32> %z
315 }
317 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
318 ; CHECK-LABEL: v2i64:
319 ; CHECK: // %bb.0:
320 ; CHECK-NEXT: uqadd v0.2d, v0.2d, v1.2d
321 ; CHECK-NEXT: ret
322 %z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
323 ret <2 x i64> %z
324 }
326 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
327 ; CHECK-LABEL: v4i64:
328 ; CHECK: // %bb.0:
329 ; CHECK-NEXT: uqadd v0.2d, v0.2d, v2.2d
330 ; CHECK-NEXT: uqadd v1.2d, v1.2d, v3.2d
331 ; CHECK-NEXT: ret
332 %z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
333 ret <4 x i64> %z
334 }
336 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
337 ; CHECK-LABEL: v8i64:
338 ; CHECK: // %bb.0:
339 ; CHECK-NEXT: uqadd v0.2d, v0.2d, v4.2d
340 ; CHECK-NEXT: uqadd v1.2d, v1.2d, v5.2d
341 ; CHECK-NEXT: uqadd v2.2d, v2.2d, v6.2d
342 ; CHECK-NEXT: uqadd v3.2d, v3.2d, v7.2d
343 ; CHECK-NEXT: ret
344 %z = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
345 ret <8 x i64> %z
346 }
348 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
349 ; CHECK-LABEL: v2i128:
350 ; CHECK: // %bb.0:
351 ; CHECK-NEXT: adds x8, x2, x6
352 ; CHECK-NEXT: adcs x9, x3, x7
353 ; CHECK-NEXT: cmp x8, x2
354 ; CHECK-NEXT: cset w10, lo
355 ; CHECK-NEXT: cmp x9, x3
356 ; CHECK-NEXT: cset w11, lo
357 ; CHECK-NEXT: csel w10, w10, w11, eq
358 ; CHECK-NEXT: cmp w10, #0
359 ; CHECK-NEXT: csinv x3, x9, xzr, eq
360 ; CHECK-NEXT: csinv x2, x8, xzr, eq
361 ; CHECK-NEXT: adds x8, x0, x4
362 ; CHECK-NEXT: adcs x9, x1, x5
363 ; CHECK-NEXT: cmp x8, x0
364 ; CHECK-NEXT: cset w10, lo
365 ; CHECK-NEXT: cmp x9, x1
366 ; CHECK-NEXT: cset w11, lo
367 ; CHECK-NEXT: csel w10, w10, w11, eq
368 ; CHECK-NEXT: cmp w10, #0
369 ; CHECK-NEXT: csinv x8, x8, xzr, eq
370 ; CHECK-NEXT: csinv x1, x9, xzr, eq
371 ; CHECK-NEXT: fmov d0, x8
372 ; CHECK-NEXT: mov v0.d[1], x1
373 ; CHECK-NEXT: fmov x0, d0
374 ; CHECK-NEXT: ret
375 %z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
376 ret <2 x i128> %z
377 }