| blob | c95bf9eda1c9356c6c0ae104f3a65931e9cdcf37 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-unknown- | FileCheck %s
4 define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) {
5 ; CHECK-LABEL: ugt_1_v16i8:
6 ; CHECK: // %bb.0:
7 ; CHECK-NEXT: cnt v0.16b, v0.16b
8 ; CHECK-NEXT: movi v1.16b, #1
9 ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
10 ; CHECK-NEXT: ret
11 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
12 %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
13 %4 = sext <16 x i1> %3 to <16 x i8>
14 ret <16 x i8> %4
15 }
17 define <16 x i8> @ult_2_v16i8(<16 x i8> %0) {
18 ; CHECK-LABEL: ult_2_v16i8:
19 ; CHECK: // %bb.0:
20 ; CHECK-NEXT: cnt v0.16b, v0.16b
21 ; CHECK-NEXT: movi v1.16b, #2
22 ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
23 ; CHECK-NEXT: ret
24 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
25 %3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
26 %4 = sext <16 x i1> %3 to <16 x i8>
27 ret <16 x i8> %4
28 }
30 define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) {
31 ; CHECK-LABEL: ugt_2_v16i8:
32 ; CHECK: // %bb.0:
33 ; CHECK-NEXT: cnt v0.16b, v0.16b
34 ; CHECK-NEXT: movi v1.16b, #2
35 ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
36 ; CHECK-NEXT: ret
37 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
38 %3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
39 %4 = sext <16 x i1> %3 to <16 x i8>
40 ret <16 x i8> %4
41 }
43 define <16 x i8> @ult_3_v16i8(<16 x i8> %0) {
44 ; CHECK-LABEL: ult_3_v16i8:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: cnt v0.16b, v0.16b
47 ; CHECK-NEXT: movi v1.16b, #3
48 ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
49 ; CHECK-NEXT: ret
50 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
51 %3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
52 %4 = sext <16 x i1> %3 to <16 x i8>
53 ret <16 x i8> %4
54 }
56 define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) {
57 ; CHECK-LABEL: ugt_3_v16i8:
58 ; CHECK: // %bb.0:
59 ; CHECK-NEXT: cnt v0.16b, v0.16b
60 ; CHECK-NEXT: movi v1.16b, #3
61 ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
62 ; CHECK-NEXT: ret
63 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
64 %3 = icmp ugt <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
65 %4 = sext <16 x i1> %3 to <16 x i8>
66 ret <16 x i8> %4
67 }
69 define <16 x i8> @ult_4_v16i8(<16 x i8> %0) {
70 ; CHECK-LABEL: ult_4_v16i8:
71 ; CHECK: // %bb.0:
72 ; CHECK-NEXT: cnt v0.16b, v0.16b
73 ; CHECK-NEXT: movi v1.16b, #4
74 ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
75 ; CHECK-NEXT: ret
76 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
77 %3 = icmp ult <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
78 %4 = sext <16 x i1> %3 to <16 x i8>
79 ret <16 x i8> %4
80 }
82 define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) {
83 ; CHECK-LABEL: ugt_4_v16i8:
84 ; CHECK: // %bb.0:
85 ; CHECK-NEXT: cnt v0.16b, v0.16b
86 ; CHECK-NEXT: movi v1.16b, #4
87 ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
88 ; CHECK-NEXT: ret
89 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
90 %3 = icmp ugt <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
91 %4 = sext <16 x i1> %3 to <16 x i8>
92 ret <16 x i8> %4
93 }
95 define <16 x i8> @ult_5_v16i8(<16 x i8> %0) {
96 ; CHECK-LABEL: ult_5_v16i8:
97 ; CHECK: // %bb.0:
98 ; CHECK-NEXT: cnt v0.16b, v0.16b
99 ; CHECK-NEXT: movi v1.16b, #5
100 ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
101 ; CHECK-NEXT: ret
102 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
103 %3 = icmp ult <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
104 %4 = sext <16 x i1> %3 to <16 x i8>
105 ret <16 x i8> %4
106 }
108 define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) {
109 ; CHECK-LABEL: ugt_5_v16i8:
110 ; CHECK: // %bb.0:
111 ; CHECK-NEXT: cnt v0.16b, v0.16b
112 ; CHECK-NEXT: movi v1.16b, #5
113 ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
114 ; CHECK-NEXT: ret
115 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
116 %3 = icmp ugt <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
117 %4 = sext <16 x i1> %3 to <16 x i8>
118 ret <16 x i8> %4
119 }
121 define <16 x i8> @ult_6_v16i8(<16 x i8> %0) {
122 ; CHECK-LABEL: ult_6_v16i8:
123 ; CHECK: // %bb.0:
124 ; CHECK-NEXT: cnt v0.16b, v0.16b
125 ; CHECK-NEXT: movi v1.16b, #6
126 ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
127 ; CHECK-NEXT: ret
128 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
129 %3 = icmp ult <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
130 %4 = sext <16 x i1> %3 to <16 x i8>
131 ret <16 x i8> %4
132 }
134 define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) {
135 ; CHECK-LABEL: ugt_6_v16i8:
136 ; CHECK: // %bb.0:
137 ; CHECK-NEXT: cnt v0.16b, v0.16b
138 ; CHECK-NEXT: movi v1.16b, #6
139 ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
140 ; CHECK-NEXT: ret
141 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
142 %3 = icmp ugt <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
143 %4 = sext <16 x i1> %3 to <16 x i8>
144 ret <16 x i8> %4
145 }
147 define <16 x i8> @ult_7_v16i8(<16 x i8> %0) {
148 ; CHECK-LABEL: ult_7_v16i8:
149 ; CHECK: // %bb.0:
150 ; CHECK-NEXT: cnt v0.16b, v0.16b
151 ; CHECK-NEXT: movi v1.16b, #7
152 ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
153 ; CHECK-NEXT: ret
154 %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
155 %3 = icmp ult <16 x i8> %2, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
156 %4 = sext <16 x i1> %3 to <16 x i8>
157 ret <16 x i8> %4
158 }
160 define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) {
161 ; CHECK-LABEL: ugt_1_v8i16:
162 ; CHECK: // %bb.0:
163 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
164 ; CHECK-NEXT: add v1.8h, v0.8h, v1.8h
165 ; CHECK-NEXT: cmtst v0.8h, v0.8h, v1.8h
166 ; CHECK-NEXT: ret
167 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
168 %3 = icmp ugt <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
169 %4 = sext <8 x i1> %3 to <8 x i16>
170 ret <8 x i16> %4
171 }
173 define <8 x i16> @ult_2_v8i16(<8 x i16> %0) {
174 ; CHECK-LABEL: ult_2_v8i16:
175 ; CHECK: // %bb.0:
176 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
177 ; CHECK-NEXT: add v1.8h, v0.8h, v1.8h
178 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
179 ; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
180 ; CHECK-NEXT: ret
181 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
182 %3 = icmp ult <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
183 %4 = sext <8 x i1> %3 to <8 x i16>
184 ret <8 x i16> %4
185 }
187 define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) {
188 ; CHECK-LABEL: ugt_2_v8i16:
189 ; CHECK: // %bb.0:
190 ; CHECK-NEXT: cnt v0.16b, v0.16b
191 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
192 ; CHECK-NEXT: movi v1.8h, #2
193 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
194 ; CHECK-NEXT: ret
195 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
196 %3 = icmp ugt <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
197 %4 = sext <8 x i1> %3 to <8 x i16>
198 ret <8 x i16> %4
199 }
201 define <8 x i16> @ult_3_v8i16(<8 x i16> %0) {
202 ; CHECK-LABEL: ult_3_v8i16:
203 ; CHECK: // %bb.0:
204 ; CHECK-NEXT: cnt v0.16b, v0.16b
205 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
206 ; CHECK-NEXT: movi v1.8h, #3
207 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
208 ; CHECK-NEXT: ret
209 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
210 %3 = icmp ult <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
211 %4 = sext <8 x i1> %3 to <8 x i16>
212 ret <8 x i16> %4
213 }
215 define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) {
216 ; CHECK-LABEL: ugt_3_v8i16:
217 ; CHECK: // %bb.0:
218 ; CHECK-NEXT: cnt v0.16b, v0.16b
219 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
220 ; CHECK-NEXT: movi v1.8h, #3
221 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
222 ; CHECK-NEXT: ret
223 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
224 %3 = icmp ugt <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
225 %4 = sext <8 x i1> %3 to <8 x i16>
226 ret <8 x i16> %4
227 }
229 define <8 x i16> @ult_4_v8i16(<8 x i16> %0) {
230 ; CHECK-LABEL: ult_4_v8i16:
231 ; CHECK: // %bb.0:
232 ; CHECK-NEXT: cnt v0.16b, v0.16b
233 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
234 ; CHECK-NEXT: movi v1.8h, #4
235 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
236 ; CHECK-NEXT: ret
237 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
238 %3 = icmp ult <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
239 %4 = sext <8 x i1> %3 to <8 x i16>
240 ret <8 x i16> %4
241 }
243 define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) {
244 ; CHECK-LABEL: ugt_4_v8i16:
245 ; CHECK: // %bb.0:
246 ; CHECK-NEXT: cnt v0.16b, v0.16b
247 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
248 ; CHECK-NEXT: movi v1.8h, #4
249 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
250 ; CHECK-NEXT: ret
251 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
252 %3 = icmp ugt <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
253 %4 = sext <8 x i1> %3 to <8 x i16>
254 ret <8 x i16> %4
255 }
257 define <8 x i16> @ult_5_v8i16(<8 x i16> %0) {
258 ; CHECK-LABEL: ult_5_v8i16:
259 ; CHECK: // %bb.0:
260 ; CHECK-NEXT: cnt v0.16b, v0.16b
261 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
262 ; CHECK-NEXT: movi v1.8h, #5
263 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
264 ; CHECK-NEXT: ret
265 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
266 %3 = icmp ult <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
267 %4 = sext <8 x i1> %3 to <8 x i16>
268 ret <8 x i16> %4
269 }
271 define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) {
272 ; CHECK-LABEL: ugt_5_v8i16:
273 ; CHECK: // %bb.0:
274 ; CHECK-NEXT: cnt v0.16b, v0.16b
275 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
276 ; CHECK-NEXT: movi v1.8h, #5
277 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
278 ; CHECK-NEXT: ret
279 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
280 %3 = icmp ugt <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
281 %4 = sext <8 x i1> %3 to <8 x i16>
282 ret <8 x i16> %4
283 }
285 define <8 x i16> @ult_6_v8i16(<8 x i16> %0) {
286 ; CHECK-LABEL: ult_6_v8i16:
287 ; CHECK: // %bb.0:
288 ; CHECK-NEXT: cnt v0.16b, v0.16b
289 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
290 ; CHECK-NEXT: movi v1.8h, #6
291 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
292 ; CHECK-NEXT: ret
293 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
294 %3 = icmp ult <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
295 %4 = sext <8 x i1> %3 to <8 x i16>
296 ret <8 x i16> %4
297 }
299 define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) {
300 ; CHECK-LABEL: ugt_6_v8i16:
301 ; CHECK: // %bb.0:
302 ; CHECK-NEXT: cnt v0.16b, v0.16b
303 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
304 ; CHECK-NEXT: movi v1.8h, #6
305 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
306 ; CHECK-NEXT: ret
307 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
308 %3 = icmp ugt <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
309 %4 = sext <8 x i1> %3 to <8 x i16>
310 ret <8 x i16> %4
311 }
313 define <8 x i16> @ult_7_v8i16(<8 x i16> %0) {
314 ; CHECK-LABEL: ult_7_v8i16:
315 ; CHECK: // %bb.0:
316 ; CHECK-NEXT: cnt v0.16b, v0.16b
317 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
318 ; CHECK-NEXT: movi v1.8h, #7
319 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
320 ; CHECK-NEXT: ret
321 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
322 %3 = icmp ult <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
323 %4 = sext <8 x i1> %3 to <8 x i16>
324 ret <8 x i16> %4
325 }
327 define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) {
328 ; CHECK-LABEL: ugt_7_v8i16:
329 ; CHECK: // %bb.0:
330 ; CHECK-NEXT: cnt v0.16b, v0.16b
331 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
332 ; CHECK-NEXT: movi v1.8h, #7
333 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
334 ; CHECK-NEXT: ret
335 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
336 %3 = icmp ugt <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
337 %4 = sext <8 x i1> %3 to <8 x i16>
338 ret <8 x i16> %4
339 }
341 define <8 x i16> @ult_8_v8i16(<8 x i16> %0) {
342 ; CHECK-LABEL: ult_8_v8i16:
343 ; CHECK: // %bb.0:
344 ; CHECK-NEXT: cnt v0.16b, v0.16b
345 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
346 ; CHECK-NEXT: movi v1.8h, #8
347 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
348 ; CHECK-NEXT: ret
349 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
350 %3 = icmp ult <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
351 %4 = sext <8 x i1> %3 to <8 x i16>
352 ret <8 x i16> %4
353 }
355 define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) {
356 ; CHECK-LABEL: ugt_8_v8i16:
357 ; CHECK: // %bb.0:
358 ; CHECK-NEXT: cnt v0.16b, v0.16b
359 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
360 ; CHECK-NEXT: movi v1.8h, #8
361 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
362 ; CHECK-NEXT: ret
363 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
364 %3 = icmp ugt <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
365 %4 = sext <8 x i1> %3 to <8 x i16>
366 ret <8 x i16> %4
367 }
369 define <8 x i16> @ult_9_v8i16(<8 x i16> %0) {
370 ; CHECK-LABEL: ult_9_v8i16:
371 ; CHECK: // %bb.0:
372 ; CHECK-NEXT: cnt v0.16b, v0.16b
373 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
374 ; CHECK-NEXT: movi v1.8h, #9
375 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
376 ; CHECK-NEXT: ret
377 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
378 %3 = icmp ult <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
379 %4 = sext <8 x i1> %3 to <8 x i16>
380 ret <8 x i16> %4
381 }
383 define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) {
384 ; CHECK-LABEL: ugt_9_v8i16:
385 ; CHECK: // %bb.0:
386 ; CHECK-NEXT: cnt v0.16b, v0.16b
387 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
388 ; CHECK-NEXT: movi v1.8h, #9
389 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
390 ; CHECK-NEXT: ret
391 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
392 %3 = icmp ugt <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
393 %4 = sext <8 x i1> %3 to <8 x i16>
394 ret <8 x i16> %4
395 }
397 define <8 x i16> @ult_10_v8i16(<8 x i16> %0) {
398 ; CHECK-LABEL: ult_10_v8i16:
399 ; CHECK: // %bb.0:
400 ; CHECK-NEXT: cnt v0.16b, v0.16b
401 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
402 ; CHECK-NEXT: movi v1.8h, #10
403 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
404 ; CHECK-NEXT: ret
405 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
406 %3 = icmp ult <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
407 %4 = sext <8 x i1> %3 to <8 x i16>
408 ret <8 x i16> %4
409 }
411 define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) {
412 ; CHECK-LABEL: ugt_10_v8i16:
413 ; CHECK: // %bb.0:
414 ; CHECK-NEXT: cnt v0.16b, v0.16b
415 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
416 ; CHECK-NEXT: movi v1.8h, #10
417 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
418 ; CHECK-NEXT: ret
419 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
420 %3 = icmp ugt <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
421 %4 = sext <8 x i1> %3 to <8 x i16>
422 ret <8 x i16> %4
423 }
425 define <8 x i16> @ult_11_v8i16(<8 x i16> %0) {
426 ; CHECK-LABEL: ult_11_v8i16:
427 ; CHECK: // %bb.0:
428 ; CHECK-NEXT: cnt v0.16b, v0.16b
429 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
430 ; CHECK-NEXT: movi v1.8h, #11
431 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
432 ; CHECK-NEXT: ret
433 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
434 %3 = icmp ult <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
435 %4 = sext <8 x i1> %3 to <8 x i16>
436 ret <8 x i16> %4
437 }
439 define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) {
440 ; CHECK-LABEL: ugt_11_v8i16:
441 ; CHECK: // %bb.0:
442 ; CHECK-NEXT: cnt v0.16b, v0.16b
443 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
444 ; CHECK-NEXT: movi v1.8h, #11
445 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
446 ; CHECK-NEXT: ret
447 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
448 %3 = icmp ugt <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
449 %4 = sext <8 x i1> %3 to <8 x i16>
450 ret <8 x i16> %4
451 }
453 define <8 x i16> @ult_12_v8i16(<8 x i16> %0) {
454 ; CHECK-LABEL: ult_12_v8i16:
455 ; CHECK: // %bb.0:
456 ; CHECK-NEXT: cnt v0.16b, v0.16b
457 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
458 ; CHECK-NEXT: movi v1.8h, #12
459 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
460 ; CHECK-NEXT: ret
461 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
462 %3 = icmp ult <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
463 %4 = sext <8 x i1> %3 to <8 x i16>
464 ret <8 x i16> %4
465 }
467 define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) {
468 ; CHECK-LABEL: ugt_12_v8i16:
469 ; CHECK: // %bb.0:
470 ; CHECK-NEXT: cnt v0.16b, v0.16b
471 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
472 ; CHECK-NEXT: movi v1.8h, #12
473 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
474 ; CHECK-NEXT: ret
475 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
476 %3 = icmp ugt <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
477 %4 = sext <8 x i1> %3 to <8 x i16>
478 ret <8 x i16> %4
479 }
481 define <8 x i16> @ult_13_v8i16(<8 x i16> %0) {
482 ; CHECK-LABEL: ult_13_v8i16:
483 ; CHECK: // %bb.0:
484 ; CHECK-NEXT: cnt v0.16b, v0.16b
485 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
486 ; CHECK-NEXT: movi v1.8h, #13
487 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
488 ; CHECK-NEXT: ret
489 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
490 %3 = icmp ult <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
491 %4 = sext <8 x i1> %3 to <8 x i16>
492 ret <8 x i16> %4
493 }
495 define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) {
496 ; CHECK-LABEL: ugt_13_v8i16:
497 ; CHECK: // %bb.0:
498 ; CHECK-NEXT: cnt v0.16b, v0.16b
499 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
500 ; CHECK-NEXT: movi v1.8h, #13
501 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
502 ; CHECK-NEXT: ret
503 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
504 %3 = icmp ugt <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13>
505 %4 = sext <8 x i1> %3 to <8 x i16>
506 ret <8 x i16> %4
507 }
509 define <8 x i16> @ult_14_v8i16(<8 x i16> %0) {
510 ; CHECK-LABEL: ult_14_v8i16:
511 ; CHECK: // %bb.0:
512 ; CHECK-NEXT: cnt v0.16b, v0.16b
513 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
514 ; CHECK-NEXT: movi v1.8h, #14
515 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
516 ; CHECK-NEXT: ret
517 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
518 %3 = icmp ult <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
519 %4 = sext <8 x i1> %3 to <8 x i16>
520 ret <8 x i16> %4
521 }
523 define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) {
524 ; CHECK-LABEL: ugt_14_v8i16:
525 ; CHECK: // %bb.0:
526 ; CHECK-NEXT: cnt v0.16b, v0.16b
527 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
528 ; CHECK-NEXT: movi v1.8h, #14
529 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
530 ; CHECK-NEXT: ret
531 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
532 %3 = icmp ugt <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
533 %4 = sext <8 x i1> %3 to <8 x i16>
534 ret <8 x i16> %4
535 }
537 define <8 x i16> @ult_15_v8i16(<8 x i16> %0) {
538 ; CHECK-LABEL: ult_15_v8i16:
539 ; CHECK: // %bb.0:
540 ; CHECK-NEXT: cnt v0.16b, v0.16b
541 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
542 ; CHECK-NEXT: movi v1.8h, #15
543 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
544 ; CHECK-NEXT: ret
545 %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
546 %3 = icmp ult <8 x i16> %2, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
547 %4 = sext <8 x i1> %3 to <8 x i16>
548 ret <8 x i16> %4
549 }
551 define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) {
552 ; CHECK-LABEL: ugt_1_v4i32:
553 ; CHECK: // %bb.0:
554 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
555 ; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
556 ; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
557 ; CHECK-NEXT: ret
558 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
559 %3 = icmp ugt <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
560 %4 = sext <4 x i1> %3 to <4 x i32>
561 ret <4 x i32> %4
562 }
564 define <4 x i32> @ult_2_v4i32(<4 x i32> %0) {
565 ; CHECK-LABEL: ult_2_v4i32:
566 ; CHECK: // %bb.0:
567 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
568 ; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
569 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
570 ; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
571 ; CHECK-NEXT: ret
572 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
573 %3 = icmp ult <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
574 %4 = sext <4 x i1> %3 to <4 x i32>
575 ret <4 x i32> %4
576 }
578 define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) {
579 ; CHECK-LABEL: ugt_2_v4i32:
580 ; CHECK: // %bb.0:
581 ; CHECK-NEXT: cnt v0.16b, v0.16b
582 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
583 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
584 ; CHECK-NEXT: movi v1.4s, #2
585 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
586 ; CHECK-NEXT: ret
587 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
588 %3 = icmp ugt <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
589 %4 = sext <4 x i1> %3 to <4 x i32>
590 ret <4 x i32> %4
591 }
593 define <4 x i32> @ult_3_v4i32(<4 x i32> %0) {
594 ; CHECK-LABEL: ult_3_v4i32:
595 ; CHECK: // %bb.0:
596 ; CHECK-NEXT: cnt v0.16b, v0.16b
597 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
598 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
599 ; CHECK-NEXT: movi v1.4s, #3
600 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
601 ; CHECK-NEXT: ret
602 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
603 %3 = icmp ult <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
604 %4 = sext <4 x i1> %3 to <4 x i32>
605 ret <4 x i32> %4
606 }
608 define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) {
609 ; CHECK-LABEL: ugt_3_v4i32:
610 ; CHECK: // %bb.0:
611 ; CHECK-NEXT: cnt v0.16b, v0.16b
612 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
613 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
614 ; CHECK-NEXT: movi v1.4s, #3
615 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
616 ; CHECK-NEXT: ret
617 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
618 %3 = icmp ugt <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
619 %4 = sext <4 x i1> %3 to <4 x i32>
620 ret <4 x i32> %4
621 }
623 define <4 x i32> @ult_4_v4i32(<4 x i32> %0) {
624 ; CHECK-LABEL: ult_4_v4i32:
625 ; CHECK: // %bb.0:
626 ; CHECK-NEXT: cnt v0.16b, v0.16b
627 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
628 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
629 ; CHECK-NEXT: movi v1.4s, #4
630 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
631 ; CHECK-NEXT: ret
632 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
633 %3 = icmp ult <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
634 %4 = sext <4 x i1> %3 to <4 x i32>
635 ret <4 x i32> %4
636 }
638 define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) {
639 ; CHECK-LABEL: ugt_4_v4i32:
640 ; CHECK: // %bb.0:
641 ; CHECK-NEXT: cnt v0.16b, v0.16b
642 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
643 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
644 ; CHECK-NEXT: movi v1.4s, #4
645 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
646 ; CHECK-NEXT: ret
647 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
648 %3 = icmp ugt <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4>
649 %4 = sext <4 x i1> %3 to <4 x i32>
650 ret <4 x i32> %4
651 }
653 define <4 x i32> @ult_5_v4i32(<4 x i32> %0) {
654 ; CHECK-LABEL: ult_5_v4i32:
655 ; CHECK: // %bb.0:
656 ; CHECK-NEXT: cnt v0.16b, v0.16b
657 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
658 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
659 ; CHECK-NEXT: movi v1.4s, #5
660 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
661 ; CHECK-NEXT: ret
662 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
663 %3 = icmp ult <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
664 %4 = sext <4 x i1> %3 to <4 x i32>
665 ret <4 x i32> %4
666 }
668 define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) {
669 ; CHECK-LABEL: ugt_5_v4i32:
670 ; CHECK: // %bb.0:
671 ; CHECK-NEXT: cnt v0.16b, v0.16b
672 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
673 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
674 ; CHECK-NEXT: movi v1.4s, #5
675 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
676 ; CHECK-NEXT: ret
677 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
678 %3 = icmp ugt <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5>
679 %4 = sext <4 x i1> %3 to <4 x i32>
680 ret <4 x i32> %4
681 }
683 define <4 x i32> @ult_6_v4i32(<4 x i32> %0) {
684 ; CHECK-LABEL: ult_6_v4i32:
685 ; CHECK: // %bb.0:
686 ; CHECK-NEXT: cnt v0.16b, v0.16b
687 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
688 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
689 ; CHECK-NEXT: movi v1.4s, #6
690 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
691 ; CHECK-NEXT: ret
692 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
693 %3 = icmp ult <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
694 %4 = sext <4 x i1> %3 to <4 x i32>
695 ret <4 x i32> %4
696 }
698 define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) {
699 ; CHECK-LABEL: ugt_6_v4i32:
700 ; CHECK: // %bb.0:
701 ; CHECK-NEXT: cnt v0.16b, v0.16b
702 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
703 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
704 ; CHECK-NEXT: movi v1.4s, #6
705 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
706 ; CHECK-NEXT: ret
707 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
708 %3 = icmp ugt <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6>
709 %4 = sext <4 x i1> %3 to <4 x i32>
710 ret <4 x i32> %4
711 }
713 define <4 x i32> @ult_7_v4i32(<4 x i32> %0) {
714 ; CHECK-LABEL: ult_7_v4i32:
715 ; CHECK: // %bb.0:
716 ; CHECK-NEXT: cnt v0.16b, v0.16b
717 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
718 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
719 ; CHECK-NEXT: movi v1.4s, #7
720 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
721 ; CHECK-NEXT: ret
722 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
723 %3 = icmp ult <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
724 %4 = sext <4 x i1> %3 to <4 x i32>
725 ret <4 x i32> %4
726 }
728 define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) {
729 ; CHECK-LABEL: ugt_7_v4i32:
730 ; CHECK: // %bb.0:
731 ; CHECK-NEXT: cnt v0.16b, v0.16b
732 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
733 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
734 ; CHECK-NEXT: movi v1.4s, #7
735 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
736 ; CHECK-NEXT: ret
737 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
738 %3 = icmp ugt <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7>
739 %4 = sext <4 x i1> %3 to <4 x i32>
740 ret <4 x i32> %4
741 }
743 define <4 x i32> @ult_8_v4i32(<4 x i32> %0) {
744 ; CHECK-LABEL: ult_8_v4i32:
745 ; CHECK: // %bb.0:
746 ; CHECK-NEXT: cnt v0.16b, v0.16b
747 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
748 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
749 ; CHECK-NEXT: movi v1.4s, #8
750 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
751 ; CHECK-NEXT: ret
752 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
753 %3 = icmp ult <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
754 %4 = sext <4 x i1> %3 to <4 x i32>
755 ret <4 x i32> %4
756 }
758 define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) {
759 ; CHECK-LABEL: ugt_8_v4i32:
760 ; CHECK: // %bb.0:
761 ; CHECK-NEXT: cnt v0.16b, v0.16b
762 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
763 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
764 ; CHECK-NEXT: movi v1.4s, #8
765 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
766 ; CHECK-NEXT: ret
767 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
768 %3 = icmp ugt <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8>
769 %4 = sext <4 x i1> %3 to <4 x i32>
770 ret <4 x i32> %4
771 }
773 define <4 x i32> @ult_9_v4i32(<4 x i32> %0) {
774 ; CHECK-LABEL: ult_9_v4i32:
775 ; CHECK: // %bb.0:
776 ; CHECK-NEXT: cnt v0.16b, v0.16b
777 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
778 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
779 ; CHECK-NEXT: movi v1.4s, #9
780 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
781 ; CHECK-NEXT: ret
782 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
783 %3 = icmp ult <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
784 %4 = sext <4 x i1> %3 to <4 x i32>
785 ret <4 x i32> %4
786 }
788 define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) {
789 ; CHECK-LABEL: ugt_9_v4i32:
790 ; CHECK: // %bb.0:
791 ; CHECK-NEXT: cnt v0.16b, v0.16b
792 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
793 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
794 ; CHECK-NEXT: movi v1.4s, #9
795 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
796 ; CHECK-NEXT: ret
797 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
798 %3 = icmp ugt <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
799 %4 = sext <4 x i1> %3 to <4 x i32>
800 ret <4 x i32> %4
801 }
803 define <4 x i32> @ult_10_v4i32(<4 x i32> %0) {
804 ; CHECK-LABEL: ult_10_v4i32:
805 ; CHECK: // %bb.0:
806 ; CHECK-NEXT: cnt v0.16b, v0.16b
807 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
808 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
809 ; CHECK-NEXT: movi v1.4s, #10
810 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
811 ; CHECK-NEXT: ret
812 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
813 %3 = icmp ult <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
814 %4 = sext <4 x i1> %3 to <4 x i32>
815 ret <4 x i32> %4
816 }
818 define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) {
819 ; CHECK-LABEL: ugt_10_v4i32:
820 ; CHECK: // %bb.0:
821 ; CHECK-NEXT: cnt v0.16b, v0.16b
822 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
823 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
824 ; CHECK-NEXT: movi v1.4s, #10
825 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
826 ; CHECK-NEXT: ret
827 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
828 %3 = icmp ugt <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10>
829 %4 = sext <4 x i1> %3 to <4 x i32>
830 ret <4 x i32> %4
831 }
833 define <4 x i32> @ult_11_v4i32(<4 x i32> %0) {
834 ; CHECK-LABEL: ult_11_v4i32:
835 ; CHECK: // %bb.0:
836 ; CHECK-NEXT: cnt v0.16b, v0.16b
837 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
838 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
839 ; CHECK-NEXT: movi v1.4s, #11
840 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
841 ; CHECK-NEXT: ret
842 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
843 %3 = icmp ult <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
844 %4 = sext <4 x i1> %3 to <4 x i32>
845 ret <4 x i32> %4
846 }
848 define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) {
849 ; CHECK-LABEL: ugt_11_v4i32:
850 ; CHECK: // %bb.0:
851 ; CHECK-NEXT: cnt v0.16b, v0.16b
852 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
853 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
854 ; CHECK-NEXT: movi v1.4s, #11
855 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
856 ; CHECK-NEXT: ret
857 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
858 %3 = icmp ugt <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11>
859 %4 = sext <4 x i1> %3 to <4 x i32>
860 ret <4 x i32> %4
861 }
863 define <4 x i32> @ult_12_v4i32(<4 x i32> %0) {
864 ; CHECK-LABEL: ult_12_v4i32:
865 ; CHECK: // %bb.0:
866 ; CHECK-NEXT: cnt v0.16b, v0.16b
867 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
868 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
869 ; CHECK-NEXT: movi v1.4s, #12
870 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
871 ; CHECK-NEXT: ret
872 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
873 %3 = icmp ult <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
874 %4 = sext <4 x i1> %3 to <4 x i32>
875 ret <4 x i32> %4
876 }
878 define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) {
879 ; CHECK-LABEL: ugt_12_v4i32:
880 ; CHECK: // %bb.0:
881 ; CHECK-NEXT: cnt v0.16b, v0.16b
882 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
883 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
884 ; CHECK-NEXT: movi v1.4s, #12
885 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
886 ; CHECK-NEXT: ret
887 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
888 %3 = icmp ugt <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12>
889 %4 = sext <4 x i1> %3 to <4 x i32>
890 ret <4 x i32> %4
891 }
893 define <4 x i32> @ult_13_v4i32(<4 x i32> %0) {
894 ; CHECK-LABEL: ult_13_v4i32:
895 ; CHECK: // %bb.0:
896 ; CHECK-NEXT: cnt v0.16b, v0.16b
897 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
898 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
899 ; CHECK-NEXT: movi v1.4s, #13
900 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
901 ; CHECK-NEXT: ret
902 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
903 %3 = icmp ult <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
904 %4 = sext <4 x i1> %3 to <4 x i32>
905 ret <4 x i32> %4
906 }
908 define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) {
909 ; CHECK-LABEL: ugt_13_v4i32:
910 ; CHECK: // %bb.0:
911 ; CHECK-NEXT: cnt v0.16b, v0.16b
912 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
913 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
914 ; CHECK-NEXT: movi v1.4s, #13
915 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
916 ; CHECK-NEXT: ret
917 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
918 %3 = icmp ugt <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13>
919 %4 = sext <4 x i1> %3 to <4 x i32>
920 ret <4 x i32> %4
921 }
923 define <4 x i32> @ult_14_v4i32(<4 x i32> %0) {
924 ; CHECK-LABEL: ult_14_v4i32:
925 ; CHECK: // %bb.0:
926 ; CHECK-NEXT: cnt v0.16b, v0.16b
927 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
928 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
929 ; CHECK-NEXT: movi v1.4s, #14
930 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
931 ; CHECK-NEXT: ret
932 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
933 %3 = icmp ult <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
934 %4 = sext <4 x i1> %3 to <4 x i32>
935 ret <4 x i32> %4
936 }
938 define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) {
939 ; CHECK-LABEL: ugt_14_v4i32:
940 ; CHECK: // %bb.0:
941 ; CHECK-NEXT: cnt v0.16b, v0.16b
942 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
943 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
944 ; CHECK-NEXT: movi v1.4s, #14
945 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
946 ; CHECK-NEXT: ret
947 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
948 %3 = icmp ugt <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14>
949 %4 = sext <4 x i1> %3 to <4 x i32>
950 ret <4 x i32> %4
951 }
953 define <4 x i32> @ult_15_v4i32(<4 x i32> %0) {
954 ; CHECK-LABEL: ult_15_v4i32:
955 ; CHECK: // %bb.0:
956 ; CHECK-NEXT: cnt v0.16b, v0.16b
957 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
958 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
959 ; CHECK-NEXT: movi v1.4s, #15
960 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
961 ; CHECK-NEXT: ret
962 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
963 %3 = icmp ult <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
964 %4 = sext <4 x i1> %3 to <4 x i32>
965 ret <4 x i32> %4
966 }
968 define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) {
969 ; CHECK-LABEL: ugt_15_v4i32:
970 ; CHECK: // %bb.0:
971 ; CHECK-NEXT: cnt v0.16b, v0.16b
972 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
973 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
974 ; CHECK-NEXT: movi v1.4s, #15
975 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
976 ; CHECK-NEXT: ret
977 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
978 %3 = icmp ugt <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
979 %4 = sext <4 x i1> %3 to <4 x i32>
980 ret <4 x i32> %4
981 }
983 define <4 x i32> @ult_16_v4i32(<4 x i32> %0) {
984 ; CHECK-LABEL: ult_16_v4i32:
985 ; CHECK: // %bb.0:
986 ; CHECK-NEXT: cnt v0.16b, v0.16b
987 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
988 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
989 ; CHECK-NEXT: movi v1.4s, #16
990 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
991 ; CHECK-NEXT: ret
992 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
993 %3 = icmp ult <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
994 %4 = sext <4 x i1> %3 to <4 x i32>
995 ret <4 x i32> %4
996 }
998 define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) {
999 ; CHECK-LABEL: ugt_16_v4i32:
1000 ; CHECK: // %bb.0:
1001 ; CHECK-NEXT: cnt v0.16b, v0.16b
1002 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1003 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1004 ; CHECK-NEXT: movi v1.4s, #16
1005 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1006 ; CHECK-NEXT: ret
1007 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1008 %3 = icmp ugt <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16>
1009 %4 = sext <4 x i1> %3 to <4 x i32>
1010 ret <4 x i32> %4
1011 }
1013 define <4 x i32> @ult_17_v4i32(<4 x i32> %0) {
1014 ; CHECK-LABEL: ult_17_v4i32:
1015 ; CHECK: // %bb.0:
1016 ; CHECK-NEXT: cnt v0.16b, v0.16b
1017 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1018 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1019 ; CHECK-NEXT: movi v1.4s, #17
1020 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1021 ; CHECK-NEXT: ret
1022 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1023 %3 = icmp ult <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
1024 %4 = sext <4 x i1> %3 to <4 x i32>
1025 ret <4 x i32> %4
1026 }
1028 define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) {
1029 ; CHECK-LABEL: ugt_17_v4i32:
1030 ; CHECK: // %bb.0:
1031 ; CHECK-NEXT: cnt v0.16b, v0.16b
1032 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1033 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1034 ; CHECK-NEXT: movi v1.4s, #17
1035 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1036 ; CHECK-NEXT: ret
1037 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1038 %3 = icmp ugt <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17>
1039 %4 = sext <4 x i1> %3 to <4 x i32>
1040 ret <4 x i32> %4
1041 }
1043 define <4 x i32> @ult_18_v4i32(<4 x i32> %0) {
1044 ; CHECK-LABEL: ult_18_v4i32:
1045 ; CHECK: // %bb.0:
1046 ; CHECK-NEXT: cnt v0.16b, v0.16b
1047 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1048 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1049 ; CHECK-NEXT: movi v1.4s, #18
1050 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1051 ; CHECK-NEXT: ret
1052 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1053 %3 = icmp ult <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
1054 %4 = sext <4 x i1> %3 to <4 x i32>
1055 ret <4 x i32> %4
1056 }
1058 define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) {
1059 ; CHECK-LABEL: ugt_18_v4i32:
1060 ; CHECK: // %bb.0:
1061 ; CHECK-NEXT: cnt v0.16b, v0.16b
1062 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1063 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1064 ; CHECK-NEXT: movi v1.4s, #18
1065 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1066 ; CHECK-NEXT: ret
1067 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1068 %3 = icmp ugt <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18>
1069 %4 = sext <4 x i1> %3 to <4 x i32>
1070 ret <4 x i32> %4
1071 }
1073 define <4 x i32> @ult_19_v4i32(<4 x i32> %0) {
1074 ; CHECK-LABEL: ult_19_v4i32:
1075 ; CHECK: // %bb.0:
1076 ; CHECK-NEXT: cnt v0.16b, v0.16b
1077 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1078 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1079 ; CHECK-NEXT: movi v1.4s, #19
1080 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1081 ; CHECK-NEXT: ret
1082 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1083 %3 = icmp ult <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
1084 %4 = sext <4 x i1> %3 to <4 x i32>
1085 ret <4 x i32> %4
1086 }
1088 define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) {
1089 ; CHECK-LABEL: ugt_19_v4i32:
1090 ; CHECK: // %bb.0:
1091 ; CHECK-NEXT: cnt v0.16b, v0.16b
1092 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1093 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1094 ; CHECK-NEXT: movi v1.4s, #19
1095 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1096 ; CHECK-NEXT: ret
1097 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1098 %3 = icmp ugt <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>
1099 %4 = sext <4 x i1> %3 to <4 x i32>
1100 ret <4 x i32> %4
1101 }
1103 define <4 x i32> @ult_20_v4i32(<4 x i32> %0) {
1104 ; CHECK-LABEL: ult_20_v4i32:
1105 ; CHECK: // %bb.0:
1106 ; CHECK-NEXT: cnt v0.16b, v0.16b
1107 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1108 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1109 ; CHECK-NEXT: movi v1.4s, #20
1110 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1111 ; CHECK-NEXT: ret
1112 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1113 %3 = icmp ult <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
1114 %4 = sext <4 x i1> %3 to <4 x i32>
1115 ret <4 x i32> %4
1116 }
1118 define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) {
1119 ; CHECK-LABEL: ugt_20_v4i32:
1120 ; CHECK: // %bb.0:
1121 ; CHECK-NEXT: cnt v0.16b, v0.16b
1122 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1123 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1124 ; CHECK-NEXT: movi v1.4s, #20
1125 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1126 ; CHECK-NEXT: ret
1127 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1128 %3 = icmp ugt <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20>
1129 %4 = sext <4 x i1> %3 to <4 x i32>
1130 ret <4 x i32> %4
1131 }
1133 define <4 x i32> @ult_21_v4i32(<4 x i32> %0) {
1134 ; CHECK-LABEL: ult_21_v4i32:
1135 ; CHECK: // %bb.0:
1136 ; CHECK-NEXT: cnt v0.16b, v0.16b
1137 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1138 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1139 ; CHECK-NEXT: movi v1.4s, #21
1140 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1141 ; CHECK-NEXT: ret
1142 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1143 %3 = icmp ult <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
1144 %4 = sext <4 x i1> %3 to <4 x i32>
1145 ret <4 x i32> %4
1146 }
1148 define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) {
1149 ; CHECK-LABEL: ugt_21_v4i32:
1150 ; CHECK: // %bb.0:
1151 ; CHECK-NEXT: cnt v0.16b, v0.16b
1152 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1153 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1154 ; CHECK-NEXT: movi v1.4s, #21
1155 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1156 ; CHECK-NEXT: ret
1157 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1158 %3 = icmp ugt <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21>
1159 %4 = sext <4 x i1> %3 to <4 x i32>
1160 ret <4 x i32> %4
1161 }
1163 define <4 x i32> @ult_22_v4i32(<4 x i32> %0) {
1164 ; CHECK-LABEL: ult_22_v4i32:
1165 ; CHECK: // %bb.0:
1166 ; CHECK-NEXT: cnt v0.16b, v0.16b
1167 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1168 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1169 ; CHECK-NEXT: movi v1.4s, #22
1170 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1171 ; CHECK-NEXT: ret
1172 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1173 %3 = icmp ult <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
1174 %4 = sext <4 x i1> %3 to <4 x i32>
1175 ret <4 x i32> %4
1176 }
1178 define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) {
1179 ; CHECK-LABEL: ugt_22_v4i32:
1180 ; CHECK: // %bb.0:
1181 ; CHECK-NEXT: cnt v0.16b, v0.16b
1182 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1183 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1184 ; CHECK-NEXT: movi v1.4s, #22
1185 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1186 ; CHECK-NEXT: ret
1187 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1188 %3 = icmp ugt <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
1189 %4 = sext <4 x i1> %3 to <4 x i32>
1190 ret <4 x i32> %4
1191 }
1193 define <4 x i32> @ult_23_v4i32(<4 x i32> %0) {
1194 ; CHECK-LABEL: ult_23_v4i32:
1195 ; CHECK: // %bb.0:
1196 ; CHECK-NEXT: cnt v0.16b, v0.16b
1197 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1198 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1199 ; CHECK-NEXT: movi v1.4s, #23
1200 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1201 ; CHECK-NEXT: ret
1202 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1203 %3 = icmp ult <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
1204 %4 = sext <4 x i1> %3 to <4 x i32>
1205 ret <4 x i32> %4
1206 }
1208 define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) {
1209 ; CHECK-LABEL: ugt_23_v4i32:
1210 ; CHECK: // %bb.0:
1211 ; CHECK-NEXT: cnt v0.16b, v0.16b
1212 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1213 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1214 ; CHECK-NEXT: movi v1.4s, #23
1215 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1216 ; CHECK-NEXT: ret
1217 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1218 %3 = icmp ugt <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23>
1219 %4 = sext <4 x i1> %3 to <4 x i32>
1220 ret <4 x i32> %4
1221 }
1223 define <4 x i32> @ult_24_v4i32(<4 x i32> %0) {
1224 ; CHECK-LABEL: ult_24_v4i32:
1225 ; CHECK: // %bb.0:
1226 ; CHECK-NEXT: cnt v0.16b, v0.16b
1227 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1228 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1229 ; CHECK-NEXT: movi v1.4s, #24
1230 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1231 ; CHECK-NEXT: ret
1232 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1233 %3 = icmp ult <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
1234 %4 = sext <4 x i1> %3 to <4 x i32>
1235 ret <4 x i32> %4
1236 }
1238 define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) {
1239 ; CHECK-LABEL: ugt_24_v4i32:
1240 ; CHECK: // %bb.0:
1241 ; CHECK-NEXT: cnt v0.16b, v0.16b
1242 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1243 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1244 ; CHECK-NEXT: movi v1.4s, #24
1245 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1246 ; CHECK-NEXT: ret
1247 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1248 %3 = icmp ugt <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24>
1249 %4 = sext <4 x i1> %3 to <4 x i32>
1250 ret <4 x i32> %4
1251 }
1253 define <4 x i32> @ult_25_v4i32(<4 x i32> %0) {
1254 ; CHECK-LABEL: ult_25_v4i32:
1255 ; CHECK: // %bb.0:
1256 ; CHECK-NEXT: cnt v0.16b, v0.16b
1257 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1258 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1259 ; CHECK-NEXT: movi v1.4s, #25
1260 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1261 ; CHECK-NEXT: ret
1262 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1263 %3 = icmp ult <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
1264 %4 = sext <4 x i1> %3 to <4 x i32>
1265 ret <4 x i32> %4
1266 }
1268 define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) {
1269 ; CHECK-LABEL: ugt_25_v4i32:
1270 ; CHECK: // %bb.0:
1271 ; CHECK-NEXT: cnt v0.16b, v0.16b
1272 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1273 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1274 ; CHECK-NEXT: movi v1.4s, #25
1275 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1276 ; CHECK-NEXT: ret
1277 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1278 %3 = icmp ugt <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25>
1279 %4 = sext <4 x i1> %3 to <4 x i32>
1280 ret <4 x i32> %4
1281 }
1283 define <4 x i32> @ult_26_v4i32(<4 x i32> %0) {
1284 ; CHECK-LABEL: ult_26_v4i32:
1285 ; CHECK: // %bb.0:
1286 ; CHECK-NEXT: cnt v0.16b, v0.16b
1287 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1288 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1289 ; CHECK-NEXT: movi v1.4s, #26
1290 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1291 ; CHECK-NEXT: ret
1292 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1293 %3 = icmp ult <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
1294 %4 = sext <4 x i1> %3 to <4 x i32>
1295 ret <4 x i32> %4
1296 }
1298 define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) {
1299 ; CHECK-LABEL: ugt_26_v4i32:
1300 ; CHECK: // %bb.0:
1301 ; CHECK-NEXT: cnt v0.16b, v0.16b
1302 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1303 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1304 ; CHECK-NEXT: movi v1.4s, #26
1305 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1306 ; CHECK-NEXT: ret
1307 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1308 %3 = icmp ugt <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
1309 %4 = sext <4 x i1> %3 to <4 x i32>
1310 ret <4 x i32> %4
1311 }
1313 define <4 x i32> @ult_27_v4i32(<4 x i32> %0) {
1314 ; CHECK-LABEL: ult_27_v4i32:
1315 ; CHECK: // %bb.0:
1316 ; CHECK-NEXT: cnt v0.16b, v0.16b
1317 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1318 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1319 ; CHECK-NEXT: movi v1.4s, #27
1320 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1321 ; CHECK-NEXT: ret
1322 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1323 %3 = icmp ult <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
1324 %4 = sext <4 x i1> %3 to <4 x i32>
1325 ret <4 x i32> %4
1326 }
1328 define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) {
1329 ; CHECK-LABEL: ugt_27_v4i32:
1330 ; CHECK: // %bb.0:
1331 ; CHECK-NEXT: cnt v0.16b, v0.16b
1332 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1333 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1334 ; CHECK-NEXT: movi v1.4s, #27
1335 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1336 ; CHECK-NEXT: ret
1337 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1338 %3 = icmp ugt <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27>
1339 %4 = sext <4 x i1> %3 to <4 x i32>
1340 ret <4 x i32> %4
1341 }
1343 define <4 x i32> @ult_28_v4i32(<4 x i32> %0) {
1344 ; CHECK-LABEL: ult_28_v4i32:
1345 ; CHECK: // %bb.0:
1346 ; CHECK-NEXT: cnt v0.16b, v0.16b
1347 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1348 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1349 ; CHECK-NEXT: movi v1.4s, #28
1350 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1351 ; CHECK-NEXT: ret
1352 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1353 %3 = icmp ult <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
1354 %4 = sext <4 x i1> %3 to <4 x i32>
1355 ret <4 x i32> %4
1356 }
1358 define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) {
1359 ; CHECK-LABEL: ugt_28_v4i32:
1360 ; CHECK: // %bb.0:
1361 ; CHECK-NEXT: cnt v0.16b, v0.16b
1362 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1363 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1364 ; CHECK-NEXT: movi v1.4s, #28
1365 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1366 ; CHECK-NEXT: ret
1367 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1368 %3 = icmp ugt <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28>
1369 %4 = sext <4 x i1> %3 to <4 x i32>
1370 ret <4 x i32> %4
1371 }
1373 define <4 x i32> @ult_29_v4i32(<4 x i32> %0) {
1374 ; CHECK-LABEL: ult_29_v4i32:
1375 ; CHECK: // %bb.0:
1376 ; CHECK-NEXT: cnt v0.16b, v0.16b
1377 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1378 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1379 ; CHECK-NEXT: movi v1.4s, #29
1380 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1381 ; CHECK-NEXT: ret
1382 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1383 %3 = icmp ult <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
1384 %4 = sext <4 x i1> %3 to <4 x i32>
1385 ret <4 x i32> %4
1386 }
1388 define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) {
1389 ; CHECK-LABEL: ugt_29_v4i32:
1390 ; CHECK: // %bb.0:
1391 ; CHECK-NEXT: cnt v0.16b, v0.16b
1392 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1393 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1394 ; CHECK-NEXT: movi v1.4s, #29
1395 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1396 ; CHECK-NEXT: ret
1397 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1398 %3 = icmp ugt <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29>
1399 %4 = sext <4 x i1> %3 to <4 x i32>
1400 ret <4 x i32> %4
1401 }
1403 define <4 x i32> @ult_30_v4i32(<4 x i32> %0) {
1404 ; CHECK-LABEL: ult_30_v4i32:
1405 ; CHECK: // %bb.0:
1406 ; CHECK-NEXT: cnt v0.16b, v0.16b
1407 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1408 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1409 ; CHECK-NEXT: movi v1.4s, #30
1410 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1411 ; CHECK-NEXT: ret
1412 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1413 %3 = icmp ult <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
1414 %4 = sext <4 x i1> %3 to <4 x i32>
1415 ret <4 x i32> %4
1416 }
1418 define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) {
1419 ; CHECK-LABEL: ugt_30_v4i32:
1420 ; CHECK: // %bb.0:
1421 ; CHECK-NEXT: cnt v0.16b, v0.16b
1422 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1423 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1424 ; CHECK-NEXT: movi v1.4s, #30
1425 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
1426 ; CHECK-NEXT: ret
1427 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1428 %3 = icmp ugt <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
1429 %4 = sext <4 x i1> %3 to <4 x i32>
1430 ret <4 x i32> %4
1431 }
1433 define <4 x i32> @ult_31_v4i32(<4 x i32> %0) {
1434 ; CHECK-LABEL: ult_31_v4i32:
1435 ; CHECK: // %bb.0:
1436 ; CHECK-NEXT: cnt v0.16b, v0.16b
1437 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1438 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1439 ; CHECK-NEXT: movi v1.4s, #31
1440 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
1441 ; CHECK-NEXT: ret
1442 %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
1443 %3 = icmp ult <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31>
1444 %4 = sext <4 x i1> %3 to <4 x i32>
1445 ret <4 x i32> %4
1446 }
1448 define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
1449 ; CHECK-LABEL: ugt_1_v2i64:
1450 ; CHECK: // %bb.0:
1451 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
1452 ; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
1453 ; CHECK-NEXT: cmtst v0.2d, v0.2d, v1.2d
1454 ; CHECK-NEXT: ret
1455 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1456 %3 = icmp ugt <2 x i64> %2, <i64 1, i64 1>
1457 %4 = sext <2 x i1> %3 to <2 x i64>
1458 ret <2 x i64> %4
1459 }
1461 define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
1462 ; CHECK-LABEL: ult_2_v2i64:
1463 ; CHECK: // %bb.0:
1464 ; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
1465 ; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
1466 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
1467 ; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
1468 ; CHECK-NEXT: ret
1469 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1470 %3 = icmp ult <2 x i64> %2, <i64 2, i64 2>
1471 %4 = sext <2 x i1> %3 to <2 x i64>
1472 ret <2 x i64> %4
1473 }
1475 define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
1476 ; CHECK-LABEL: ugt_2_v2i64:
1477 ; CHECK: // %bb.0:
1478 ; CHECK-NEXT: cnt v0.16b, v0.16b
1479 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1480 ; CHECK-NEXT: mov w8, #2
1481 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1482 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1483 ; CHECK-NEXT: dup v1.2d, x8
1484 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1485 ; CHECK-NEXT: ret
1486 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1487 %3 = icmp ugt <2 x i64> %2, <i64 2, i64 2>
1488 %4 = sext <2 x i1> %3 to <2 x i64>
1489 ret <2 x i64> %4
1490 }
1492 define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
1493 ; CHECK-LABEL: ult_3_v2i64:
1494 ; CHECK: // %bb.0:
1495 ; CHECK-NEXT: cnt v0.16b, v0.16b
1496 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1497 ; CHECK-NEXT: mov w8, #3
1498 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1499 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1500 ; CHECK-NEXT: dup v1.2d, x8
1501 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1502 ; CHECK-NEXT: ret
1503 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1504 %3 = icmp ult <2 x i64> %2, <i64 3, i64 3>
1505 %4 = sext <2 x i1> %3 to <2 x i64>
1506 ret <2 x i64> %4
1507 }
1509 define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
1510 ; CHECK-LABEL: ugt_3_v2i64:
1511 ; CHECK: // %bb.0:
1512 ; CHECK-NEXT: cnt v0.16b, v0.16b
1513 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1514 ; CHECK-NEXT: mov w8, #3
1515 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1516 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1517 ; CHECK-NEXT: dup v1.2d, x8
1518 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1519 ; CHECK-NEXT: ret
1520 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1521 %3 = icmp ugt <2 x i64> %2, <i64 3, i64 3>
1522 %4 = sext <2 x i1> %3 to <2 x i64>
1523 ret <2 x i64> %4
1524 }
1526 define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
1527 ; CHECK-LABEL: ult_4_v2i64:
1528 ; CHECK: // %bb.0:
1529 ; CHECK-NEXT: cnt v0.16b, v0.16b
1530 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1531 ; CHECK-NEXT: mov w8, #4
1532 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1533 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1534 ; CHECK-NEXT: dup v1.2d, x8
1535 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1536 ; CHECK-NEXT: ret
1537 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1538 %3 = icmp ult <2 x i64> %2, <i64 4, i64 4>
1539 %4 = sext <2 x i1> %3 to <2 x i64>
1540 ret <2 x i64> %4
1541 }
1543 define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
1544 ; CHECK-LABEL: ugt_4_v2i64:
1545 ; CHECK: // %bb.0:
1546 ; CHECK-NEXT: cnt v0.16b, v0.16b
1547 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1548 ; CHECK-NEXT: mov w8, #4
1549 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1550 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1551 ; CHECK-NEXT: dup v1.2d, x8
1552 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1553 ; CHECK-NEXT: ret
1554 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1555 %3 = icmp ugt <2 x i64> %2, <i64 4, i64 4>
1556 %4 = sext <2 x i1> %3 to <2 x i64>
1557 ret <2 x i64> %4
1558 }
1560 define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
1561 ; CHECK-LABEL: ult_5_v2i64:
1562 ; CHECK: // %bb.0:
1563 ; CHECK-NEXT: cnt v0.16b, v0.16b
1564 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1565 ; CHECK-NEXT: mov w8, #5
1566 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1567 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1568 ; CHECK-NEXT: dup v1.2d, x8
1569 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1570 ; CHECK-NEXT: ret
1571 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1572 %3 = icmp ult <2 x i64> %2, <i64 5, i64 5>
1573 %4 = sext <2 x i1> %3 to <2 x i64>
1574 ret <2 x i64> %4
1575 }
1577 define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
1578 ; CHECK-LABEL: ugt_5_v2i64:
1579 ; CHECK: // %bb.0:
1580 ; CHECK-NEXT: cnt v0.16b, v0.16b
1581 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1582 ; CHECK-NEXT: mov w8, #5
1583 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1584 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1585 ; CHECK-NEXT: dup v1.2d, x8
1586 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1587 ; CHECK-NEXT: ret
1588 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1589 %3 = icmp ugt <2 x i64> %2, <i64 5, i64 5>
1590 %4 = sext <2 x i1> %3 to <2 x i64>
1591 ret <2 x i64> %4
1592 }
1594 define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
1595 ; CHECK-LABEL: ult_6_v2i64:
1596 ; CHECK: // %bb.0:
1597 ; CHECK-NEXT: cnt v0.16b, v0.16b
1598 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1599 ; CHECK-NEXT: mov w8, #6
1600 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1601 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1602 ; CHECK-NEXT: dup v1.2d, x8
1603 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1604 ; CHECK-NEXT: ret
1605 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1606 %3 = icmp ult <2 x i64> %2, <i64 6, i64 6>
1607 %4 = sext <2 x i1> %3 to <2 x i64>
1608 ret <2 x i64> %4
1609 }
1611 define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
1612 ; CHECK-LABEL: ugt_6_v2i64:
1613 ; CHECK: // %bb.0:
1614 ; CHECK-NEXT: cnt v0.16b, v0.16b
1615 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1616 ; CHECK-NEXT: mov w8, #6
1617 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1618 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1619 ; CHECK-NEXT: dup v1.2d, x8
1620 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1621 ; CHECK-NEXT: ret
1622 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1623 %3 = icmp ugt <2 x i64> %2, <i64 6, i64 6>
1624 %4 = sext <2 x i1> %3 to <2 x i64>
1625 ret <2 x i64> %4
1626 }
1628 define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
1629 ; CHECK-LABEL: ult_7_v2i64:
1630 ; CHECK: // %bb.0:
1631 ; CHECK-NEXT: cnt v0.16b, v0.16b
1632 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1633 ; CHECK-NEXT: mov w8, #7
1634 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1635 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1636 ; CHECK-NEXT: dup v1.2d, x8
1637 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1638 ; CHECK-NEXT: ret
1639 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1640 %3 = icmp ult <2 x i64> %2, <i64 7, i64 7>
1641 %4 = sext <2 x i1> %3 to <2 x i64>
1642 ret <2 x i64> %4
1643 }
1645 define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
1646 ; CHECK-LABEL: ugt_7_v2i64:
1647 ; CHECK: // %bb.0:
1648 ; CHECK-NEXT: cnt v0.16b, v0.16b
1649 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1650 ; CHECK-NEXT: mov w8, #7
1651 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1652 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1653 ; CHECK-NEXT: dup v1.2d, x8
1654 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1655 ; CHECK-NEXT: ret
1656 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1657 %3 = icmp ugt <2 x i64> %2, <i64 7, i64 7>
1658 %4 = sext <2 x i1> %3 to <2 x i64>
1659 ret <2 x i64> %4
1660 }
1662 define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
1663 ; CHECK-LABEL: ult_8_v2i64:
1664 ; CHECK: // %bb.0:
1665 ; CHECK-NEXT: cnt v0.16b, v0.16b
1666 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1667 ; CHECK-NEXT: mov w8, #8
1668 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1669 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1670 ; CHECK-NEXT: dup v1.2d, x8
1671 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1672 ; CHECK-NEXT: ret
1673 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1674 %3 = icmp ult <2 x i64> %2, <i64 8, i64 8>
1675 %4 = sext <2 x i1> %3 to <2 x i64>
1676 ret <2 x i64> %4
1677 }
1679 define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
1680 ; CHECK-LABEL: ugt_8_v2i64:
1681 ; CHECK: // %bb.0:
1682 ; CHECK-NEXT: cnt v0.16b, v0.16b
1683 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1684 ; CHECK-NEXT: mov w8, #8
1685 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1686 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1687 ; CHECK-NEXT: dup v1.2d, x8
1688 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1689 ; CHECK-NEXT: ret
1690 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1691 %3 = icmp ugt <2 x i64> %2, <i64 8, i64 8>
1692 %4 = sext <2 x i1> %3 to <2 x i64>
1693 ret <2 x i64> %4
1694 }
1696 define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
1697 ; CHECK-LABEL: ult_9_v2i64:
1698 ; CHECK: // %bb.0:
1699 ; CHECK-NEXT: cnt v0.16b, v0.16b
1700 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1701 ; CHECK-NEXT: mov w8, #9
1702 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1703 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1704 ; CHECK-NEXT: dup v1.2d, x8
1705 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1706 ; CHECK-NEXT: ret
1707 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1708 %3 = icmp ult <2 x i64> %2, <i64 9, i64 9>
1709 %4 = sext <2 x i1> %3 to <2 x i64>
1710 ret <2 x i64> %4
1711 }
1713 define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
1714 ; CHECK-LABEL: ugt_9_v2i64:
1715 ; CHECK: // %bb.0:
1716 ; CHECK-NEXT: cnt v0.16b, v0.16b
1717 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1718 ; CHECK-NEXT: mov w8, #9
1719 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1720 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1721 ; CHECK-NEXT: dup v1.2d, x8
1722 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1723 ; CHECK-NEXT: ret
1724 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1725 %3 = icmp ugt <2 x i64> %2, <i64 9, i64 9>
1726 %4 = sext <2 x i1> %3 to <2 x i64>
1727 ret <2 x i64> %4
1728 }
1730 define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
1731 ; CHECK-LABEL: ult_10_v2i64:
1732 ; CHECK: // %bb.0:
1733 ; CHECK-NEXT: cnt v0.16b, v0.16b
1734 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1735 ; CHECK-NEXT: mov w8, #10
1736 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1737 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1738 ; CHECK-NEXT: dup v1.2d, x8
1739 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1740 ; CHECK-NEXT: ret
1741 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1742 %3 = icmp ult <2 x i64> %2, <i64 10, i64 10>
1743 %4 = sext <2 x i1> %3 to <2 x i64>
1744 ret <2 x i64> %4
1745 }
1747 define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
1748 ; CHECK-LABEL: ugt_10_v2i64:
1749 ; CHECK: // %bb.0:
1750 ; CHECK-NEXT: cnt v0.16b, v0.16b
1751 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1752 ; CHECK-NEXT: mov w8, #10
1753 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1754 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1755 ; CHECK-NEXT: dup v1.2d, x8
1756 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1757 ; CHECK-NEXT: ret
1758 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1759 %3 = icmp ugt <2 x i64> %2, <i64 10, i64 10>
1760 %4 = sext <2 x i1> %3 to <2 x i64>
1761 ret <2 x i64> %4
1762 }
1764 define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
1765 ; CHECK-LABEL: ult_11_v2i64:
1766 ; CHECK: // %bb.0:
1767 ; CHECK-NEXT: cnt v0.16b, v0.16b
1768 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1769 ; CHECK-NEXT: mov w8, #11
1770 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1771 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1772 ; CHECK-NEXT: dup v1.2d, x8
1773 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1774 ; CHECK-NEXT: ret
1775 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1776 %3 = icmp ult <2 x i64> %2, <i64 11, i64 11>
1777 %4 = sext <2 x i1> %3 to <2 x i64>
1778 ret <2 x i64> %4
1779 }
1781 define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
1782 ; CHECK-LABEL: ugt_11_v2i64:
1783 ; CHECK: // %bb.0:
1784 ; CHECK-NEXT: cnt v0.16b, v0.16b
1785 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1786 ; CHECK-NEXT: mov w8, #11
1787 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1788 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1789 ; CHECK-NEXT: dup v1.2d, x8
1790 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1791 ; CHECK-NEXT: ret
1792 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1793 %3 = icmp ugt <2 x i64> %2, <i64 11, i64 11>
1794 %4 = sext <2 x i1> %3 to <2 x i64>
1795 ret <2 x i64> %4
1796 }
1798 define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
1799 ; CHECK-LABEL: ult_12_v2i64:
1800 ; CHECK: // %bb.0:
1801 ; CHECK-NEXT: cnt v0.16b, v0.16b
1802 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1803 ; CHECK-NEXT: mov w8, #12
1804 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1805 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1806 ; CHECK-NEXT: dup v1.2d, x8
1807 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1808 ; CHECK-NEXT: ret
1809 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1810 %3 = icmp ult <2 x i64> %2, <i64 12, i64 12>
1811 %4 = sext <2 x i1> %3 to <2 x i64>
1812 ret <2 x i64> %4
1813 }
1815 define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
1816 ; CHECK-LABEL: ugt_12_v2i64:
1817 ; CHECK: // %bb.0:
1818 ; CHECK-NEXT: cnt v0.16b, v0.16b
1819 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1820 ; CHECK-NEXT: mov w8, #12
1821 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1822 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1823 ; CHECK-NEXT: dup v1.2d, x8
1824 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1825 ; CHECK-NEXT: ret
1826 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1827 %3 = icmp ugt <2 x i64> %2, <i64 12, i64 12>
1828 %4 = sext <2 x i1> %3 to <2 x i64>
1829 ret <2 x i64> %4
1830 }
1832 define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
1833 ; CHECK-LABEL: ult_13_v2i64:
1834 ; CHECK: // %bb.0:
1835 ; CHECK-NEXT: cnt v0.16b, v0.16b
1836 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1837 ; CHECK-NEXT: mov w8, #13
1838 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1839 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1840 ; CHECK-NEXT: dup v1.2d, x8
1841 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1842 ; CHECK-NEXT: ret
1843 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1844 %3 = icmp ult <2 x i64> %2, <i64 13, i64 13>
1845 %4 = sext <2 x i1> %3 to <2 x i64>
1846 ret <2 x i64> %4
1847 }
1849 define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
1850 ; CHECK-LABEL: ugt_13_v2i64:
1851 ; CHECK: // %bb.0:
1852 ; CHECK-NEXT: cnt v0.16b, v0.16b
1853 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1854 ; CHECK-NEXT: mov w8, #13
1855 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1856 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1857 ; CHECK-NEXT: dup v1.2d, x8
1858 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1859 ; CHECK-NEXT: ret
1860 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1861 %3 = icmp ugt <2 x i64> %2, <i64 13, i64 13>
1862 %4 = sext <2 x i1> %3 to <2 x i64>
1863 ret <2 x i64> %4
1864 }
1866 define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
1867 ; CHECK-LABEL: ult_14_v2i64:
1868 ; CHECK: // %bb.0:
1869 ; CHECK-NEXT: cnt v0.16b, v0.16b
1870 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1871 ; CHECK-NEXT: mov w8, #14
1872 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1873 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1874 ; CHECK-NEXT: dup v1.2d, x8
1875 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1876 ; CHECK-NEXT: ret
1877 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1878 %3 = icmp ult <2 x i64> %2, <i64 14, i64 14>
1879 %4 = sext <2 x i1> %3 to <2 x i64>
1880 ret <2 x i64> %4
1881 }
1883 define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
1884 ; CHECK-LABEL: ugt_14_v2i64:
1885 ; CHECK: // %bb.0:
1886 ; CHECK-NEXT: cnt v0.16b, v0.16b
1887 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1888 ; CHECK-NEXT: mov w8, #14
1889 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1890 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1891 ; CHECK-NEXT: dup v1.2d, x8
1892 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1893 ; CHECK-NEXT: ret
1894 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1895 %3 = icmp ugt <2 x i64> %2, <i64 14, i64 14>
1896 %4 = sext <2 x i1> %3 to <2 x i64>
1897 ret <2 x i64> %4
1898 }
1900 define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
1901 ; CHECK-LABEL: ult_15_v2i64:
1902 ; CHECK: // %bb.0:
1903 ; CHECK-NEXT: cnt v0.16b, v0.16b
1904 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1905 ; CHECK-NEXT: mov w8, #15
1906 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1907 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1908 ; CHECK-NEXT: dup v1.2d, x8
1909 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1910 ; CHECK-NEXT: ret
1911 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1912 %3 = icmp ult <2 x i64> %2, <i64 15, i64 15>
1913 %4 = sext <2 x i1> %3 to <2 x i64>
1914 ret <2 x i64> %4
1915 }
1917 define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
1918 ; CHECK-LABEL: ugt_15_v2i64:
1919 ; CHECK: // %bb.0:
1920 ; CHECK-NEXT: cnt v0.16b, v0.16b
1921 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1922 ; CHECK-NEXT: mov w8, #15
1923 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1924 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1925 ; CHECK-NEXT: dup v1.2d, x8
1926 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1927 ; CHECK-NEXT: ret
1928 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1929 %3 = icmp ugt <2 x i64> %2, <i64 15, i64 15>
1930 %4 = sext <2 x i1> %3 to <2 x i64>
1931 ret <2 x i64> %4
1932 }
1934 define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
1935 ; CHECK-LABEL: ult_16_v2i64:
1936 ; CHECK: // %bb.0:
1937 ; CHECK-NEXT: cnt v0.16b, v0.16b
1938 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1939 ; CHECK-NEXT: mov w8, #16
1940 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1941 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1942 ; CHECK-NEXT: dup v1.2d, x8
1943 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1944 ; CHECK-NEXT: ret
1945 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1946 %3 = icmp ult <2 x i64> %2, <i64 16, i64 16>
1947 %4 = sext <2 x i1> %3 to <2 x i64>
1948 ret <2 x i64> %4
1949 }
1951 define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
1952 ; CHECK-LABEL: ugt_16_v2i64:
1953 ; CHECK: // %bb.0:
1954 ; CHECK-NEXT: cnt v0.16b, v0.16b
1955 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1956 ; CHECK-NEXT: mov w8, #16
1957 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1958 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1959 ; CHECK-NEXT: dup v1.2d, x8
1960 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1961 ; CHECK-NEXT: ret
1962 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1963 %3 = icmp ugt <2 x i64> %2, <i64 16, i64 16>
1964 %4 = sext <2 x i1> %3 to <2 x i64>
1965 ret <2 x i64> %4
1966 }
1968 define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
1969 ; CHECK-LABEL: ult_17_v2i64:
1970 ; CHECK: // %bb.0:
1971 ; CHECK-NEXT: cnt v0.16b, v0.16b
1972 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1973 ; CHECK-NEXT: mov w8, #17
1974 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1975 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1976 ; CHECK-NEXT: dup v1.2d, x8
1977 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
1978 ; CHECK-NEXT: ret
1979 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1980 %3 = icmp ult <2 x i64> %2, <i64 17, i64 17>
1981 %4 = sext <2 x i1> %3 to <2 x i64>
1982 ret <2 x i64> %4
1983 }
1985 define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
1986 ; CHECK-LABEL: ugt_17_v2i64:
1987 ; CHECK: // %bb.0:
1988 ; CHECK-NEXT: cnt v0.16b, v0.16b
1989 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
1990 ; CHECK-NEXT: mov w8, #17
1991 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
1992 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
1993 ; CHECK-NEXT: dup v1.2d, x8
1994 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
1995 ; CHECK-NEXT: ret
1996 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
1997 %3 = icmp ugt <2 x i64> %2, <i64 17, i64 17>
1998 %4 = sext <2 x i1> %3 to <2 x i64>
1999 ret <2 x i64> %4
2000 }
2002 define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
2003 ; CHECK-LABEL: ult_18_v2i64:
2004 ; CHECK: // %bb.0:
2005 ; CHECK-NEXT: cnt v0.16b, v0.16b
2006 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2007 ; CHECK-NEXT: mov w8, #18
2008 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2009 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2010 ; CHECK-NEXT: dup v1.2d, x8
2011 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2012 ; CHECK-NEXT: ret
2013 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2014 %3 = icmp ult <2 x i64> %2, <i64 18, i64 18>
2015 %4 = sext <2 x i1> %3 to <2 x i64>
2016 ret <2 x i64> %4
2017 }
2019 define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
2020 ; CHECK-LABEL: ugt_18_v2i64:
2021 ; CHECK: // %bb.0:
2022 ; CHECK-NEXT: cnt v0.16b, v0.16b
2023 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2024 ; CHECK-NEXT: mov w8, #18
2025 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2026 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2027 ; CHECK-NEXT: dup v1.2d, x8
2028 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2029 ; CHECK-NEXT: ret
2030 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2031 %3 = icmp ugt <2 x i64> %2, <i64 18, i64 18>
2032 %4 = sext <2 x i1> %3 to <2 x i64>
2033 ret <2 x i64> %4
2034 }
2036 define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
2037 ; CHECK-LABEL: ult_19_v2i64:
2038 ; CHECK: // %bb.0:
2039 ; CHECK-NEXT: cnt v0.16b, v0.16b
2040 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2041 ; CHECK-NEXT: mov w8, #19
2042 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2043 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2044 ; CHECK-NEXT: dup v1.2d, x8
2045 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2046 ; CHECK-NEXT: ret
2047 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2048 %3 = icmp ult <2 x i64> %2, <i64 19, i64 19>
2049 %4 = sext <2 x i1> %3 to <2 x i64>
2050 ret <2 x i64> %4
2051 }
2053 define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
2054 ; CHECK-LABEL: ugt_19_v2i64:
2055 ; CHECK: // %bb.0:
2056 ; CHECK-NEXT: cnt v0.16b, v0.16b
2057 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2058 ; CHECK-NEXT: mov w8, #19
2059 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2060 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2061 ; CHECK-NEXT: dup v1.2d, x8
2062 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2063 ; CHECK-NEXT: ret
2064 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2065 %3 = icmp ugt <2 x i64> %2, <i64 19, i64 19>
2066 %4 = sext <2 x i1> %3 to <2 x i64>
2067 ret <2 x i64> %4
2068 }
2070 define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
2071 ; CHECK-LABEL: ult_20_v2i64:
2072 ; CHECK: // %bb.0:
2073 ; CHECK-NEXT: cnt v0.16b, v0.16b
2074 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2075 ; CHECK-NEXT: mov w8, #20
2076 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2077 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2078 ; CHECK-NEXT: dup v1.2d, x8
2079 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2080 ; CHECK-NEXT: ret
2081 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2082 %3 = icmp ult <2 x i64> %2, <i64 20, i64 20>
2083 %4 = sext <2 x i1> %3 to <2 x i64>
2084 ret <2 x i64> %4
2085 }
2087 define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
2088 ; CHECK-LABEL: ugt_20_v2i64:
2089 ; CHECK: // %bb.0:
2090 ; CHECK-NEXT: cnt v0.16b, v0.16b
2091 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2092 ; CHECK-NEXT: mov w8, #20
2093 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2094 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2095 ; CHECK-NEXT: dup v1.2d, x8
2096 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2097 ; CHECK-NEXT: ret
2098 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2099 %3 = icmp ugt <2 x i64> %2, <i64 20, i64 20>
2100 %4 = sext <2 x i1> %3 to <2 x i64>
2101 ret <2 x i64> %4
2102 }
2104 define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
2105 ; CHECK-LABEL: ult_21_v2i64:
2106 ; CHECK: // %bb.0:
2107 ; CHECK-NEXT: cnt v0.16b, v0.16b
2108 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2109 ; CHECK-NEXT: mov w8, #21
2110 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2111 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2112 ; CHECK-NEXT: dup v1.2d, x8
2113 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2114 ; CHECK-NEXT: ret
2115 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2116 %3 = icmp ult <2 x i64> %2, <i64 21, i64 21>
2117 %4 = sext <2 x i1> %3 to <2 x i64>
2118 ret <2 x i64> %4
2119 }
2121 define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
2122 ; CHECK-LABEL: ugt_21_v2i64:
2123 ; CHECK: // %bb.0:
2124 ; CHECK-NEXT: cnt v0.16b, v0.16b
2125 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2126 ; CHECK-NEXT: mov w8, #21
2127 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2128 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2129 ; CHECK-NEXT: dup v1.2d, x8
2130 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2131 ; CHECK-NEXT: ret
2132 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2133 %3 = icmp ugt <2 x i64> %2, <i64 21, i64 21>
2134 %4 = sext <2 x i1> %3 to <2 x i64>
2135 ret <2 x i64> %4
2136 }
2138 define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
2139 ; CHECK-LABEL: ult_22_v2i64:
2140 ; CHECK: // %bb.0:
2141 ; CHECK-NEXT: cnt v0.16b, v0.16b
2142 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2143 ; CHECK-NEXT: mov w8, #22
2144 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2145 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2146 ; CHECK-NEXT: dup v1.2d, x8
2147 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2148 ; CHECK-NEXT: ret
2149 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2150 %3 = icmp ult <2 x i64> %2, <i64 22, i64 22>
2151 %4 = sext <2 x i1> %3 to <2 x i64>
2152 ret <2 x i64> %4
2153 }
2155 define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
2156 ; CHECK-LABEL: ugt_22_v2i64:
2157 ; CHECK: // %bb.0:
2158 ; CHECK-NEXT: cnt v0.16b, v0.16b
2159 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2160 ; CHECK-NEXT: mov w8, #22
2161 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2162 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2163 ; CHECK-NEXT: dup v1.2d, x8
2164 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2165 ; CHECK-NEXT: ret
2166 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2167 %3 = icmp ugt <2 x i64> %2, <i64 22, i64 22>
2168 %4 = sext <2 x i1> %3 to <2 x i64>
2169 ret <2 x i64> %4
2170 }
2172 define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
2173 ; CHECK-LABEL: ult_23_v2i64:
2174 ; CHECK: // %bb.0:
2175 ; CHECK-NEXT: cnt v0.16b, v0.16b
2176 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2177 ; CHECK-NEXT: mov w8, #23
2178 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2179 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2180 ; CHECK-NEXT: dup v1.2d, x8
2181 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2182 ; CHECK-NEXT: ret
2183 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2184 %3 = icmp ult <2 x i64> %2, <i64 23, i64 23>
2185 %4 = sext <2 x i1> %3 to <2 x i64>
2186 ret <2 x i64> %4
2187 }
2189 define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
2190 ; CHECK-LABEL: ugt_23_v2i64:
2191 ; CHECK: // %bb.0:
2192 ; CHECK-NEXT: cnt v0.16b, v0.16b
2193 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2194 ; CHECK-NEXT: mov w8, #23
2195 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2196 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2197 ; CHECK-NEXT: dup v1.2d, x8
2198 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2199 ; CHECK-NEXT: ret
2200 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2201 %3 = icmp ugt <2 x i64> %2, <i64 23, i64 23>
2202 %4 = sext <2 x i1> %3 to <2 x i64>
2203 ret <2 x i64> %4
2204 }
2206 define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
2207 ; CHECK-LABEL: ult_24_v2i64:
2208 ; CHECK: // %bb.0:
2209 ; CHECK-NEXT: cnt v0.16b, v0.16b
2210 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2211 ; CHECK-NEXT: mov w8, #24
2212 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2213 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2214 ; CHECK-NEXT: dup v1.2d, x8
2215 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2216 ; CHECK-NEXT: ret
2217 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2218 %3 = icmp ult <2 x i64> %2, <i64 24, i64 24>
2219 %4 = sext <2 x i1> %3 to <2 x i64>
2220 ret <2 x i64> %4
2221 }
2223 define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
2224 ; CHECK-LABEL: ugt_24_v2i64:
2225 ; CHECK: // %bb.0:
2226 ; CHECK-NEXT: cnt v0.16b, v0.16b
2227 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2228 ; CHECK-NEXT: mov w8, #24
2229 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2230 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2231 ; CHECK-NEXT: dup v1.2d, x8
2232 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2233 ; CHECK-NEXT: ret
2234 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2235 %3 = icmp ugt <2 x i64> %2, <i64 24, i64 24>
2236 %4 = sext <2 x i1> %3 to <2 x i64>
2237 ret <2 x i64> %4
2238 }
2240 define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
2241 ; CHECK-LABEL: ult_25_v2i64:
2242 ; CHECK: // %bb.0:
2243 ; CHECK-NEXT: cnt v0.16b, v0.16b
2244 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2245 ; CHECK-NEXT: mov w8, #25
2246 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2247 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2248 ; CHECK-NEXT: dup v1.2d, x8
2249 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2250 ; CHECK-NEXT: ret
2251 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2252 %3 = icmp ult <2 x i64> %2, <i64 25, i64 25>
2253 %4 = sext <2 x i1> %3 to <2 x i64>
2254 ret <2 x i64> %4
2255 }
2257 define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
2258 ; CHECK-LABEL: ugt_25_v2i64:
2259 ; CHECK: // %bb.0:
2260 ; CHECK-NEXT: cnt v0.16b, v0.16b
2261 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2262 ; CHECK-NEXT: mov w8, #25
2263 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2264 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2265 ; CHECK-NEXT: dup v1.2d, x8
2266 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2267 ; CHECK-NEXT: ret
2268 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2269 %3 = icmp ugt <2 x i64> %2, <i64 25, i64 25>
2270 %4 = sext <2 x i1> %3 to <2 x i64>
2271 ret <2 x i64> %4
2272 }
2274 define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
2275 ; CHECK-LABEL: ult_26_v2i64:
2276 ; CHECK: // %bb.0:
2277 ; CHECK-NEXT: cnt v0.16b, v0.16b
2278 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2279 ; CHECK-NEXT: mov w8, #26
2280 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2281 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2282 ; CHECK-NEXT: dup v1.2d, x8
2283 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2284 ; CHECK-NEXT: ret
2285 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2286 %3 = icmp ult <2 x i64> %2, <i64 26, i64 26>
2287 %4 = sext <2 x i1> %3 to <2 x i64>
2288 ret <2 x i64> %4
2289 }
2291 define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
2292 ; CHECK-LABEL: ugt_26_v2i64:
2293 ; CHECK: // %bb.0:
2294 ; CHECK-NEXT: cnt v0.16b, v0.16b
2295 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2296 ; CHECK-NEXT: mov w8, #26
2297 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2298 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2299 ; CHECK-NEXT: dup v1.2d, x8
2300 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2301 ; CHECK-NEXT: ret
2302 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2303 %3 = icmp ugt <2 x i64> %2, <i64 26, i64 26>
2304 %4 = sext <2 x i1> %3 to <2 x i64>
2305 ret <2 x i64> %4
2306 }
2308 define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
2309 ; CHECK-LABEL: ult_27_v2i64:
2310 ; CHECK: // %bb.0:
2311 ; CHECK-NEXT: cnt v0.16b, v0.16b
2312 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2313 ; CHECK-NEXT: mov w8, #27
2314 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2315 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2316 ; CHECK-NEXT: dup v1.2d, x8
2317 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2318 ; CHECK-NEXT: ret
2319 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2320 %3 = icmp ult <2 x i64> %2, <i64 27, i64 27>
2321 %4 = sext <2 x i1> %3 to <2 x i64>
2322 ret <2 x i64> %4
2323 }
2325 define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
2326 ; CHECK-LABEL: ugt_27_v2i64:
2327 ; CHECK: // %bb.0:
2328 ; CHECK-NEXT: cnt v0.16b, v0.16b
2329 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2330 ; CHECK-NEXT: mov w8, #27
2331 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2332 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2333 ; CHECK-NEXT: dup v1.2d, x8
2334 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2335 ; CHECK-NEXT: ret
2336 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2337 %3 = icmp ugt <2 x i64> %2, <i64 27, i64 27>
2338 %4 = sext <2 x i1> %3 to <2 x i64>
2339 ret <2 x i64> %4
2340 }
2342 define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
2343 ; CHECK-LABEL: ult_28_v2i64:
2344 ; CHECK: // %bb.0:
2345 ; CHECK-NEXT: cnt v0.16b, v0.16b
2346 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2347 ; CHECK-NEXT: mov w8, #28
2348 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2349 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2350 ; CHECK-NEXT: dup v1.2d, x8
2351 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2352 ; CHECK-NEXT: ret
2353 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2354 %3 = icmp ult <2 x i64> %2, <i64 28, i64 28>
2355 %4 = sext <2 x i1> %3 to <2 x i64>
2356 ret <2 x i64> %4
2357 }
2359 define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
2360 ; CHECK-LABEL: ugt_28_v2i64:
2361 ; CHECK: // %bb.0:
2362 ; CHECK-NEXT: cnt v0.16b, v0.16b
2363 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2364 ; CHECK-NEXT: mov w8, #28
2365 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2366 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2367 ; CHECK-NEXT: dup v1.2d, x8
2368 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2369 ; CHECK-NEXT: ret
2370 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2371 %3 = icmp ugt <2 x i64> %2, <i64 28, i64 28>
2372 %4 = sext <2 x i1> %3 to <2 x i64>
2373 ret <2 x i64> %4
2374 }
2376 define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
2377 ; CHECK-LABEL: ult_29_v2i64:
2378 ; CHECK: // %bb.0:
2379 ; CHECK-NEXT: cnt v0.16b, v0.16b
2380 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2381 ; CHECK-NEXT: mov w8, #29
2382 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2383 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2384 ; CHECK-NEXT: dup v1.2d, x8
2385 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2386 ; CHECK-NEXT: ret
2387 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2388 %3 = icmp ult <2 x i64> %2, <i64 29, i64 29>
2389 %4 = sext <2 x i1> %3 to <2 x i64>
2390 ret <2 x i64> %4
2391 }
2393 define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
2394 ; CHECK-LABEL: ugt_29_v2i64:
2395 ; CHECK: // %bb.0:
2396 ; CHECK-NEXT: cnt v0.16b, v0.16b
2397 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2398 ; CHECK-NEXT: mov w8, #29
2399 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2400 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2401 ; CHECK-NEXT: dup v1.2d, x8
2402 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2403 ; CHECK-NEXT: ret
2404 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2405 %3 = icmp ugt <2 x i64> %2, <i64 29, i64 29>
2406 %4 = sext <2 x i1> %3 to <2 x i64>
2407 ret <2 x i64> %4
2408 }
2410 define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
2411 ; CHECK-LABEL: ult_30_v2i64:
2412 ; CHECK: // %bb.0:
2413 ; CHECK-NEXT: cnt v0.16b, v0.16b
2414 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2415 ; CHECK-NEXT: mov w8, #30
2416 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2417 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2418 ; CHECK-NEXT: dup v1.2d, x8
2419 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2420 ; CHECK-NEXT: ret
2421 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2422 %3 = icmp ult <2 x i64> %2, <i64 30, i64 30>
2423 %4 = sext <2 x i1> %3 to <2 x i64>
2424 ret <2 x i64> %4
2425 }
2427 define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
2428 ; CHECK-LABEL: ugt_30_v2i64:
2429 ; CHECK: // %bb.0:
2430 ; CHECK-NEXT: cnt v0.16b, v0.16b
2431 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2432 ; CHECK-NEXT: mov w8, #30
2433 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2434 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2435 ; CHECK-NEXT: dup v1.2d, x8
2436 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2437 ; CHECK-NEXT: ret
2438 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2439 %3 = icmp ugt <2 x i64> %2, <i64 30, i64 30>
2440 %4 = sext <2 x i1> %3 to <2 x i64>
2441 ret <2 x i64> %4
2442 }
2444 define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
2445 ; CHECK-LABEL: ult_31_v2i64:
2446 ; CHECK: // %bb.0:
2447 ; CHECK-NEXT: cnt v0.16b, v0.16b
2448 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2449 ; CHECK-NEXT: mov w8, #31
2450 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2451 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2452 ; CHECK-NEXT: dup v1.2d, x8
2453 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2454 ; CHECK-NEXT: ret
2455 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2456 %3 = icmp ult <2 x i64> %2, <i64 31, i64 31>
2457 %4 = sext <2 x i1> %3 to <2 x i64>
2458 ret <2 x i64> %4
2459 }
2461 define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
2462 ; CHECK-LABEL: ugt_31_v2i64:
2463 ; CHECK: // %bb.0:
2464 ; CHECK-NEXT: cnt v0.16b, v0.16b
2465 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2466 ; CHECK-NEXT: mov w8, #31
2467 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2468 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2469 ; CHECK-NEXT: dup v1.2d, x8
2470 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2471 ; CHECK-NEXT: ret
2472 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2473 %3 = icmp ugt <2 x i64> %2, <i64 31, i64 31>
2474 %4 = sext <2 x i1> %3 to <2 x i64>
2475 ret <2 x i64> %4
2476 }
2478 define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
2479 ; CHECK-LABEL: ult_32_v2i64:
2480 ; CHECK: // %bb.0:
2481 ; CHECK-NEXT: cnt v0.16b, v0.16b
2482 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2483 ; CHECK-NEXT: mov w8, #32
2484 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2485 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2486 ; CHECK-NEXT: dup v1.2d, x8
2487 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2488 ; CHECK-NEXT: ret
2489 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2490 %3 = icmp ult <2 x i64> %2, <i64 32, i64 32>
2491 %4 = sext <2 x i1> %3 to <2 x i64>
2492 ret <2 x i64> %4
2493 }
2495 define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
2496 ; CHECK-LABEL: ugt_32_v2i64:
2497 ; CHECK: // %bb.0:
2498 ; CHECK-NEXT: cnt v0.16b, v0.16b
2499 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2500 ; CHECK-NEXT: mov w8, #32
2501 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2502 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2503 ; CHECK-NEXT: dup v1.2d, x8
2504 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2505 ; CHECK-NEXT: ret
2506 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2507 %3 = icmp ugt <2 x i64> %2, <i64 32, i64 32>
2508 %4 = sext <2 x i1> %3 to <2 x i64>
2509 ret <2 x i64> %4
2510 }
2512 define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
2513 ; CHECK-LABEL: ult_33_v2i64:
2514 ; CHECK: // %bb.0:
2515 ; CHECK-NEXT: cnt v0.16b, v0.16b
2516 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2517 ; CHECK-NEXT: mov w8, #33
2518 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2519 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2520 ; CHECK-NEXT: dup v1.2d, x8
2521 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2522 ; CHECK-NEXT: ret
2523 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2524 %3 = icmp ult <2 x i64> %2, <i64 33, i64 33>
2525 %4 = sext <2 x i1> %3 to <2 x i64>
2526 ret <2 x i64> %4
2527 }
2529 define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
2530 ; CHECK-LABEL: ugt_33_v2i64:
2531 ; CHECK: // %bb.0:
2532 ; CHECK-NEXT: cnt v0.16b, v0.16b
2533 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2534 ; CHECK-NEXT: mov w8, #33
2535 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2536 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2537 ; CHECK-NEXT: dup v1.2d, x8
2538 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2539 ; CHECK-NEXT: ret
2540 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2541 %3 = icmp ugt <2 x i64> %2, <i64 33, i64 33>
2542 %4 = sext <2 x i1> %3 to <2 x i64>
2543 ret <2 x i64> %4
2544 }
2546 define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
2547 ; CHECK-LABEL: ult_34_v2i64:
2548 ; CHECK: // %bb.0:
2549 ; CHECK-NEXT: cnt v0.16b, v0.16b
2550 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2551 ; CHECK-NEXT: mov w8, #34
2552 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2553 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2554 ; CHECK-NEXT: dup v1.2d, x8
2555 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2556 ; CHECK-NEXT: ret
2557 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2558 %3 = icmp ult <2 x i64> %2, <i64 34, i64 34>
2559 %4 = sext <2 x i1> %3 to <2 x i64>
2560 ret <2 x i64> %4
2561 }
2563 define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
2564 ; CHECK-LABEL: ugt_34_v2i64:
2565 ; CHECK: // %bb.0:
2566 ; CHECK-NEXT: cnt v0.16b, v0.16b
2567 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2568 ; CHECK-NEXT: mov w8, #34
2569 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2570 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2571 ; CHECK-NEXT: dup v1.2d, x8
2572 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2573 ; CHECK-NEXT: ret
2574 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2575 %3 = icmp ugt <2 x i64> %2, <i64 34, i64 34>
2576 %4 = sext <2 x i1> %3 to <2 x i64>
2577 ret <2 x i64> %4
2578 }
2580 define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
2581 ; CHECK-LABEL: ult_35_v2i64:
2582 ; CHECK: // %bb.0:
2583 ; CHECK-NEXT: cnt v0.16b, v0.16b
2584 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2585 ; CHECK-NEXT: mov w8, #35
2586 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2587 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2588 ; CHECK-NEXT: dup v1.2d, x8
2589 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2590 ; CHECK-NEXT: ret
2591 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2592 %3 = icmp ult <2 x i64> %2, <i64 35, i64 35>
2593 %4 = sext <2 x i1> %3 to <2 x i64>
2594 ret <2 x i64> %4
2595 }
2597 define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
2598 ; CHECK-LABEL: ugt_35_v2i64:
2599 ; CHECK: // %bb.0:
2600 ; CHECK-NEXT: cnt v0.16b, v0.16b
2601 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2602 ; CHECK-NEXT: mov w8, #35
2603 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2604 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2605 ; CHECK-NEXT: dup v1.2d, x8
2606 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2607 ; CHECK-NEXT: ret
2608 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2609 %3 = icmp ugt <2 x i64> %2, <i64 35, i64 35>
2610 %4 = sext <2 x i1> %3 to <2 x i64>
2611 ret <2 x i64> %4
2612 }
2614 define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
2615 ; CHECK-LABEL: ult_36_v2i64:
2616 ; CHECK: // %bb.0:
2617 ; CHECK-NEXT: cnt v0.16b, v0.16b
2618 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2619 ; CHECK-NEXT: mov w8, #36
2620 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2621 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2622 ; CHECK-NEXT: dup v1.2d, x8
2623 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2624 ; CHECK-NEXT: ret
2625 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2626 %3 = icmp ult <2 x i64> %2, <i64 36, i64 36>
2627 %4 = sext <2 x i1> %3 to <2 x i64>
2628 ret <2 x i64> %4
2629 }
2631 define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
2632 ; CHECK-LABEL: ugt_36_v2i64:
2633 ; CHECK: // %bb.0:
2634 ; CHECK-NEXT: cnt v0.16b, v0.16b
2635 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2636 ; CHECK-NEXT: mov w8, #36
2637 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2638 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2639 ; CHECK-NEXT: dup v1.2d, x8
2640 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2641 ; CHECK-NEXT: ret
2642 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2643 %3 = icmp ugt <2 x i64> %2, <i64 36, i64 36>
2644 %4 = sext <2 x i1> %3 to <2 x i64>
2645 ret <2 x i64> %4
2646 }
2648 define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
2649 ; CHECK-LABEL: ult_37_v2i64:
2650 ; CHECK: // %bb.0:
2651 ; CHECK-NEXT: cnt v0.16b, v0.16b
2652 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2653 ; CHECK-NEXT: mov w8, #37
2654 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2655 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2656 ; CHECK-NEXT: dup v1.2d, x8
2657 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2658 ; CHECK-NEXT: ret
2659 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2660 %3 = icmp ult <2 x i64> %2, <i64 37, i64 37>
2661 %4 = sext <2 x i1> %3 to <2 x i64>
2662 ret <2 x i64> %4
2663 }
2665 define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
2666 ; CHECK-LABEL: ugt_37_v2i64:
2667 ; CHECK: // %bb.0:
2668 ; CHECK-NEXT: cnt v0.16b, v0.16b
2669 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2670 ; CHECK-NEXT: mov w8, #37
2671 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2672 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2673 ; CHECK-NEXT: dup v1.2d, x8
2674 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2675 ; CHECK-NEXT: ret
2676 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2677 %3 = icmp ugt <2 x i64> %2, <i64 37, i64 37>
2678 %4 = sext <2 x i1> %3 to <2 x i64>
2679 ret <2 x i64> %4
2680 }
2682 define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
2683 ; CHECK-LABEL: ult_38_v2i64:
2684 ; CHECK: // %bb.0:
2685 ; CHECK-NEXT: cnt v0.16b, v0.16b
2686 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2687 ; CHECK-NEXT: mov w8, #38
2688 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2689 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2690 ; CHECK-NEXT: dup v1.2d, x8
2691 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2692 ; CHECK-NEXT: ret
2693 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2694 %3 = icmp ult <2 x i64> %2, <i64 38, i64 38>
2695 %4 = sext <2 x i1> %3 to <2 x i64>
2696 ret <2 x i64> %4
2697 }
2699 define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
2700 ; CHECK-LABEL: ugt_38_v2i64:
2701 ; CHECK: // %bb.0:
2702 ; CHECK-NEXT: cnt v0.16b, v0.16b
2703 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2704 ; CHECK-NEXT: mov w8, #38
2705 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2706 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2707 ; CHECK-NEXT: dup v1.2d, x8
2708 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2709 ; CHECK-NEXT: ret
2710 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2711 %3 = icmp ugt <2 x i64> %2, <i64 38, i64 38>
2712 %4 = sext <2 x i1> %3 to <2 x i64>
2713 ret <2 x i64> %4
2714 }
2716 define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
2717 ; CHECK-LABEL: ult_39_v2i64:
2718 ; CHECK: // %bb.0:
2719 ; CHECK-NEXT: cnt v0.16b, v0.16b
2720 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2721 ; CHECK-NEXT: mov w8, #39
2722 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2723 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2724 ; CHECK-NEXT: dup v1.2d, x8
2725 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2726 ; CHECK-NEXT: ret
2727 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2728 %3 = icmp ult <2 x i64> %2, <i64 39, i64 39>
2729 %4 = sext <2 x i1> %3 to <2 x i64>
2730 ret <2 x i64> %4
2731 }
2733 define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
2734 ; CHECK-LABEL: ugt_39_v2i64:
2735 ; CHECK: // %bb.0:
2736 ; CHECK-NEXT: cnt v0.16b, v0.16b
2737 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2738 ; CHECK-NEXT: mov w8, #39
2739 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2740 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2741 ; CHECK-NEXT: dup v1.2d, x8
2742 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2743 ; CHECK-NEXT: ret
2744 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2745 %3 = icmp ugt <2 x i64> %2, <i64 39, i64 39>
2746 %4 = sext <2 x i1> %3 to <2 x i64>
2747 ret <2 x i64> %4
2748 }
2750 define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
2751 ; CHECK-LABEL: ult_40_v2i64:
2752 ; CHECK: // %bb.0:
2753 ; CHECK-NEXT: cnt v0.16b, v0.16b
2754 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2755 ; CHECK-NEXT: mov w8, #40
2756 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2757 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2758 ; CHECK-NEXT: dup v1.2d, x8
2759 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2760 ; CHECK-NEXT: ret
2761 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2762 %3 = icmp ult <2 x i64> %2, <i64 40, i64 40>
2763 %4 = sext <2 x i1> %3 to <2 x i64>
2764 ret <2 x i64> %4
2765 }
2767 define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
2768 ; CHECK-LABEL: ugt_40_v2i64:
2769 ; CHECK: // %bb.0:
2770 ; CHECK-NEXT: cnt v0.16b, v0.16b
2771 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2772 ; CHECK-NEXT: mov w8, #40
2773 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2774 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2775 ; CHECK-NEXT: dup v1.2d, x8
2776 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2777 ; CHECK-NEXT: ret
2778 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2779 %3 = icmp ugt <2 x i64> %2, <i64 40, i64 40>
2780 %4 = sext <2 x i1> %3 to <2 x i64>
2781 ret <2 x i64> %4
2782 }
2784 define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
2785 ; CHECK-LABEL: ult_41_v2i64:
2786 ; CHECK: // %bb.0:
2787 ; CHECK-NEXT: cnt v0.16b, v0.16b
2788 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2789 ; CHECK-NEXT: mov w8, #41
2790 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2791 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2792 ; CHECK-NEXT: dup v1.2d, x8
2793 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2794 ; CHECK-NEXT: ret
2795 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2796 %3 = icmp ult <2 x i64> %2, <i64 41, i64 41>
2797 %4 = sext <2 x i1> %3 to <2 x i64>
2798 ret <2 x i64> %4
2799 }
2801 define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
2802 ; CHECK-LABEL: ugt_41_v2i64:
2803 ; CHECK: // %bb.0:
2804 ; CHECK-NEXT: cnt v0.16b, v0.16b
2805 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2806 ; CHECK-NEXT: mov w8, #41
2807 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2808 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2809 ; CHECK-NEXT: dup v1.2d, x8
2810 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2811 ; CHECK-NEXT: ret
2812 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2813 %3 = icmp ugt <2 x i64> %2, <i64 41, i64 41>
2814 %4 = sext <2 x i1> %3 to <2 x i64>
2815 ret <2 x i64> %4
2816 }
2818 define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
2819 ; CHECK-LABEL: ult_42_v2i64:
2820 ; CHECK: // %bb.0:
2821 ; CHECK-NEXT: cnt v0.16b, v0.16b
2822 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2823 ; CHECK-NEXT: mov w8, #42
2824 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2825 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2826 ; CHECK-NEXT: dup v1.2d, x8
2827 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2828 ; CHECK-NEXT: ret
2829 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2830 %3 = icmp ult <2 x i64> %2, <i64 42, i64 42>
2831 %4 = sext <2 x i1> %3 to <2 x i64>
2832 ret <2 x i64> %4
2833 }
2835 define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
2836 ; CHECK-LABEL: ugt_42_v2i64:
2837 ; CHECK: // %bb.0:
2838 ; CHECK-NEXT: cnt v0.16b, v0.16b
2839 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2840 ; CHECK-NEXT: mov w8, #42
2841 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2842 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2843 ; CHECK-NEXT: dup v1.2d, x8
2844 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2845 ; CHECK-NEXT: ret
2846 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2847 %3 = icmp ugt <2 x i64> %2, <i64 42, i64 42>
2848 %4 = sext <2 x i1> %3 to <2 x i64>
2849 ret <2 x i64> %4
2850 }
2852 define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
2853 ; CHECK-LABEL: ult_43_v2i64:
2854 ; CHECK: // %bb.0:
2855 ; CHECK-NEXT: cnt v0.16b, v0.16b
2856 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2857 ; CHECK-NEXT: mov w8, #43
2858 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2859 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2860 ; CHECK-NEXT: dup v1.2d, x8
2861 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2862 ; CHECK-NEXT: ret
2863 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2864 %3 = icmp ult <2 x i64> %2, <i64 43, i64 43>
2865 %4 = sext <2 x i1> %3 to <2 x i64>
2866 ret <2 x i64> %4
2867 }
2869 define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
2870 ; CHECK-LABEL: ugt_43_v2i64:
2871 ; CHECK: // %bb.0:
2872 ; CHECK-NEXT: cnt v0.16b, v0.16b
2873 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2874 ; CHECK-NEXT: mov w8, #43
2875 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2876 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2877 ; CHECK-NEXT: dup v1.2d, x8
2878 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2879 ; CHECK-NEXT: ret
2880 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2881 %3 = icmp ugt <2 x i64> %2, <i64 43, i64 43>
2882 %4 = sext <2 x i1> %3 to <2 x i64>
2883 ret <2 x i64> %4
2884 }
2886 define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
2887 ; CHECK-LABEL: ult_44_v2i64:
2888 ; CHECK: // %bb.0:
2889 ; CHECK-NEXT: cnt v0.16b, v0.16b
2890 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2891 ; CHECK-NEXT: mov w8, #44
2892 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2893 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2894 ; CHECK-NEXT: dup v1.2d, x8
2895 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2896 ; CHECK-NEXT: ret
2897 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2898 %3 = icmp ult <2 x i64> %2, <i64 44, i64 44>
2899 %4 = sext <2 x i1> %3 to <2 x i64>
2900 ret <2 x i64> %4
2901 }
2903 define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
2904 ; CHECK-LABEL: ugt_44_v2i64:
2905 ; CHECK: // %bb.0:
2906 ; CHECK-NEXT: cnt v0.16b, v0.16b
2907 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2908 ; CHECK-NEXT: mov w8, #44
2909 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2910 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2911 ; CHECK-NEXT: dup v1.2d, x8
2912 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2913 ; CHECK-NEXT: ret
2914 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2915 %3 = icmp ugt <2 x i64> %2, <i64 44, i64 44>
2916 %4 = sext <2 x i1> %3 to <2 x i64>
2917 ret <2 x i64> %4
2918 }
2920 define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
2921 ; CHECK-LABEL: ult_45_v2i64:
2922 ; CHECK: // %bb.0:
2923 ; CHECK-NEXT: cnt v0.16b, v0.16b
2924 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2925 ; CHECK-NEXT: mov w8, #45
2926 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2927 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2928 ; CHECK-NEXT: dup v1.2d, x8
2929 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2930 ; CHECK-NEXT: ret
2931 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2932 %3 = icmp ult <2 x i64> %2, <i64 45, i64 45>
2933 %4 = sext <2 x i1> %3 to <2 x i64>
2934 ret <2 x i64> %4
2935 }
2937 define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
2938 ; CHECK-LABEL: ugt_45_v2i64:
2939 ; CHECK: // %bb.0:
2940 ; CHECK-NEXT: cnt v0.16b, v0.16b
2941 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2942 ; CHECK-NEXT: mov w8, #45
2943 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2944 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2945 ; CHECK-NEXT: dup v1.2d, x8
2946 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2947 ; CHECK-NEXT: ret
2948 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2949 %3 = icmp ugt <2 x i64> %2, <i64 45, i64 45>
2950 %4 = sext <2 x i1> %3 to <2 x i64>
2951 ret <2 x i64> %4
2952 }
2954 define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
2955 ; CHECK-LABEL: ult_46_v2i64:
2956 ; CHECK: // %bb.0:
2957 ; CHECK-NEXT: cnt v0.16b, v0.16b
2958 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2959 ; CHECK-NEXT: mov w8, #46
2960 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2961 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2962 ; CHECK-NEXT: dup v1.2d, x8
2963 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2964 ; CHECK-NEXT: ret
2965 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2966 %3 = icmp ult <2 x i64> %2, <i64 46, i64 46>
2967 %4 = sext <2 x i1> %3 to <2 x i64>
2968 ret <2 x i64> %4
2969 }
2971 define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
2972 ; CHECK-LABEL: ugt_46_v2i64:
2973 ; CHECK: // %bb.0:
2974 ; CHECK-NEXT: cnt v0.16b, v0.16b
2975 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2976 ; CHECK-NEXT: mov w8, #46
2977 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2978 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2979 ; CHECK-NEXT: dup v1.2d, x8
2980 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
2981 ; CHECK-NEXT: ret
2982 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
2983 %3 = icmp ugt <2 x i64> %2, <i64 46, i64 46>
2984 %4 = sext <2 x i1> %3 to <2 x i64>
2985 ret <2 x i64> %4
2986 }
2988 define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
2989 ; CHECK-LABEL: ult_47_v2i64:
2990 ; CHECK: // %bb.0:
2991 ; CHECK-NEXT: cnt v0.16b, v0.16b
2992 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
2993 ; CHECK-NEXT: mov w8, #47
2994 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
2995 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
2996 ; CHECK-NEXT: dup v1.2d, x8
2997 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
2998 ; CHECK-NEXT: ret
2999 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3000 %3 = icmp ult <2 x i64> %2, <i64 47, i64 47>
3001 %4 = sext <2 x i1> %3 to <2 x i64>
3002 ret <2 x i64> %4
3003 }
3005 define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
3006 ; CHECK-LABEL: ugt_47_v2i64:
3007 ; CHECK: // %bb.0:
3008 ; CHECK-NEXT: cnt v0.16b, v0.16b
3009 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3010 ; CHECK-NEXT: mov w8, #47
3011 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3012 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3013 ; CHECK-NEXT: dup v1.2d, x8
3014 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3015 ; CHECK-NEXT: ret
3016 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3017 %3 = icmp ugt <2 x i64> %2, <i64 47, i64 47>
3018 %4 = sext <2 x i1> %3 to <2 x i64>
3019 ret <2 x i64> %4
3020 }
3022 define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
3023 ; CHECK-LABEL: ult_48_v2i64:
3024 ; CHECK: // %bb.0:
3025 ; CHECK-NEXT: cnt v0.16b, v0.16b
3026 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3027 ; CHECK-NEXT: mov w8, #48
3028 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3029 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3030 ; CHECK-NEXT: dup v1.2d, x8
3031 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3032 ; CHECK-NEXT: ret
3033 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3034 %3 = icmp ult <2 x i64> %2, <i64 48, i64 48>
3035 %4 = sext <2 x i1> %3 to <2 x i64>
3036 ret <2 x i64> %4
3037 }
3039 define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
3040 ; CHECK-LABEL: ugt_48_v2i64:
3041 ; CHECK: // %bb.0:
3042 ; CHECK-NEXT: cnt v0.16b, v0.16b
3043 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3044 ; CHECK-NEXT: mov w8, #48
3045 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3046 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3047 ; CHECK-NEXT: dup v1.2d, x8
3048 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3049 ; CHECK-NEXT: ret
3050 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3051 %3 = icmp ugt <2 x i64> %2, <i64 48, i64 48>
3052 %4 = sext <2 x i1> %3 to <2 x i64>
3053 ret <2 x i64> %4
3054 }
3056 define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
3057 ; CHECK-LABEL: ult_49_v2i64:
3058 ; CHECK: // %bb.0:
3059 ; CHECK-NEXT: cnt v0.16b, v0.16b
3060 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3061 ; CHECK-NEXT: mov w8, #49
3062 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3063 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3064 ; CHECK-NEXT: dup v1.2d, x8
3065 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3066 ; CHECK-NEXT: ret
3067 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3068 %3 = icmp ult <2 x i64> %2, <i64 49, i64 49>
3069 %4 = sext <2 x i1> %3 to <2 x i64>
3070 ret <2 x i64> %4
3071 }
3073 define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
3074 ; CHECK-LABEL: ugt_49_v2i64:
3075 ; CHECK: // %bb.0:
3076 ; CHECK-NEXT: cnt v0.16b, v0.16b
3077 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3078 ; CHECK-NEXT: mov w8, #49
3079 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3080 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3081 ; CHECK-NEXT: dup v1.2d, x8
3082 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3083 ; CHECK-NEXT: ret
3084 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3085 %3 = icmp ugt <2 x i64> %2, <i64 49, i64 49>
3086 %4 = sext <2 x i1> %3 to <2 x i64>
3087 ret <2 x i64> %4
3088 }
3090 define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
3091 ; CHECK-LABEL: ult_50_v2i64:
3092 ; CHECK: // %bb.0:
3093 ; CHECK-NEXT: cnt v0.16b, v0.16b
3094 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3095 ; CHECK-NEXT: mov w8, #50
3096 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3097 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3098 ; CHECK-NEXT: dup v1.2d, x8
3099 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3100 ; CHECK-NEXT: ret
3101 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3102 %3 = icmp ult <2 x i64> %2, <i64 50, i64 50>
3103 %4 = sext <2 x i1> %3 to <2 x i64>
3104 ret <2 x i64> %4
3105 }
3107 define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
3108 ; CHECK-LABEL: ugt_50_v2i64:
3109 ; CHECK: // %bb.0:
3110 ; CHECK-NEXT: cnt v0.16b, v0.16b
3111 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3112 ; CHECK-NEXT: mov w8, #50
3113 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3114 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3115 ; CHECK-NEXT: dup v1.2d, x8
3116 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3117 ; CHECK-NEXT: ret
3118 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3119 %3 = icmp ugt <2 x i64> %2, <i64 50, i64 50>
3120 %4 = sext <2 x i1> %3 to <2 x i64>
3121 ret <2 x i64> %4
3122 }
3124 define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
3125 ; CHECK-LABEL: ult_51_v2i64:
3126 ; CHECK: // %bb.0:
3127 ; CHECK-NEXT: cnt v0.16b, v0.16b
3128 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3129 ; CHECK-NEXT: mov w8, #51
3130 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3131 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3132 ; CHECK-NEXT: dup v1.2d, x8
3133 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3134 ; CHECK-NEXT: ret
3135 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3136 %3 = icmp ult <2 x i64> %2, <i64 51, i64 51>
3137 %4 = sext <2 x i1> %3 to <2 x i64>
3138 ret <2 x i64> %4
3139 }
3141 define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
3142 ; CHECK-LABEL: ugt_51_v2i64:
3143 ; CHECK: // %bb.0:
3144 ; CHECK-NEXT: cnt v0.16b, v0.16b
3145 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3146 ; CHECK-NEXT: mov w8, #51
3147 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3148 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3149 ; CHECK-NEXT: dup v1.2d, x8
3150 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3151 ; CHECK-NEXT: ret
3152 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3153 %3 = icmp ugt <2 x i64> %2, <i64 51, i64 51>
3154 %4 = sext <2 x i1> %3 to <2 x i64>
3155 ret <2 x i64> %4
3156 }
3158 define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
3159 ; CHECK-LABEL: ult_52_v2i64:
3160 ; CHECK: // %bb.0:
3161 ; CHECK-NEXT: cnt v0.16b, v0.16b
3162 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3163 ; CHECK-NEXT: mov w8, #52
3164 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3165 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3166 ; CHECK-NEXT: dup v1.2d, x8
3167 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3168 ; CHECK-NEXT: ret
3169 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3170 %3 = icmp ult <2 x i64> %2, <i64 52, i64 52>
3171 %4 = sext <2 x i1> %3 to <2 x i64>
3172 ret <2 x i64> %4
3173 }
3175 define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
3176 ; CHECK-LABEL: ugt_52_v2i64:
3177 ; CHECK: // %bb.0:
3178 ; CHECK-NEXT: cnt v0.16b, v0.16b
3179 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3180 ; CHECK-NEXT: mov w8, #52
3181 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3182 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3183 ; CHECK-NEXT: dup v1.2d, x8
3184 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3185 ; CHECK-NEXT: ret
3186 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3187 %3 = icmp ugt <2 x i64> %2, <i64 52, i64 52>
3188 %4 = sext <2 x i1> %3 to <2 x i64>
3189 ret <2 x i64> %4
3190 }
3192 define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
3193 ; CHECK-LABEL: ult_53_v2i64:
3194 ; CHECK: // %bb.0:
3195 ; CHECK-NEXT: cnt v0.16b, v0.16b
3196 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3197 ; CHECK-NEXT: mov w8, #53
3198 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3199 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3200 ; CHECK-NEXT: dup v1.2d, x8
3201 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3202 ; CHECK-NEXT: ret
3203 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3204 %3 = icmp ult <2 x i64> %2, <i64 53, i64 53>
3205 %4 = sext <2 x i1> %3 to <2 x i64>
3206 ret <2 x i64> %4
3207 }
3209 define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
3210 ; CHECK-LABEL: ugt_53_v2i64:
3211 ; CHECK: // %bb.0:
3212 ; CHECK-NEXT: cnt v0.16b, v0.16b
3213 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3214 ; CHECK-NEXT: mov w8, #53
3215 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3216 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3217 ; CHECK-NEXT: dup v1.2d, x8
3218 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3219 ; CHECK-NEXT: ret
3220 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3221 %3 = icmp ugt <2 x i64> %2, <i64 53, i64 53>
3222 %4 = sext <2 x i1> %3 to <2 x i64>
3223 ret <2 x i64> %4
3224 }
3226 define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
3227 ; CHECK-LABEL: ult_54_v2i64:
3228 ; CHECK: // %bb.0:
3229 ; CHECK-NEXT: cnt v0.16b, v0.16b
3230 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3231 ; CHECK-NEXT: mov w8, #54
3232 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3233 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3234 ; CHECK-NEXT: dup v1.2d, x8
3235 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3236 ; CHECK-NEXT: ret
3237 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3238 %3 = icmp ult <2 x i64> %2, <i64 54, i64 54>
3239 %4 = sext <2 x i1> %3 to <2 x i64>
3240 ret <2 x i64> %4
3241 }
3243 define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
3244 ; CHECK-LABEL: ugt_54_v2i64:
3245 ; CHECK: // %bb.0:
3246 ; CHECK-NEXT: cnt v0.16b, v0.16b
3247 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3248 ; CHECK-NEXT: mov w8, #54
3249 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3250 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3251 ; CHECK-NEXT: dup v1.2d, x8
3252 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3253 ; CHECK-NEXT: ret
3254 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3255 %3 = icmp ugt <2 x i64> %2, <i64 54, i64 54>
3256 %4 = sext <2 x i1> %3 to <2 x i64>
3257 ret <2 x i64> %4
3258 }
3260 define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
3261 ; CHECK-LABEL: ult_55_v2i64:
3262 ; CHECK: // %bb.0:
3263 ; CHECK-NEXT: cnt v0.16b, v0.16b
3264 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3265 ; CHECK-NEXT: mov w8, #55
3266 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3267 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3268 ; CHECK-NEXT: dup v1.2d, x8
3269 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3270 ; CHECK-NEXT: ret
3271 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3272 %3 = icmp ult <2 x i64> %2, <i64 55, i64 55>
3273 %4 = sext <2 x i1> %3 to <2 x i64>
3274 ret <2 x i64> %4
3275 }
3277 define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
3278 ; CHECK-LABEL: ugt_55_v2i64:
3279 ; CHECK: // %bb.0:
3280 ; CHECK-NEXT: cnt v0.16b, v0.16b
3281 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3282 ; CHECK-NEXT: mov w8, #55
3283 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3284 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3285 ; CHECK-NEXT: dup v1.2d, x8
3286 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3287 ; CHECK-NEXT: ret
3288 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3289 %3 = icmp ugt <2 x i64> %2, <i64 55, i64 55>
3290 %4 = sext <2 x i1> %3 to <2 x i64>
3291 ret <2 x i64> %4
3292 }
3294 define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
3295 ; CHECK-LABEL: ult_56_v2i64:
3296 ; CHECK: // %bb.0:
3297 ; CHECK-NEXT: cnt v0.16b, v0.16b
3298 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3299 ; CHECK-NEXT: mov w8, #56
3300 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3301 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3302 ; CHECK-NEXT: dup v1.2d, x8
3303 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3304 ; CHECK-NEXT: ret
3305 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3306 %3 = icmp ult <2 x i64> %2, <i64 56, i64 56>
3307 %4 = sext <2 x i1> %3 to <2 x i64>
3308 ret <2 x i64> %4
3309 }
3311 define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
3312 ; CHECK-LABEL: ugt_56_v2i64:
3313 ; CHECK: // %bb.0:
3314 ; CHECK-NEXT: cnt v0.16b, v0.16b
3315 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3316 ; CHECK-NEXT: mov w8, #56
3317 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3318 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3319 ; CHECK-NEXT: dup v1.2d, x8
3320 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3321 ; CHECK-NEXT: ret
3322 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3323 %3 = icmp ugt <2 x i64> %2, <i64 56, i64 56>
3324 %4 = sext <2 x i1> %3 to <2 x i64>
3325 ret <2 x i64> %4
3326 }
3328 define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
3329 ; CHECK-LABEL: ult_57_v2i64:
3330 ; CHECK: // %bb.0:
3331 ; CHECK-NEXT: cnt v0.16b, v0.16b
3332 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3333 ; CHECK-NEXT: mov w8, #57
3334 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3335 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3336 ; CHECK-NEXT: dup v1.2d, x8
3337 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3338 ; CHECK-NEXT: ret
3339 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3340 %3 = icmp ult <2 x i64> %2, <i64 57, i64 57>
3341 %4 = sext <2 x i1> %3 to <2 x i64>
3342 ret <2 x i64> %4
3343 }
3345 define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
3346 ; CHECK-LABEL: ugt_57_v2i64:
3347 ; CHECK: // %bb.0:
3348 ; CHECK-NEXT: cnt v0.16b, v0.16b
3349 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3350 ; CHECK-NEXT: mov w8, #57
3351 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3352 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3353 ; CHECK-NEXT: dup v1.2d, x8
3354 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3355 ; CHECK-NEXT: ret
3356 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3357 %3 = icmp ugt <2 x i64> %2, <i64 57, i64 57>
3358 %4 = sext <2 x i1> %3 to <2 x i64>
3359 ret <2 x i64> %4
3360 }
3362 define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
3363 ; CHECK-LABEL: ult_58_v2i64:
3364 ; CHECK: // %bb.0:
3365 ; CHECK-NEXT: cnt v0.16b, v0.16b
3366 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3367 ; CHECK-NEXT: mov w8, #58
3368 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3369 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3370 ; CHECK-NEXT: dup v1.2d, x8
3371 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3372 ; CHECK-NEXT: ret
3373 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3374 %3 = icmp ult <2 x i64> %2, <i64 58, i64 58>
3375 %4 = sext <2 x i1> %3 to <2 x i64>
3376 ret <2 x i64> %4
3377 }
3379 define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
3380 ; CHECK-LABEL: ugt_58_v2i64:
3381 ; CHECK: // %bb.0:
3382 ; CHECK-NEXT: cnt v0.16b, v0.16b
3383 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3384 ; CHECK-NEXT: mov w8, #58
3385 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3386 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3387 ; CHECK-NEXT: dup v1.2d, x8
3388 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3389 ; CHECK-NEXT: ret
3390 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3391 %3 = icmp ugt <2 x i64> %2, <i64 58, i64 58>
3392 %4 = sext <2 x i1> %3 to <2 x i64>
3393 ret <2 x i64> %4
3394 }
3396 define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
3397 ; CHECK-LABEL: ult_59_v2i64:
3398 ; CHECK: // %bb.0:
3399 ; CHECK-NEXT: cnt v0.16b, v0.16b
3400 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3401 ; CHECK-NEXT: mov w8, #59
3402 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3403 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3404 ; CHECK-NEXT: dup v1.2d, x8
3405 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3406 ; CHECK-NEXT: ret
3407 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3408 %3 = icmp ult <2 x i64> %2, <i64 59, i64 59>
3409 %4 = sext <2 x i1> %3 to <2 x i64>
3410 ret <2 x i64> %4
3411 }
3413 define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
3414 ; CHECK-LABEL: ugt_59_v2i64:
3415 ; CHECK: // %bb.0:
3416 ; CHECK-NEXT: cnt v0.16b, v0.16b
3417 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3418 ; CHECK-NEXT: mov w8, #59
3419 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3420 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3421 ; CHECK-NEXT: dup v1.2d, x8
3422 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3423 ; CHECK-NEXT: ret
3424 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3425 %3 = icmp ugt <2 x i64> %2, <i64 59, i64 59>
3426 %4 = sext <2 x i1> %3 to <2 x i64>
3427 ret <2 x i64> %4
3428 }
3430 define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
3431 ; CHECK-LABEL: ult_60_v2i64:
3432 ; CHECK: // %bb.0:
3433 ; CHECK-NEXT: cnt v0.16b, v0.16b
3434 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3435 ; CHECK-NEXT: mov w8, #60
3436 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3437 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3438 ; CHECK-NEXT: dup v1.2d, x8
3439 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3440 ; CHECK-NEXT: ret
3441 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3442 %3 = icmp ult <2 x i64> %2, <i64 60, i64 60>
3443 %4 = sext <2 x i1> %3 to <2 x i64>
3444 ret <2 x i64> %4
3445 }
3447 define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
3448 ; CHECK-LABEL: ugt_60_v2i64:
3449 ; CHECK: // %bb.0:
3450 ; CHECK-NEXT: cnt v0.16b, v0.16b
3451 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3452 ; CHECK-NEXT: mov w8, #60
3453 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3454 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3455 ; CHECK-NEXT: dup v1.2d, x8
3456 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3457 ; CHECK-NEXT: ret
3458 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3459 %3 = icmp ugt <2 x i64> %2, <i64 60, i64 60>
3460 %4 = sext <2 x i1> %3 to <2 x i64>
3461 ret <2 x i64> %4
3462 }
3464 define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
3465 ; CHECK-LABEL: ult_61_v2i64:
3466 ; CHECK: // %bb.0:
3467 ; CHECK-NEXT: cnt v0.16b, v0.16b
3468 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3469 ; CHECK-NEXT: mov w8, #61
3470 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3471 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3472 ; CHECK-NEXT: dup v1.2d, x8
3473 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3474 ; CHECK-NEXT: ret
3475 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3476 %3 = icmp ult <2 x i64> %2, <i64 61, i64 61>
3477 %4 = sext <2 x i1> %3 to <2 x i64>
3478 ret <2 x i64> %4
3479 }
3481 define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
3482 ; CHECK-LABEL: ugt_61_v2i64:
3483 ; CHECK: // %bb.0:
3484 ; CHECK-NEXT: cnt v0.16b, v0.16b
3485 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3486 ; CHECK-NEXT: mov w8, #61
3487 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3488 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3489 ; CHECK-NEXT: dup v1.2d, x8
3490 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3491 ; CHECK-NEXT: ret
3492 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3493 %3 = icmp ugt <2 x i64> %2, <i64 61, i64 61>
3494 %4 = sext <2 x i1> %3 to <2 x i64>
3495 ret <2 x i64> %4
3496 }
3498 define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
3499 ; CHECK-LABEL: ult_62_v2i64:
3500 ; CHECK: // %bb.0:
3501 ; CHECK-NEXT: cnt v0.16b, v0.16b
3502 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3503 ; CHECK-NEXT: mov w8, #62
3504 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3505 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3506 ; CHECK-NEXT: dup v1.2d, x8
3507 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3508 ; CHECK-NEXT: ret
3509 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3510 %3 = icmp ult <2 x i64> %2, <i64 62, i64 62>
3511 %4 = sext <2 x i1> %3 to <2 x i64>
3512 ret <2 x i64> %4
3513 }
3515 define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
3516 ; CHECK-LABEL: ugt_62_v2i64:
3517 ; CHECK: // %bb.0:
3518 ; CHECK-NEXT: cnt v0.16b, v0.16b
3519 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3520 ; CHECK-NEXT: mov w8, #62
3521 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3522 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3523 ; CHECK-NEXT: dup v1.2d, x8
3524 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
3525 ; CHECK-NEXT: ret
3526 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3527 %3 = icmp ugt <2 x i64> %2, <i64 62, i64 62>
3528 %4 = sext <2 x i1> %3 to <2 x i64>
3529 ret <2 x i64> %4
3530 }
3532 define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
3533 ; CHECK-LABEL: ult_63_v2i64:
3534 ; CHECK: // %bb.0:
3535 ; CHECK-NEXT: cnt v0.16b, v0.16b
3536 ; CHECK-NEXT: uaddlp v0.8h, v0.16b
3537 ; CHECK-NEXT: mov w8, #63
3538 ; CHECK-NEXT: uaddlp v0.4s, v0.8h
3539 ; CHECK-NEXT: uaddlp v0.2d, v0.4s
3540 ; CHECK-NEXT: dup v1.2d, x8
3541 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
3542 ; CHECK-NEXT: ret
3543 %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
3544 %3 = icmp ult <2 x i64> %2, <i64 63, i64 63>
3545 %4 = sext <2 x i1> %3 to <2 x i64>
3546 ret <2 x i64> %4
3547 }
3549 declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
3550 declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
3551 declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
3552 declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)