1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3 ; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
4 ; to be uniform during instruction selection. The custom selection for
5 ; brcond was not checking if the branch was uniform, relying on the
6 ; selection pattern to check that. That would fail, so then the branch
7 ; would fail to select.
9 ; GCN-LABEL: {{^}}copytoreg_divergent_brcond:
12 ; GCN-DAG: v_cmp_lt_i32
13 ; GCN-DAG: v_cmp_gt_i32
17 ; GCN: s_or_b64 exec, exec
18 ; GCN: {{[s|v]}}_cmp_eq_u32
21 define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
23 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
24 %tmp3 = zext i32 %tmp to i64
25 %tmp5 = add i64 %tmp3, undef
26 %tmp6 = trunc i64 %tmp5 to i32
27 %tmp7 = mul nsw i32 %tmp6, %arg2
30 bb8.loopexit: ; preds = %bb14
33 bb8: ; preds = %bb8.loopexit, %bb
36 bb9: ; preds = %bb14, %bb8
37 %tmp10 = icmp slt i32 %tmp7, %arg1
38 %tmp11 = icmp sgt i32 %arg, 0
39 %tmp12 = and i1 %tmp10, %tmp11
40 br i1 %tmp12, label %bb13, label %bb14
43 store volatile i32 0, i32 addrspace(1)* undef, align 4
46 bb14: ; preds = %bb13, %bb9
47 %tmp15 = icmp eq i32 %arg2, 1
48 br i1 %tmp15, label %bb8.loopexit, label %bb9
51 declare i32 @llvm.amdgcn.workitem.id.x() #1
53 attributes #0 = { nounwind optnone noinline }
54 attributes #1 = { nounwind readnone speculatable }