llvm/test/CodeGen/AMDGPU/dpp64_combine.mir

   1 # RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN
   2
   3 ---
   4 # GCN-LABEL: name: dpp64_old_impdef
   5 # GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %1, 0, %0, 337, 15, 15, 1, implicit $mode, implicit $exec
   6 ---
   7 name: dpp64_old_impdef
   8 tracksRegLiveness: true
   9 body: |
  10   bb.0:
  11     %0:vreg_64_align2 = IMPLICIT_DEF
  12     %1:vreg_64_align2 = IMPLICIT_DEF
  13     %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO %1, %0, 337, 15, 15, 1, implicit $exec
  14     %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
  15 ...
  16
  17 # GCN-LABEL: name: dpp64_old_undef
  18 # GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp undef %1:vreg_64_align2, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec
  19 ---
  20 name: dpp64_old_undef
  21 tracksRegLiveness: true
  22 body: |
  23   bb.0:
  24     %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec
  25     %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
  26 ...
  27
  28 # GCN-LABEL: name: dpp64_old_is_0
  29 # GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %4, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec
  30 name: dpp64_old_is_0
  31 tracksRegLiveness: true
  32 body: |
  33   bb.0:
  34     %1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
  35     %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec
  36     %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
  37 ...
  38
  39 # DPP64 does not support all control values and must be split to become legal
  40 # GCN-LABEL: name: dpp64_illegal_ctrl
  41 # GCN: %4:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64_align2, undef %2.sub0:vreg_64_align2, 1, 15, 15, 1, implicit $exec
  42 # GCN: %5:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64_align2, undef %2.sub1:vreg_64_align2, 1, 15, 15, 1, implicit $exec
  43 # GCN: %0:vreg_64_align2 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1
  44 # GCN: %3:vreg_64_align2 = V_CEIL_F64_e32 %0, implicit $mode, implicit $exec
  45 name: dpp64_illegal_ctrl
  46 tracksRegLiveness: true
  47 body: |
  48   bb.0:
  49     %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 1, 15, 15, 1, implicit $exec
  50     %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
  51 ...