1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=regallocfast -o - %s | FileCheck %s
4 # Make sure incorrect kills aren't emitted on vcc
8 tracksRegLiveness: true
11 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
12 stackPtrOffsetReg: '$sgpr32'
17 ; CHECK-LABEL: name: foo
18 ; CHECK: liveins: $vgpr0
19 ; CHECK: V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
20 ; CHECK: $sgpr4_sgpr5 = COPY $vcc
21 ; CHECK: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, 3, killed $vcc, implicit $exec
22 ; CHECK: S_ENDPGM 0, implicit killed $vgpr0, implicit killed $sgpr4_sgpr5
23 %0:vgpr_32 = COPY $vgpr0
24 V_CMP_NE_U32_e32 0, %0, implicit-def $vcc, implicit $exec
25 $sgpr4_sgpr5 = COPY $vcc
26 %1:sreg_64_xexec = COPY $vcc
27 %2:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, 3, %1, implicit $exec
29 S_ENDPGM 0, implicit $vgpr0, implicit $sgpr4_sgpr5
33 # This would hit "Unexpected reg unit state" assert.
36 tracksRegLiveness: true
39 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
40 stackPtrOffsetReg: '$sgpr32'
45 ; CHECK-LABEL: name: bar
46 ; CHECK: liveins: $vgpr0
47 ; CHECK: V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
48 ; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
49 ; CHECK: SI_SPILL_S64_SAVE $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s64) into %stack.0, align 4, addrspace 5)
50 ; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
51 ; CHECK: $vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s64) from %stack.0, align 4, addrspace 5)
52 ; CHECK: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, 3, killed $sgpr4_sgpr5, implicit $exec
53 ; CHECK: S_ENDPGM 0, implicit killed $vgpr0, implicit killed renamable $vcc
54 %0:vgpr_32 = COPY $vgpr0
55 V_CMP_NE_U32_e32 0, %0, implicit-def $vcc, implicit $exec
56 %3:sreg_64_xexec = COPY $vcc
57 %1:sreg_64_xexec = COPY $vcc
58 %2:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, 3, %1, implicit $exec
60 S_ENDPGM 0, implicit $vgpr0, implicit %3