| blob | 7dabae23c6b5b759e6705f908d8979b1826d5c80 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s --check-prefixes=SI
3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s --check-prefixes=VI
4 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefixes=EG
6 declare float @llvm.fabs.f32(float) #1
8 define amdgpu_kernel void @fp_to_sint_i32(i32 addrspace(1)* %out, float %in) {
9 ; SI-LABEL: fp_to_sint_i32:
10 ; SI: ; %bb.0:
11 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
12 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
13 ; SI-NEXT: s_mov_b32 s3, 0xf000
14 ; SI-NEXT: s_mov_b32 s2, -1
15 ; SI-NEXT: s_waitcnt lgkmcnt(0)
16 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
17 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
18 ; SI-NEXT: s_endpgm
19 ;
20 ; VI-LABEL: fp_to_sint_i32:
21 ; VI: ; %bb.0:
22 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
23 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
24 ; VI-NEXT: s_mov_b32 s3, 0xf000
25 ; VI-NEXT: s_waitcnt lgkmcnt(0)
26 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
27 ; VI-NEXT: s_mov_b32 s2, -1
28 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
29 ; VI-NEXT: s_endpgm
30 ;
31 ; EG-LABEL: fp_to_sint_i32:
32 ; EG: ; %bb.0:
33 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
34 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
35 ; EG-NEXT: CF_END
36 ; EG-NEXT: PAD
37 ; EG-NEXT: ALU clause starting at 4:
38 ; EG-NEXT: TRUNC * T0.W, KC0[2].Z,
39 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
40 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
41 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
42 %conv = fptosi float %in to i32
43 store i32 %conv, i32 addrspace(1)* %out
44 ret void
45 }
47 define amdgpu_kernel void @fp_to_sint_i32_fabs(i32 addrspace(1)* %out, float %in) {
48 ; SI-LABEL: fp_to_sint_i32_fabs:
49 ; SI: ; %bb.0:
50 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
51 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
52 ; SI-NEXT: s_mov_b32 s3, 0xf000
53 ; SI-NEXT: s_mov_b32 s2, -1
54 ; SI-NEXT: s_waitcnt lgkmcnt(0)
55 ; SI-NEXT: v_cvt_i32_f32_e64 v0, |s4|
56 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
57 ; SI-NEXT: s_endpgm
58 ;
59 ; VI-LABEL: fp_to_sint_i32_fabs:
60 ; VI: ; %bb.0:
61 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
62 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
63 ; VI-NEXT: s_mov_b32 s3, 0xf000
64 ; VI-NEXT: s_waitcnt lgkmcnt(0)
65 ; VI-NEXT: v_cvt_i32_f32_e64 v0, |s2|
66 ; VI-NEXT: s_mov_b32 s2, -1
67 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
68 ; VI-NEXT: s_endpgm
69 ;
70 ; EG-LABEL: fp_to_sint_i32_fabs:
71 ; EG: ; %bb.0:
72 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
73 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
74 ; EG-NEXT: CF_END
75 ; EG-NEXT: PAD
76 ; EG-NEXT: ALU clause starting at 4:
77 ; EG-NEXT: TRUNC * T0.W, |KC0[2].Z|,
78 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
79 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
80 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
81 %in.fabs = call float @llvm.fabs.f32(float %in)
82 %conv = fptosi float %in.fabs to i32
83 store i32 %conv, i32 addrspace(1)* %out
84 ret void
85 }
87 define amdgpu_kernel void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
88 ; SI-LABEL: fp_to_sint_v2i32:
89 ; SI: ; %bb.0:
90 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
91 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
92 ; SI-NEXT: s_mov_b32 s3, 0xf000
93 ; SI-NEXT: s_mov_b32 s2, -1
94 ; SI-NEXT: s_waitcnt lgkmcnt(0)
95 ; SI-NEXT: v_cvt_i32_f32_e32 v1, s5
96 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
97 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
98 ; SI-NEXT: s_endpgm
99 ;
100 ; VI-LABEL: fp_to_sint_v2i32:
101 ; VI: ; %bb.0:
102 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
103 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
104 ; VI-NEXT: s_waitcnt lgkmcnt(0)
105 ; VI-NEXT: v_cvt_i32_f32_e32 v1, s3
106 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
107 ; VI-NEXT: s_mov_b32 s3, 0xf000
108 ; VI-NEXT: s_mov_b32 s2, -1
109 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
110 ; VI-NEXT: s_endpgm
111 ;
112 ; EG-LABEL: fp_to_sint_v2i32:
113 ; EG: ; %bb.0:
114 ; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
115 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
116 ; EG-NEXT: CF_END
117 ; EG-NEXT: PAD
118 ; EG-NEXT: ALU clause starting at 4:
119 ; EG-NEXT: TRUNC * T0.W, KC0[3].X,
120 ; EG-NEXT: FLT_TO_INT T0.Y, PV.W,
121 ; EG-NEXT: TRUNC * T0.W, KC0[2].W,
122 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
123 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
124 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
125 %result = fptosi <2 x float> %in to <2 x i32>
126 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
127 ret void
128 }
130 define amdgpu_kernel void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
131 ; SI-LABEL: fp_to_sint_v4i32:
132 ; SI: ; %bb.0:
133 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
134 ; SI-NEXT: s_waitcnt lgkmcnt(0)
135 ; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
136 ; SI-NEXT: s_mov_b32 s3, 0xf000
137 ; SI-NEXT: s_mov_b32 s2, -1
138 ; SI-NEXT: s_waitcnt lgkmcnt(0)
139 ; SI-NEXT: v_cvt_i32_f32_e32 v3, s7
140 ; SI-NEXT: v_cvt_i32_f32_e32 v2, s6
141 ; SI-NEXT: v_cvt_i32_f32_e32 v1, s5
142 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
143 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
144 ; SI-NEXT: s_endpgm
145 ;
146 ; VI-LABEL: fp_to_sint_v4i32:
147 ; VI: ; %bb.0:
148 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
149 ; VI-NEXT: s_waitcnt lgkmcnt(0)
150 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
151 ; VI-NEXT: s_mov_b32 s3, 0xf000
152 ; VI-NEXT: s_mov_b32 s2, -1
153 ; VI-NEXT: s_waitcnt lgkmcnt(0)
154 ; VI-NEXT: v_cvt_i32_f32_e32 v3, s7
155 ; VI-NEXT: v_cvt_i32_f32_e32 v2, s6
156 ; VI-NEXT: v_cvt_i32_f32_e32 v1, s5
157 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s4
158 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
159 ; VI-NEXT: s_endpgm
160 ;
161 ; EG-LABEL: fp_to_sint_v4i32:
162 ; EG: ; %bb.0:
163 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
164 ; EG-NEXT: TEX 0 @6
165 ; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]
166 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
167 ; EG-NEXT: CF_END
168 ; EG-NEXT: PAD
169 ; EG-NEXT: Fetch clause starting at 6:
170 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
171 ; EG-NEXT: ALU clause starting at 8:
172 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
173 ; EG-NEXT: ALU clause starting at 9:
174 ; EG-NEXT: TRUNC T0.W, T0.W,
175 ; EG-NEXT: TRUNC * T1.W, T0.Z,
176 ; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
177 ; EG-NEXT: FLT_TO_INT T0.Z, T1.W,
178 ; EG-NEXT: TRUNC * T1.W, T0.Y,
179 ; EG-NEXT: FLT_TO_INT T0.Y, PV.W,
180 ; EG-NEXT: TRUNC * T1.W, T0.X,
181 ; EG-NEXT: FLT_TO_INT T0.X, PV.W,
182 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
183 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
184 %value = load <4 x float>, <4 x float> addrspace(1) * %in
185 %result = fptosi <4 x float> %value to <4 x i32>
186 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
187 ret void
188 }
190 ; Check that the compiler doesn't crash with a "cannot select" error
191 define amdgpu_kernel void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
192 ; SI-LABEL: fp_to_sint_i64:
193 ; SI: ; %bb.0: ; %entry
194 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
195 ; SI-NEXT: s_load_dword s0, s[0:1], 0xb
196 ; SI-NEXT: s_mov_b32 s7, 0xf000
197 ; SI-NEXT: s_mov_b32 s6, -1
198 ; SI-NEXT: s_mov_b32 s1, 0x2f800000
199 ; SI-NEXT: s_mov_b32 s2, 0xcf800000
200 ; SI-NEXT: s_waitcnt lgkmcnt(0)
201 ; SI-NEXT: v_trunc_f32_e32 v0, s0
202 ; SI-NEXT: v_mul_f32_e64 v1, |v0|, s1
203 ; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v0
204 ; SI-NEXT: v_floor_f32_e32 v1, v1
205 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v1
206 ; SI-NEXT: v_fma_f32 v0, v1, s2, |v0|
207 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
208 ; SI-NEXT: v_xor_b32_e32 v1, v3, v2
209 ; SI-NEXT: v_xor_b32_e32 v0, v0, v2
210 ; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
211 ; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
212 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
213 ; SI-NEXT: s_endpgm
214 ;
215 ; VI-LABEL: fp_to_sint_i64:
216 ; VI: ; %bb.0: ; %entry
217 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
218 ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
219 ; VI-NEXT: s_mov_b32 s2, 0x2f800000
220 ; VI-NEXT: s_mov_b32 s3, 0xcf800000
221 ; VI-NEXT: s_mov_b32 s7, 0xf000
222 ; VI-NEXT: s_mov_b32 s6, -1
223 ; VI-NEXT: s_waitcnt lgkmcnt(0)
224 ; VI-NEXT: v_trunc_f32_e32 v0, s0
225 ; VI-NEXT: v_mul_f32_e64 v1, |v0|, s2
226 ; VI-NEXT: v_floor_f32_e32 v1, v1
227 ; VI-NEXT: v_fma_f32 v2, v1, s3, |v0|
228 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
229 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
230 ; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
231 ; VI-NEXT: v_xor_b32_e32 v0, v2, v3
232 ; VI-NEXT: v_xor_b32_e32 v1, v1, v3
233 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
234 ; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
235 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
236 ; VI-NEXT: s_endpgm
237 ;
238 ; EG-LABEL: fp_to_sint_i64:
239 ; EG: ; %bb.0: ; %entry
240 ; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[]
241 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
242 ; EG-NEXT: CF_END
243 ; EG-NEXT: PAD
244 ; EG-NEXT: ALU clause starting at 4:
245 ; EG-NEXT: MOV * T0.W, literal.x,
246 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
247 ; EG-NEXT: BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
248 ; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.y,
249 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
250 ; EG-NEXT: OR_INT T1.W, PS, literal.x,
251 ; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,
252 ; EG-NEXT: 8388608(1.175494e-38), -150(nan)
253 ; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,
254 ; EG-NEXT: SUB_INT T0.Y, literal.y, T0.W,
255 ; EG-NEXT: AND_INT T0.Z, PS, literal.z,
256 ; EG-NEXT: NOT_INT T0.W, PS,
257 ; EG-NEXT: LSHR * T3.W, PV.W, 1,
258 ; EG-NEXT: -127(nan), 150(2.101948e-43)
259 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
260 ; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
261 ; EG-NEXT: LSHL T1.Y, T1.W, PV.Z,
262 ; EG-NEXT: AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
263 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
264 ; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,
265 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
266 ; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
267 ; EG-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
268 ; EG-NEXT: CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
269 ; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,
270 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
271 ; EG-NEXT: CNDE_INT T0.Z, PS, 0.0, PV.W,
272 ; EG-NEXT: CNDE_INT T0.W, PS, PV.Y, PV.Z,
273 ; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,
274 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
275 ; EG-NEXT: XOR_INT T0.W, PV.W, PS,
276 ; EG-NEXT: XOR_INT * T2.W, PV.Z, PS,
277 ; EG-NEXT: SUB_INT T2.W, PS, T1.W,
278 ; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
279 ; EG-NEXT: SUB_INT T2.W, PV.W, PS,
280 ; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x,
281 ; EG-NEXT: -1(nan), 0(0.000000e+00)
282 ; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W,
283 ; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
284 ; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W,
285 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
286 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
287 entry:
288 %0 = fptosi float %in to i64
289 store i64 %0, i64 addrspace(1)* %out
290 ret void
291 }
293 define amdgpu_kernel void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
294 ; SI-LABEL: fp_to_sint_v2i64:
295 ; SI: ; %bb.0:
296 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
297 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
298 ; SI-NEXT: s_mov_b32 s7, 0xf000
299 ; SI-NEXT: s_mov_b32 s6, -1
300 ; SI-NEXT: s_mov_b32 s2, 0x2f800000
301 ; SI-NEXT: s_mov_b32 s3, 0xcf800000
302 ; SI-NEXT: s_waitcnt lgkmcnt(0)
303 ; SI-NEXT: v_trunc_f32_e32 v0, s1
304 ; SI-NEXT: v_trunc_f32_e32 v1, s0
305 ; SI-NEXT: v_mul_f32_e64 v2, |v0|, s2
306 ; SI-NEXT: v_ashrrev_i32_e32 v3, 31, v0
307 ; SI-NEXT: v_mul_f32_e64 v4, |v1|, s2
308 ; SI-NEXT: v_ashrrev_i32_e32 v5, 31, v1
309 ; SI-NEXT: v_floor_f32_e32 v2, v2
310 ; SI-NEXT: v_floor_f32_e32 v4, v4
311 ; SI-NEXT: v_cvt_u32_f32_e32 v6, v2
312 ; SI-NEXT: v_fma_f32 v0, v2, s3, |v0|
313 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v4
314 ; SI-NEXT: v_fma_f32 v1, v4, s3, |v1|
315 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
316 ; SI-NEXT: v_xor_b32_e32 v4, v6, v3
317 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
318 ; SI-NEXT: v_xor_b32_e32 v6, v2, v5
319 ; SI-NEXT: v_xor_b32_e32 v0, v0, v3
320 ; SI-NEXT: v_xor_b32_e32 v1, v1, v5
321 ; SI-NEXT: v_sub_i32_e32 v2, vcc, v0, v3
322 ; SI-NEXT: v_subb_u32_e32 v3, vcc, v4, v3, vcc
323 ; SI-NEXT: v_sub_i32_e32 v0, vcc, v1, v5
324 ; SI-NEXT: v_subb_u32_e32 v1, vcc, v6, v5, vcc
325 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
326 ; SI-NEXT: s_endpgm
327 ;
328 ; VI-LABEL: fp_to_sint_v2i64:
329 ; VI: ; %bb.0:
330 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
331 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
332 ; VI-NEXT: s_mov_b32 s2, 0x2f800000
333 ; VI-NEXT: s_mov_b32 s3, 0xcf800000
334 ; VI-NEXT: s_mov_b32 s7, 0xf000
335 ; VI-NEXT: s_mov_b32 s6, -1
336 ; VI-NEXT: s_waitcnt lgkmcnt(0)
337 ; VI-NEXT: v_trunc_f32_e32 v0, s1
338 ; VI-NEXT: v_mul_f32_e64 v1, |v0|, s2
339 ; VI-NEXT: v_floor_f32_e32 v1, v1
340 ; VI-NEXT: v_fma_f32 v2, v1, s3, |v0|
341 ; VI-NEXT: v_trunc_f32_e32 v4, s0
342 ; VI-NEXT: v_mul_f32_e64 v3, |v4|, s2
343 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
344 ; VI-NEXT: v_floor_f32_e32 v3, v3
345 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
346 ; VI-NEXT: v_cvt_u32_f32_e32 v5, v3
347 ; VI-NEXT: v_fma_f32 v3, v3, s3, |v4|
348 ; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
349 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v3
350 ; VI-NEXT: v_xor_b32_e32 v2, v2, v0
351 ; VI-NEXT: v_xor_b32_e32 v1, v1, v0
352 ; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
353 ; VI-NEXT: v_subb_u32_e32 v3, vcc, v1, v0, vcc
354 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
355 ; VI-NEXT: v_xor_b32_e32 v0, v6, v1
356 ; VI-NEXT: v_xor_b32_e32 v4, v5, v1
357 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
358 ; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
359 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
360 ; VI-NEXT: s_endpgm
361 ;
362 ; EG-LABEL: fp_to_sint_v2i64:
363 ; EG: ; %bb.0:
364 ; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[]
365 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
366 ; EG-NEXT: CF_END
367 ; EG-NEXT: PAD
368 ; EG-NEXT: ALU clause starting at 4:
369 ; EG-NEXT: MOV * T0.W, literal.x,
370 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
371 ; EG-NEXT: BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
372 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
373 ; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
374 ; EG-NEXT: BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
375 ; EG-NEXT: ADD_INT * T2.W, PV.W, literal.z,
376 ; EG-NEXT: 8388607(1.175494e-38), 23(3.222986e-44)
377 ; EG-NEXT: -150(nan), 0(0.000000e+00)
378 ; EG-NEXT: SUB_INT T0.X, literal.x, PV.W,
379 ; EG-NEXT: SUB_INT T0.Y, literal.x, T1.W,
380 ; EG-NEXT: AND_INT T1.Z, PS, literal.y,
381 ; EG-NEXT: OR_INT T3.W, PV.Z, literal.z,
382 ; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,
383 ; EG-NEXT: 150(2.101948e-43), 31(4.344025e-44)
384 ; EG-NEXT: 8388608(1.175494e-38), 8388607(1.175494e-38)
385 ; EG-NEXT: OR_INT T1.X, PS, literal.x,
386 ; EG-NEXT: LSHL T1.Y, PV.W, PV.Z,
387 ; EG-NEXT: AND_INT T0.Z, T2.W, literal.y,
388 ; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
389 ; EG-NEXT: AND_INT * T5.W, PV.Y, literal.y,
390 ; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)
391 ; EG-NEXT: CNDE_INT T2.X, PS, PV.W, 0.0,
392 ; EG-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
393 ; EG-NEXT: ADD_INT T1.Z, T0.W, literal.x,
394 ; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
395 ; EG-NEXT: AND_INT * T5.W, T0.X, literal.y,
396 ; EG-NEXT: -150(nan), 32(4.484155e-44)
397 ; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,
398 ; EG-NEXT: NOT_INT T2.Y, T2.W,
399 ; EG-NEXT: AND_INT T2.Z, PV.Z, literal.x,
400 ; EG-NEXT: NOT_INT T2.W, PV.Z,
401 ; EG-NEXT: LSHR * T4.W, T1.X, 1,
402 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
403 ; EG-NEXT: LSHR T3.X, T3.W, 1,
404 ; EG-NEXT: ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
405 ; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
406 ; EG-NEXT: LSHL T0.W, T1.X, PV.Z,
407 ; EG-NEXT: AND_INT * T2.W, T1.Z, literal.y,
408 ; EG-NEXT: -127(nan), 32(4.484155e-44)
409 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
410 ; EG-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W,
411 ; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
412 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
413 ; EG-NEXT: ADD_INT * T1.W, T1.W, literal.y,
414 ; EG-NEXT: 23(3.222986e-44), -127(nan)
415 ; EG-NEXT: CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
416 ; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,
417 ; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
418 ; EG-NEXT: CNDE_INT T0.W, PV.Z, T0.X, PV.X,
419 ; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,
420 ; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)
421 ; EG-NEXT: XOR_INT T0.X, PV.W, PS,
422 ; EG-NEXT: XOR_INT T2.Y, PV.Z, PS,
423 ; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
424 ; EG-NEXT: CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
425 ; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,
426 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
427 ; EG-NEXT: XOR_INT T0.Y, PV.W, PS,
428 ; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
429 ; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
430 ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
431 ; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
432 ; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x,
433 ; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
434 ; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
435 ; EG-NEXT: -1(nan), 0(0.000000e+00)
436 ; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
437 ; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x,
438 ; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122
439 ; EG-NEXT: -1(nan), 0(0.000000e+00)
440 ; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z,
441 ; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
442 ; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W,
443 ; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
444 ; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W,
445 ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
446 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
447 %conv = fptosi <2 x float> %x to <2 x i64>
448 store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
449 ret void
450 }
452 define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
453 ; SI-LABEL: fp_to_sint_v4i64:
454 ; SI: ; %bb.0:
455 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
456 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
457 ; SI-NEXT: s_mov_b32 s7, 0xf000
458 ; SI-NEXT: s_mov_b32 s6, -1
459 ; SI-NEXT: s_mov_b32 s8, 0x2f800000
460 ; SI-NEXT: s_mov_b32 s9, 0xcf800000
461 ; SI-NEXT: s_waitcnt lgkmcnt(0)
462 ; SI-NEXT: v_trunc_f32_e32 v0, s1
463 ; SI-NEXT: v_trunc_f32_e32 v1, s0
464 ; SI-NEXT: v_trunc_f32_e32 v2, s3
465 ; SI-NEXT: v_trunc_f32_e32 v3, s2
466 ; SI-NEXT: v_mul_f32_e64 v4, |v0|, s8
467 ; SI-NEXT: v_ashrrev_i32_e32 v5, 31, v0
468 ; SI-NEXT: v_mul_f32_e64 v6, |v1|, s8
469 ; SI-NEXT: v_ashrrev_i32_e32 v7, 31, v1
470 ; SI-NEXT: v_mul_f32_e64 v8, |v2|, s8
471 ; SI-NEXT: v_ashrrev_i32_e32 v9, 31, v2
472 ; SI-NEXT: v_mul_f32_e64 v10, |v3|, s8
473 ; SI-NEXT: v_ashrrev_i32_e32 v11, 31, v3
474 ; SI-NEXT: v_floor_f32_e32 v4, v4
475 ; SI-NEXT: v_floor_f32_e32 v6, v6
476 ; SI-NEXT: v_floor_f32_e32 v8, v8
477 ; SI-NEXT: v_floor_f32_e32 v10, v10
478 ; SI-NEXT: v_cvt_u32_f32_e32 v12, v4
479 ; SI-NEXT: v_fma_f32 v0, v4, s9, |v0|
480 ; SI-NEXT: v_cvt_u32_f32_e32 v4, v6
481 ; SI-NEXT: v_fma_f32 v1, v6, s9, |v1|
482 ; SI-NEXT: v_cvt_u32_f32_e32 v6, v8
483 ; SI-NEXT: v_fma_f32 v2, v8, s9, |v2|
484 ; SI-NEXT: v_cvt_u32_f32_e32 v8, v10
485 ; SI-NEXT: v_fma_f32 v3, v10, s9, |v3|
486 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
487 ; SI-NEXT: v_xor_b32_e32 v10, v12, v5
488 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v1
489 ; SI-NEXT: v_xor_b32_e32 v4, v4, v7
490 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v2
491 ; SI-NEXT: v_xor_b32_e32 v12, v6, v9
492 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v3
493 ; SI-NEXT: v_xor_b32_e32 v8, v8, v11
494 ; SI-NEXT: v_xor_b32_e32 v0, v0, v5
495 ; SI-NEXT: v_xor_b32_e32 v1, v1, v7
496 ; SI-NEXT: v_xor_b32_e32 v6, v2, v9
497 ; SI-NEXT: v_xor_b32_e32 v13, v3, v11
498 ; SI-NEXT: v_sub_i32_e32 v2, vcc, v0, v5
499 ; SI-NEXT: v_subb_u32_e32 v3, vcc, v10, v5, vcc
500 ; SI-NEXT: v_sub_i32_e32 v0, vcc, v1, v7
501 ; SI-NEXT: v_subb_u32_e32 v1, vcc, v4, v7, vcc
502 ; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v9
503 ; SI-NEXT: v_subb_u32_e32 v7, vcc, v12, v9, vcc
504 ; SI-NEXT: v_sub_i32_e32 v4, vcc, v13, v11
505 ; SI-NEXT: v_subb_u32_e32 v5, vcc, v8, v11, vcc
506 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
507 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
508 ; SI-NEXT: s_endpgm
509 ;
510 ; VI-LABEL: fp_to_sint_v4i64:
511 ; VI: ; %bb.0:
512 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
513 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
514 ; VI-NEXT: s_mov_b32 s8, 0x2f800000
515 ; VI-NEXT: s_mov_b32 s9, 0xcf800000
516 ; VI-NEXT: s_mov_b32 s7, 0xf000
517 ; VI-NEXT: s_mov_b32 s6, -1
518 ; VI-NEXT: s_waitcnt lgkmcnt(0)
519 ; VI-NEXT: v_trunc_f32_e32 v0, s1
520 ; VI-NEXT: v_mul_f32_e64 v1, |v0|, s8
521 ; VI-NEXT: v_floor_f32_e32 v1, v1
522 ; VI-NEXT: v_fma_f32 v2, v1, s9, |v0|
523 ; VI-NEXT: v_trunc_f32_e32 v4, s0
524 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
525 ; VI-NEXT: v_mul_f32_e64 v3, |v4|, s8
526 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
527 ; VI-NEXT: v_floor_f32_e32 v3, v3
528 ; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
529 ; VI-NEXT: v_cvt_u32_f32_e32 v5, v3
530 ; VI-NEXT: v_fma_f32 v3, v3, s9, |v4|
531 ; VI-NEXT: v_xor_b32_e32 v2, v2, v0
532 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v3
533 ; VI-NEXT: v_xor_b32_e32 v1, v1, v0
534 ; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0
535 ; VI-NEXT: v_subb_u32_e32 v3, vcc, v1, v0, vcc
536 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v4
537 ; VI-NEXT: v_xor_b32_e32 v4, v5, v1
538 ; VI-NEXT: v_trunc_f32_e32 v5, s3
539 ; VI-NEXT: v_xor_b32_e32 v0, v6, v1
540 ; VI-NEXT: v_mul_f32_e64 v6, |v5|, s8
541 ; VI-NEXT: v_floor_f32_e32 v6, v6
542 ; VI-NEXT: v_cvt_u32_f32_e32 v7, v6
543 ; VI-NEXT: v_fma_f32 v6, v6, s9, |v5|
544 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v6
545 ; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
546 ; VI-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
547 ; VI-NEXT: v_ashrrev_i32_e32 v4, 31, v5
548 ; VI-NEXT: v_trunc_f32_e32 v8, s2
549 ; VI-NEXT: v_xor_b32_e32 v5, v6, v4
550 ; VI-NEXT: v_mul_f32_e64 v6, |v8|, s8
551 ; VI-NEXT: v_floor_f32_e32 v6, v6
552 ; VI-NEXT: v_cvt_u32_f32_e32 v9, v6
553 ; VI-NEXT: v_fma_f32 v6, v6, s9, |v8|
554 ; VI-NEXT: v_cvt_u32_f32_e32 v10, v6
555 ; VI-NEXT: v_sub_u32_e32 v6, vcc, v5, v4
556 ; VI-NEXT: v_xor_b32_e32 v7, v7, v4
557 ; VI-NEXT: v_ashrrev_i32_e32 v5, 31, v8
558 ; VI-NEXT: v_subb_u32_e32 v7, vcc, v7, v4, vcc
559 ; VI-NEXT: v_xor_b32_e32 v4, v10, v5
560 ; VI-NEXT: v_xor_b32_e32 v8, v9, v5
561 ; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v5
562 ; VI-NEXT: v_subb_u32_e32 v5, vcc, v8, v5, vcc
563 ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
564 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
565 ; VI-NEXT: s_endpgm
566 ;
567 ; EG-LABEL: fp_to_sint_v4i64:
568 ; EG: ; %bb.0:
569 ; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
570 ; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[]
571 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
572 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
573 ; EG-NEXT: CF_END
574 ; EG-NEXT: PAD
575 ; EG-NEXT: ALU clause starting at 6:
576 ; EG-NEXT: MOV * T0.W, literal.x,
577 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
578 ; EG-NEXT: BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
579 ; EG-NEXT: AND_INT * T2.W, KC0[4].X, literal.y,
580 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
581 ; EG-NEXT: OR_INT T0.Z, PS, literal.x,
582 ; EG-NEXT: BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
583 ; EG-NEXT: ADD_INT * T3.W, PV.W, literal.z,
584 ; EG-NEXT: 8388608(1.175494e-38), 23(3.222986e-44)
585 ; EG-NEXT: -150(nan), 0(0.000000e+00)
586 ; EG-NEXT: ADD_INT T0.Y, PV.W, literal.x,
587 ; EG-NEXT: AND_INT T1.Z, PS, literal.y,
588 ; EG-NEXT: NOT_INT T4.W, PS,
589 ; EG-NEXT: LSHR * T5.W, PV.Z, 1,
590 ; EG-NEXT: -127(nan), 31(4.344025e-44)
591 ; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,
592 ; EG-NEXT: BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
593 ; EG-NEXT: AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
594 ; EG-NEXT: LSHL T3.W, T0.Z, PV.Z,
595 ; EG-NEXT: SUB_INT * T1.W, literal.z, T1.W,
596 ; EG-NEXT: -127(nan), 32(4.484155e-44)
597 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
598 ; EG-NEXT: AND_INT T1.X, PS, literal.x,
599 ; EG-NEXT: BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
600 ; EG-NEXT: AND_INT T0.Z, KC0[3].Z, literal.y,
601 ; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
602 ; EG-NEXT: SETGT_INT * T4.W, PV.X, literal.z,
603 ; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38)
604 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
605 ; EG-NEXT: CNDE_INT T2.X, PS, 0.0, PV.W,
606 ; EG-NEXT: OR_INT T1.Y, PV.Z, literal.x,
607 ; EG-NEXT: ADD_INT T0.Z, T2.W, literal.y,
608 ; EG-NEXT: CNDE_INT T1.W, PV.X, PV.Y, 0.0,
609 ; EG-NEXT: CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
610 ; EG-NEXT: 8388608(1.175494e-38), -150(nan)
611 ; EG-NEXT: CNDE_INT T1.X, T4.W, PV.W, PS,
612 ; EG-NEXT: ASHR T2.Y, KC0[4].X, literal.x,
613 ; EG-NEXT: AND_INT T1.Z, PV.Z, literal.x,
614 ; EG-NEXT: NOT_INT T1.W, PV.Z,
615 ; EG-NEXT: LSHR * T3.W, PV.Y, 1,
616 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
617 ; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
618 ; EG-NEXT: LSHL T3.Y, T1.Y, PV.Z,
619 ; EG-NEXT: XOR_INT T1.Z, PV.X, PV.Y,
620 ; EG-NEXT: XOR_INT T1.W, T2.X, PV.Y,
621 ; EG-NEXT: SUB_INT * T2.W, literal.x, T2.W,
622 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
623 ; EG-NEXT: AND_INT T1.X, T0.Z, literal.x,
624 ; EG-NEXT: AND_INT T4.Y, PS, literal.x,
625 ; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
626 ; EG-NEXT: SUB_INT T1.W, PV.W, T2.Y,
627 ; EG-NEXT: SUBB_UINT * T2.W, PV.Z, T2.Y,
628 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
629 ; EG-NEXT: SUB_INT T2.X, PV.W, PS,
630 ; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
631 ; EG-NEXT: CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
632 ; EG-NEXT: CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
633 ; EG-NEXT: SETGT_INT * T2.W, T0.Y, literal.x,
634 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
635 ; EG-NEXT: BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
636 ; EG-NEXT: AND_INT T3.Y, KC0[3].W, literal.y,
637 ; EG-NEXT: CNDE_INT T2.Z, PS, 0.0, PV.W,
638 ; EG-NEXT: CNDE_INT T1.W, PS, PV.Y, PV.Z,
639 ; EG-NEXT: ASHR * T2.W, KC0[3].Z, literal.z,
640 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
641 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
642 ; EG-NEXT: BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
643 ; EG-NEXT: XOR_INT T1.Y, PV.W, PS,
644 ; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
645 ; EG-NEXT: OR_INT T0.W, PV.Y, literal.y,
646 ; EG-NEXT: SUB_INT * T1.W, literal.z, PV.X,
647 ; EG-NEXT: 23(3.222986e-44), 8388608(1.175494e-38)
648 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
649 ; EG-NEXT: AND_INT T4.X, KC0[3].Y, literal.x,
650 ; EG-NEXT: AND_INT T3.Y, PS, literal.y,
651 ; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
652 ; EG-NEXT: SUB_INT T1.W, PV.Z, T2.W,
653 ; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
654 ; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
655 ; EG-NEXT: SUB_INT T5.X, PV.W, PS,
656 ; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
657 ; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
658 ; EG-NEXT: OR_INT T1.W, PV.X, literal.y,
659 ; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z,
660 ; EG-NEXT: -1(nan), 8388608(1.175494e-38)
661 ; EG-NEXT: -150(nan), 0(0.000000e+00)
662 ; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
663 ; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
664 ; EG-NEXT: AND_INT T2.Z, PS, literal.z,
665 ; EG-NEXT: NOT_INT T4.W, PS,
666 ; EG-NEXT: LSHR * T5.W, PV.W, 1,
667 ; EG-NEXT: -127(nan), 150(2.101948e-43)
668 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
669 ; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
670 ; EG-NEXT: LSHL T4.Y, T1.W, PV.Z,
671 ; EG-NEXT: AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
672 ; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
673 ; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
674 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
675 ; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
676 ; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0,
677 ; EG-NEXT: -150(nan), 0(0.000000e+00)
678 ; EG-NEXT: ALU clause starting at 108:
679 ; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0,
680 ; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
681 ; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
682 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
683 ; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
684 ; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z,
685 ; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
686 ; EG-NEXT: NOT_INT T1.W, T6.X,
687 ; EG-NEXT: LSHR * T3.W, T0.W, 1,
688 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
689 ; EG-NEXT: ASHR T7.X, KC0[3].Y, literal.x,
690 ; EG-NEXT: ADD_INT T4.Y, T1.X, literal.y,
691 ; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
692 ; EG-NEXT: LSHL T0.W, T0.W, PV.Z,
693 ; EG-NEXT: AND_INT * T1.W, T6.X, literal.z,
694 ; EG-NEXT: 31(4.344025e-44), -127(nan)
695 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
696 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
697 ; EG-NEXT: CNDE_INT T5.Y, PS, PV.Z, PV.W,
698 ; EG-NEXT: SETGT_INT T2.Z, PV.Y, literal.x,
699 ; EG-NEXT: XOR_INT T0.W, T3.Y, PV.X,
700 ; EG-NEXT: XOR_INT * T1.W, T3.X, PV.X,
701 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
702 ; EG-NEXT: SUB_INT T3.X, PS, T7.X,
703 ; EG-NEXT: SUBB_UINT T3.Y, PV.W, T7.X,
704 ; EG-NEXT: CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
705 ; EG-NEXT: CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
706 ; EG-NEXT: ASHR * T3.W, KC0[3].W, literal.x,
707 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
708 ; EG-NEXT: XOR_INT T1.X, PV.W, PS,
709 ; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
710 ; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
711 ; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x,
712 ; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122
713 ; EG-NEXT: -1(nan), 0(0.000000e+00)
714 ; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x,
715 ; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z,
716 ; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
717 ; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
718 ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
719 ; EG-NEXT: -1(nan), 0(0.000000e+00)
720 ; EG-NEXT: SUB_INT T3.X, PV.W, PS,
721 ; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x,
722 ; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212
723 ; EG-NEXT: SUB_INT T0.W, T0.W, T7.X,
724 ; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122
725 ; EG-NEXT: -1(nan), 0(0.000000e+00)
726 ; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W,
727 ; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X,
728 ; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
729 ; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
730 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
731 ; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W,
732 ; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
733 ; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W,
734 ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
735 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
736 ; EG-NEXT: LSHR * T0.X, PV.W, literal.x,
737 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
738 %conv = fptosi <4 x float> %x to <4 x i64>
739 store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
740 ret void
741 }
743 define amdgpu_kernel void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
744 ; SI-LABEL: fp_to_uint_f32_to_i1:
745 ; SI: ; %bb.0:
746 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
747 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
748 ; SI-NEXT: s_mov_b32 s3, 0xf000
749 ; SI-NEXT: s_mov_b32 s2, -1
750 ; SI-NEXT: s_waitcnt lgkmcnt(0)
751 ; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s4
752 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
753 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
754 ; SI-NEXT: s_endpgm
755 ;
756 ; VI-LABEL: fp_to_uint_f32_to_i1:
757 ; VI: ; %bb.0:
758 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
759 ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
760 ; VI-NEXT: s_mov_b32 s7, 0xf000
761 ; VI-NEXT: s_mov_b32 s6, -1
762 ; VI-NEXT: s_waitcnt lgkmcnt(0)
763 ; VI-NEXT: v_cmp_eq_f32_e64 s[0:1], -1.0, s0
764 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
765 ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0
766 ; VI-NEXT: s_endpgm
767 ;
768 ; EG-LABEL: fp_to_uint_f32_to_i1:
769 ; EG: ; %bb.0:
770 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
771 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
772 ; EG-NEXT: CF_END
773 ; EG-NEXT: PAD
774 ; EG-NEXT: ALU clause starting at 4:
775 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
776 ; EG-NEXT: SETE_DX10 * T1.W, KC0[2].Z, literal.y,
777 ; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)
778 ; EG-NEXT: AND_INT T1.W, PS, 1,
779 ; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
780 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
781 ; EG-NEXT: LSHL T0.X, PV.W, PS,
782 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
783 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
784 ; EG-NEXT: MOV T0.Y, 0.0,
785 ; EG-NEXT: MOV * T0.Z, 0.0,
786 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
787 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
788 %conv = fptosi float %in to i1
789 store i1 %conv, i1 addrspace(1)* %out
790 ret void
791 }
793 define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
794 ; SI-LABEL: fp_to_uint_fabs_f32_to_i1:
795 ; SI: ; %bb.0:
796 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
797 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
798 ; SI-NEXT: s_mov_b32 s3, 0xf000
799 ; SI-NEXT: s_mov_b32 s2, -1
800 ; SI-NEXT: s_waitcnt lgkmcnt(0)
801 ; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s4|
802 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
803 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
804 ; SI-NEXT: s_endpgm
805 ;
806 ; VI-LABEL: fp_to_uint_fabs_f32_to_i1:
807 ; VI: ; %bb.0:
808 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
809 ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
810 ; VI-NEXT: s_mov_b32 s7, 0xf000
811 ; VI-NEXT: s_mov_b32 s6, -1
812 ; VI-NEXT: s_waitcnt lgkmcnt(0)
813 ; VI-NEXT: v_cmp_eq_f32_e64 s[0:1], -1.0, |s0|
814 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
815 ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0
816 ; VI-NEXT: s_endpgm
817 ;
818 ; EG-LABEL: fp_to_uint_fabs_f32_to_i1:
819 ; EG: ; %bb.0:
820 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
821 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
822 ; EG-NEXT: CF_END
823 ; EG-NEXT: PAD
824 ; EG-NEXT: ALU clause starting at 4:
825 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
826 ; EG-NEXT: SETE_DX10 * T1.W, |KC0[2].Z|, literal.y,
827 ; EG-NEXT: 3(4.203895e-45), -1082130432(-1.000000e+00)
828 ; EG-NEXT: AND_INT T1.W, PS, 1,
829 ; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
830 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
831 ; EG-NEXT: LSHL T0.X, PV.W, PS,
832 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
833 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
834 ; EG-NEXT: MOV T0.Y, 0.0,
835 ; EG-NEXT: MOV * T0.Z, 0.0,
836 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
837 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
838 %in.fabs = call float @llvm.fabs.f32(float %in)
839 %conv = fptosi float %in.fabs to i1
840 store i1 %conv, i1 addrspace(1)* %out
841 ret void
842 }
844 define amdgpu_kernel void @fp_to_sint_f32_i16(i16 addrspace(1)* %out, float %in) #0 {
845 ; SI-LABEL: fp_to_sint_f32_i16:
846 ; SI: ; %bb.0:
847 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
848 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
849 ; SI-NEXT: s_mov_b32 s3, 0xf000
850 ; SI-NEXT: s_mov_b32 s2, -1
851 ; SI-NEXT: s_waitcnt lgkmcnt(0)
852 ; SI-NEXT: v_cvt_i32_f32_e32 v0, s4
853 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
854 ; SI-NEXT: s_endpgm
855 ;
856 ; VI-LABEL: fp_to_sint_f32_i16:
857 ; VI: ; %bb.0:
858 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
859 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
860 ; VI-NEXT: s_mov_b32 s3, 0xf000
861 ; VI-NEXT: s_waitcnt lgkmcnt(0)
862 ; VI-NEXT: v_cvt_i32_f32_e32 v0, s2
863 ; VI-NEXT: s_mov_b32 s2, -1
864 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
865 ; VI-NEXT: s_endpgm
866 ;
867 ; EG-LABEL: fp_to_sint_f32_i16:
868 ; EG: ; %bb.0:
869 ; EG-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
870 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
871 ; EG-NEXT: CF_END
872 ; EG-NEXT: PAD
873 ; EG-NEXT: ALU clause starting at 4:
874 ; EG-NEXT: TRUNC T0.W, KC0[2].Z,
875 ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
876 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
877 ; EG-NEXT: FLT_TO_INT * T0.W, PV.W,
878 ; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
879 ; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
880 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
881 ; EG-NEXT: LSHL T0.X, PV.W, PS,
882 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
883 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
884 ; EG-NEXT: MOV T0.Y, 0.0,
885 ; EG-NEXT: MOV * T0.Z, 0.0,
886 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
887 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
888 %sint = fptosi float %in to i16
889 store i16 %sint, i16 addrspace(1)* %out
890 ret void
891 }
893 attributes #0 = { nounwind }
894 attributes #1 = { nounwind readnone }