| blob | 538fcf2bb54918671d62a4fdad37bc147759f11e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
4 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG
6 declare float @llvm.fabs.f32(float) #1
8 define amdgpu_kernel void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) {
9 ; SI-LABEL: fp_to_uint_f32_to_i32:
10 ; SI: ; %bb.0:
11 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
12 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
13 ; SI-NEXT: s_mov_b32 s3, 0xf000
14 ; SI-NEXT: s_mov_b32 s2, -1
15 ; SI-NEXT: s_waitcnt lgkmcnt(0)
16 ; SI-NEXT: v_cvt_u32_f32_e32 v0, s4
17 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
18 ; SI-NEXT: s_endpgm
19 ;
20 ; VI-LABEL: fp_to_uint_f32_to_i32:
21 ; VI: ; %bb.0:
22 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
23 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
24 ; VI-NEXT: s_mov_b32 s3, 0xf000
25 ; VI-NEXT: s_waitcnt lgkmcnt(0)
26 ; VI-NEXT: v_cvt_u32_f32_e32 v0, s2
27 ; VI-NEXT: s_mov_b32 s2, -1
28 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
29 ; VI-NEXT: s_endpgm
30 ;
31 ; EG-LABEL: fp_to_uint_f32_to_i32:
32 ; EG: ; %bb.0:
33 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
34 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
35 ; EG-NEXT: CF_END
36 ; EG-NEXT: PAD
37 ; EG-NEXT: ALU clause starting at 4:
38 ; EG-NEXT: TRUNC * T0.W, KC0[2].Z,
39 ; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
40 ; EG-NEXT: FLT_TO_UINT * T1.X, PV.W,
41 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
42 %conv = fptoui float %in to i32
43 store i32 %conv, i32 addrspace(1)* %out
44 ret void
45 }
47 define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
48 ; SI-LABEL: fp_to_uint_v2f32_to_v2i32:
49 ; SI: ; %bb.0:
50 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
51 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
52 ; SI-NEXT: s_mov_b32 s3, 0xf000
53 ; SI-NEXT: s_mov_b32 s2, -1
54 ; SI-NEXT: s_waitcnt lgkmcnt(0)
55 ; SI-NEXT: v_cvt_u32_f32_e32 v1, s5
56 ; SI-NEXT: v_cvt_u32_f32_e32 v0, s4
57 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
58 ; SI-NEXT: s_endpgm
59 ;
60 ; VI-LABEL: fp_to_uint_v2f32_to_v2i32:
61 ; VI: ; %bb.0:
62 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
63 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
64 ; VI-NEXT: s_waitcnt lgkmcnt(0)
65 ; VI-NEXT: v_cvt_u32_f32_e32 v1, s3
66 ; VI-NEXT: v_cvt_u32_f32_e32 v0, s2
67 ; VI-NEXT: s_mov_b32 s3, 0xf000
68 ; VI-NEXT: s_mov_b32 s2, -1
69 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
70 ; VI-NEXT: s_endpgm
71 ;
72 ; EG-LABEL: fp_to_uint_v2f32_to_v2i32:
73 ; EG: ; %bb.0:
74 ; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
75 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
76 ; EG-NEXT: CF_END
77 ; EG-NEXT: PAD
78 ; EG-NEXT: ALU clause starting at 4:
79 ; EG-NEXT: TRUNC T0.W, KC0[3].X,
80 ; EG-NEXT: TRUNC * T1.W, KC0[2].W,
81 ; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W,
82 ; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
83 ; EG-NEXT: FLT_TO_UINT * T0.X, T1.W,
84 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
85 %result = fptoui <2 x float> %in to <2 x i32>
86 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
87 ret void
88 }
90 define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
91 ; SI-LABEL: fp_to_uint_v4f32_to_v4i32:
92 ; SI: ; %bb.0:
93 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
94 ; SI-NEXT: s_waitcnt lgkmcnt(0)
95 ; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
96 ; SI-NEXT: s_mov_b32 s3, 0xf000
97 ; SI-NEXT: s_mov_b32 s2, -1
98 ; SI-NEXT: s_waitcnt lgkmcnt(0)
99 ; SI-NEXT: v_cvt_u32_f32_e32 v3, s7
100 ; SI-NEXT: v_cvt_u32_f32_e32 v2, s6
101 ; SI-NEXT: v_cvt_u32_f32_e32 v1, s5
102 ; SI-NEXT: v_cvt_u32_f32_e32 v0, s4
103 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
104 ; SI-NEXT: s_endpgm
105 ;
106 ; VI-LABEL: fp_to_uint_v4f32_to_v4i32:
107 ; VI: ; %bb.0:
108 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
109 ; VI-NEXT: s_waitcnt lgkmcnt(0)
110 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
111 ; VI-NEXT: s_mov_b32 s3, 0xf000
112 ; VI-NEXT: s_mov_b32 s2, -1
113 ; VI-NEXT: s_waitcnt lgkmcnt(0)
114 ; VI-NEXT: v_cvt_u32_f32_e32 v3, s7
115 ; VI-NEXT: v_cvt_u32_f32_e32 v2, s6
116 ; VI-NEXT: v_cvt_u32_f32_e32 v1, s5
117 ; VI-NEXT: v_cvt_u32_f32_e32 v0, s4
118 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
119 ; VI-NEXT: s_endpgm
120 ;
121 ; EG-LABEL: fp_to_uint_v4f32_to_v4i32:
122 ; EG: ; %bb.0:
123 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
124 ; EG-NEXT: TEX 0 @6
125 ; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]
126 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
127 ; EG-NEXT: CF_END
128 ; EG-NEXT: PAD
129 ; EG-NEXT: Fetch clause starting at 6:
130 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
131 ; EG-NEXT: ALU clause starting at 8:
132 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
133 ; EG-NEXT: ALU clause starting at 9:
134 ; EG-NEXT: TRUNC T0.W, T0.W,
135 ; EG-NEXT: TRUNC * T1.W, T0.Z,
136 ; EG-NEXT: FLT_TO_UINT * T0.W, PV.W,
137 ; EG-NEXT: TRUNC T2.W, T0.Y,
138 ; EG-NEXT: FLT_TO_UINT * T0.Z, T1.W,
139 ; EG-NEXT: TRUNC T1.W, T0.X,
140 ; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W,
141 ; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
142 ; EG-NEXT: FLT_TO_UINT * T0.X, PV.W,
143 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
144 %value = load <4 x float>, <4 x float> addrspace(1) * %in
145 %result = fptoui <4 x float> %value to <4 x i32>
146 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
147 ret void
148 }
150 define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) {
151 ; SI-LABEL: fp_to_uint_f32_to_i64:
152 ; SI: ; %bb.0:
153 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
154 ; SI-NEXT: s_load_dword s0, s[0:1], 0xb
155 ; SI-NEXT: s_mov_b32 s7, 0xf000
156 ; SI-NEXT: s_mov_b32 s6, -1
157 ; SI-NEXT: s_mov_b32 s1, 0xcf800000
158 ; SI-NEXT: s_waitcnt lgkmcnt(0)
159 ; SI-NEXT: v_trunc_f32_e32 v0, s0
160 ; SI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
161 ; SI-NEXT: v_floor_f32_e32 v2, v1
162 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v2
163 ; SI-NEXT: v_fma_f32 v0, v2, s1, v0
164 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
165 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
166 ; SI-NEXT: s_endpgm
167 ;
168 ; VI-LABEL: fp_to_uint_f32_to_i64:
169 ; VI: ; %bb.0:
170 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
171 ; VI-NEXT: s_mov_b32 s3, 0xcf800000
172 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
173 ; VI-NEXT: s_waitcnt lgkmcnt(0)
174 ; VI-NEXT: v_trunc_f32_e32 v0, s2
175 ; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
176 ; VI-NEXT: v_floor_f32_e32 v2, v1
177 ; VI-NEXT: v_fma_f32 v0, v2, s3, v0
178 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v2
179 ; VI-NEXT: v_cvt_u32_f32_e32 v0, v0
180 ; VI-NEXT: s_mov_b32 s3, 0xf000
181 ; VI-NEXT: s_mov_b32 s2, -1
182 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
183 ; VI-NEXT: s_endpgm
184 ;
185 ; EG-LABEL: fp_to_uint_f32_to_i64:
186 ; EG: ; %bb.0:
187 ; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[]
188 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
189 ; EG-NEXT: CF_END
190 ; EG-NEXT: PAD
191 ; EG-NEXT: ALU clause starting at 4:
192 ; EG-NEXT: MOV * T0.W, literal.x,
193 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
194 ; EG-NEXT: BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
195 ; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.y,
196 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
197 ; EG-NEXT: OR_INT T1.W, PS, literal.x,
198 ; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,
199 ; EG-NEXT: 8388608(1.175494e-38), -150(nan)
200 ; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,
201 ; EG-NEXT: SUB_INT T0.Y, literal.y, T0.W,
202 ; EG-NEXT: AND_INT T0.Z, PS, literal.z,
203 ; EG-NEXT: NOT_INT T0.W, PS,
204 ; EG-NEXT: LSHR * T3.W, PV.W, 1,
205 ; EG-NEXT: -127(nan), 150(2.101948e-43)
206 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
207 ; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
208 ; EG-NEXT: LSHL T1.Y, T1.W, PV.Z,
209 ; EG-NEXT: AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
210 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
211 ; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,
212 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
213 ; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
214 ; EG-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
215 ; EG-NEXT: CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
216 ; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,
217 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
218 ; EG-NEXT: CNDE_INT T0.Z, PS, 0.0, PV.W,
219 ; EG-NEXT: CNDE_INT T0.W, PS, PV.Y, PV.Z,
220 ; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,
221 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
222 ; EG-NEXT: XOR_INT T0.W, PV.W, PS,
223 ; EG-NEXT: XOR_INT * T2.W, PV.Z, PS,
224 ; EG-NEXT: SUB_INT T2.W, PS, T1.W,
225 ; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
226 ; EG-NEXT: SUB_INT T2.W, PV.W, PS,
227 ; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x,
228 ; EG-NEXT: -1(nan), 0(0.000000e+00)
229 ; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W,
230 ; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
231 ; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W,
232 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
233 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
234 %conv = fptoui float %x to i64
235 store i64 %conv, i64 addrspace(1)* %out
236 ret void
237 }
239 define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
240 ; SI-LABEL: fp_to_uint_v2f32_to_v2i64:
241 ; SI: ; %bb.0:
242 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
243 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
244 ; SI-NEXT: s_mov_b32 s7, 0xf000
245 ; SI-NEXT: s_mov_b32 s6, -1
246 ; SI-NEXT: s_mov_b32 s2, 0x2f800000
247 ; SI-NEXT: s_mov_b32 s3, 0xcf800000
248 ; SI-NEXT: s_waitcnt lgkmcnt(0)
249 ; SI-NEXT: v_trunc_f32_e32 v0, s1
250 ; SI-NEXT: v_trunc_f32_e32 v2, s0
251 ; SI-NEXT: v_mul_f32_e32 v1, s2, v0
252 ; SI-NEXT: v_mul_f32_e32 v3, s2, v2
253 ; SI-NEXT: v_floor_f32_e32 v4, v1
254 ; SI-NEXT: v_floor_f32_e32 v5, v3
255 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v4
256 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v5
257 ; SI-NEXT: v_fma_f32 v0, v4, s3, v0
258 ; SI-NEXT: v_fma_f32 v4, v5, s3, v2
259 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v0
260 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v4
261 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
262 ; SI-NEXT: s_endpgm
263 ;
264 ; VI-LABEL: fp_to_uint_v2f32_to_v2i64:
265 ; VI: ; %bb.0:
266 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
267 ; VI-NEXT: s_mov_b32 s4, 0x2f800000
268 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
269 ; VI-NEXT: s_waitcnt lgkmcnt(0)
270 ; VI-NEXT: v_trunc_f32_e32 v0, s3
271 ; VI-NEXT: v_trunc_f32_e32 v4, s2
272 ; VI-NEXT: v_mul_f32_e32 v1, s4, v0
273 ; VI-NEXT: v_mul_f32_e32 v2, s4, v4
274 ; VI-NEXT: v_floor_f32_e32 v5, v1
275 ; VI-NEXT: s_mov_b32 s2, 0xcf800000
276 ; VI-NEXT: v_floor_f32_e32 v6, v2
277 ; VI-NEXT: v_fma_f32 v0, v5, s2, v0
278 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v0
279 ; VI-NEXT: v_fma_f32 v0, v6, s2, v4
280 ; VI-NEXT: v_cvt_u32_f32_e32 v3, v5
281 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v6
282 ; VI-NEXT: v_cvt_u32_f32_e32 v0, v0
283 ; VI-NEXT: s_mov_b32 s3, 0xf000
284 ; VI-NEXT: s_mov_b32 s2, -1
285 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
286 ; VI-NEXT: s_endpgm
287 ;
288 ; EG-LABEL: fp_to_uint_v2f32_to_v2i64:
289 ; EG: ; %bb.0:
290 ; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[]
291 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
292 ; EG-NEXT: CF_END
293 ; EG-NEXT: PAD
294 ; EG-NEXT: ALU clause starting at 4:
295 ; EG-NEXT: MOV * T0.W, literal.x,
296 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
297 ; EG-NEXT: BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
298 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
299 ; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
300 ; EG-NEXT: BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
301 ; EG-NEXT: ADD_INT * T2.W, PV.W, literal.z,
302 ; EG-NEXT: 8388607(1.175494e-38), 23(3.222986e-44)
303 ; EG-NEXT: -150(nan), 0(0.000000e+00)
304 ; EG-NEXT: SUB_INT T0.X, literal.x, PV.W,
305 ; EG-NEXT: SUB_INT T0.Y, literal.x, T1.W,
306 ; EG-NEXT: AND_INT T1.Z, PS, literal.y,
307 ; EG-NEXT: OR_INT T3.W, PV.Z, literal.z,
308 ; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,
309 ; EG-NEXT: 150(2.101948e-43), 31(4.344025e-44)
310 ; EG-NEXT: 8388608(1.175494e-38), 8388607(1.175494e-38)
311 ; EG-NEXT: OR_INT T1.X, PS, literal.x,
312 ; EG-NEXT: LSHL T1.Y, PV.W, PV.Z,
313 ; EG-NEXT: AND_INT T0.Z, T2.W, literal.y,
314 ; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
315 ; EG-NEXT: AND_INT * T5.W, PV.Y, literal.y,
316 ; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)
317 ; EG-NEXT: CNDE_INT T2.X, PS, PV.W, 0.0,
318 ; EG-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
319 ; EG-NEXT: ADD_INT T1.Z, T0.W, literal.x,
320 ; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
321 ; EG-NEXT: AND_INT * T5.W, T0.X, literal.y,
322 ; EG-NEXT: -150(nan), 32(4.484155e-44)
323 ; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,
324 ; EG-NEXT: NOT_INT T2.Y, T2.W,
325 ; EG-NEXT: AND_INT T2.Z, PV.Z, literal.x,
326 ; EG-NEXT: NOT_INT T2.W, PV.Z,
327 ; EG-NEXT: LSHR * T4.W, T1.X, 1,
328 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
329 ; EG-NEXT: LSHR T3.X, T3.W, 1,
330 ; EG-NEXT: ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
331 ; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
332 ; EG-NEXT: LSHL T0.W, T1.X, PV.Z,
333 ; EG-NEXT: AND_INT * T2.W, T1.Z, literal.y,
334 ; EG-NEXT: -127(nan), 32(4.484155e-44)
335 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
336 ; EG-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W,
337 ; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
338 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
339 ; EG-NEXT: ADD_INT * T1.W, T1.W, literal.y,
340 ; EG-NEXT: 23(3.222986e-44), -127(nan)
341 ; EG-NEXT: CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
342 ; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,
343 ; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
344 ; EG-NEXT: CNDE_INT T0.W, PV.Z, T0.X, PV.X,
345 ; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,
346 ; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)
347 ; EG-NEXT: XOR_INT T0.X, PV.W, PS,
348 ; EG-NEXT: XOR_INT T2.Y, PV.Z, PS,
349 ; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
350 ; EG-NEXT: CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
351 ; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,
352 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
353 ; EG-NEXT: XOR_INT T0.Y, PV.W, PS,
354 ; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
355 ; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
356 ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
357 ; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
358 ; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x,
359 ; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
360 ; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
361 ; EG-NEXT: -1(nan), 0(0.000000e+00)
362 ; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
363 ; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x,
364 ; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122
365 ; EG-NEXT: -1(nan), 0(0.000000e+00)
366 ; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z,
367 ; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
368 ; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W,
369 ; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
370 ; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W,
371 ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
372 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
373 %conv = fptoui <2 x float> %x to <2 x i64>
374 store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
375 ret void
376 }
378 define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
379 ; SI-LABEL: fp_to_uint_v4f32_to_v4i64:
380 ; SI: ; %bb.0:
381 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
382 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
383 ; SI-NEXT: s_mov_b32 s7, 0xf000
384 ; SI-NEXT: s_mov_b32 s6, -1
385 ; SI-NEXT: s_mov_b32 s8, 0x2f800000
386 ; SI-NEXT: s_mov_b32 s9, 0xcf800000
387 ; SI-NEXT: s_waitcnt lgkmcnt(0)
388 ; SI-NEXT: v_trunc_f32_e32 v0, s1
389 ; SI-NEXT: v_trunc_f32_e32 v2, s0
390 ; SI-NEXT: v_trunc_f32_e32 v4, s3
391 ; SI-NEXT: v_trunc_f32_e32 v6, s2
392 ; SI-NEXT: v_mul_f32_e32 v1, s8, v0
393 ; SI-NEXT: v_mul_f32_e32 v3, s8, v2
394 ; SI-NEXT: v_mul_f32_e32 v5, s8, v4
395 ; SI-NEXT: v_mul_f32_e32 v7, s8, v6
396 ; SI-NEXT: v_floor_f32_e32 v8, v1
397 ; SI-NEXT: v_floor_f32_e32 v9, v3
398 ; SI-NEXT: v_floor_f32_e32 v10, v5
399 ; SI-NEXT: v_floor_f32_e32 v11, v7
400 ; SI-NEXT: v_cvt_u32_f32_e32 v3, v8
401 ; SI-NEXT: v_cvt_u32_f32_e32 v1, v9
402 ; SI-NEXT: v_fma_f32 v0, v8, s9, v0
403 ; SI-NEXT: v_fma_f32 v8, v9, s9, v2
404 ; SI-NEXT: v_cvt_u32_f32_e32 v7, v10
405 ; SI-NEXT: v_cvt_u32_f32_e32 v5, v11
406 ; SI-NEXT: v_fma_f32 v4, v10, s9, v4
407 ; SI-NEXT: v_fma_f32 v9, v11, s9, v6
408 ; SI-NEXT: v_cvt_u32_f32_e32 v2, v0
409 ; SI-NEXT: v_cvt_u32_f32_e32 v0, v8
410 ; SI-NEXT: v_cvt_u32_f32_e32 v6, v4
411 ; SI-NEXT: v_cvt_u32_f32_e32 v4, v9
412 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
413 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
414 ; SI-NEXT: s_endpgm
415 ;
416 ; VI-LABEL: fp_to_uint_v4f32_to_v4i64:
417 ; VI: ; %bb.0:
418 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
419 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
420 ; VI-NEXT: s_mov_b32 s6, 0x2f800000
421 ; VI-NEXT: s_mov_b32 s7, 0xf000
422 ; VI-NEXT: s_waitcnt lgkmcnt(0)
423 ; VI-NEXT: v_trunc_f32_e32 v0, s1
424 ; VI-NEXT: v_trunc_f32_e32 v4, s0
425 ; VI-NEXT: v_mul_f32_e32 v1, s6, v0
426 ; VI-NEXT: v_mul_f32_e32 v2, s6, v4
427 ; VI-NEXT: v_floor_f32_e32 v5, v1
428 ; VI-NEXT: s_mov_b32 s0, 0xcf800000
429 ; VI-NEXT: v_floor_f32_e32 v6, v2
430 ; VI-NEXT: v_fma_f32 v0, v5, s0, v0
431 ; VI-NEXT: v_cvt_u32_f32_e32 v2, v0
432 ; VI-NEXT: v_fma_f32 v0, v6, s0, v4
433 ; VI-NEXT: v_trunc_f32_e32 v4, s3
434 ; VI-NEXT: v_cvt_u32_f32_e32 v3, v5
435 ; VI-NEXT: v_mul_f32_e32 v5, s6, v4
436 ; VI-NEXT: v_trunc_f32_e32 v8, s2
437 ; VI-NEXT: v_cvt_u32_f32_e32 v1, v6
438 ; VI-NEXT: v_floor_f32_e32 v6, v5
439 ; VI-NEXT: v_mul_f32_e32 v5, s6, v8
440 ; VI-NEXT: v_floor_f32_e32 v9, v5
441 ; VI-NEXT: v_fma_f32 v4, v6, s0, v4
442 ; VI-NEXT: v_cvt_u32_f32_e32 v7, v6
443 ; VI-NEXT: v_cvt_u32_f32_e32 v6, v4
444 ; VI-NEXT: v_fma_f32 v4, v9, s0, v8
445 ; VI-NEXT: v_cvt_u32_f32_e32 v5, v9
446 ; VI-NEXT: v_cvt_u32_f32_e32 v4, v4
447 ; VI-NEXT: v_cvt_u32_f32_e32 v0, v0
448 ; VI-NEXT: s_mov_b32 s6, -1
449 ; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
450 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
451 ; VI-NEXT: s_endpgm
452 ;
453 ; EG-LABEL: fp_to_uint_v4f32_to_v4i64:
454 ; EG: ; %bb.0:
455 ; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
456 ; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[]
457 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
458 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
459 ; EG-NEXT: CF_END
460 ; EG-NEXT: PAD
461 ; EG-NEXT: ALU clause starting at 6:
462 ; EG-NEXT: MOV * T0.W, literal.x,
463 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
464 ; EG-NEXT: BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
465 ; EG-NEXT: AND_INT * T2.W, KC0[4].X, literal.y,
466 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
467 ; EG-NEXT: OR_INT T0.Z, PS, literal.x,
468 ; EG-NEXT: BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
469 ; EG-NEXT: ADD_INT * T3.W, PV.W, literal.z,
470 ; EG-NEXT: 8388608(1.175494e-38), 23(3.222986e-44)
471 ; EG-NEXT: -150(nan), 0(0.000000e+00)
472 ; EG-NEXT: ADD_INT T0.Y, PV.W, literal.x,
473 ; EG-NEXT: AND_INT T1.Z, PS, literal.y,
474 ; EG-NEXT: NOT_INT T4.W, PS,
475 ; EG-NEXT: LSHR * T5.W, PV.Z, 1,
476 ; EG-NEXT: -127(nan), 31(4.344025e-44)
477 ; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,
478 ; EG-NEXT: BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
479 ; EG-NEXT: AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
480 ; EG-NEXT: LSHL T3.W, T0.Z, PV.Z,
481 ; EG-NEXT: SUB_INT * T1.W, literal.z, T1.W,
482 ; EG-NEXT: -127(nan), 32(4.484155e-44)
483 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
484 ; EG-NEXT: AND_INT T1.X, PS, literal.x,
485 ; EG-NEXT: BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
486 ; EG-NEXT: AND_INT T0.Z, KC0[3].Z, literal.y,
487 ; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
488 ; EG-NEXT: SETGT_INT * T4.W, PV.X, literal.z,
489 ; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38)
490 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
491 ; EG-NEXT: CNDE_INT T2.X, PS, 0.0, PV.W,
492 ; EG-NEXT: OR_INT T1.Y, PV.Z, literal.x,
493 ; EG-NEXT: ADD_INT T0.Z, T2.W, literal.y,
494 ; EG-NEXT: CNDE_INT T1.W, PV.X, PV.Y, 0.0,
495 ; EG-NEXT: CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
496 ; EG-NEXT: 8388608(1.175494e-38), -150(nan)
497 ; EG-NEXT: CNDE_INT T1.X, T4.W, PV.W, PS,
498 ; EG-NEXT: ASHR T2.Y, KC0[4].X, literal.x,
499 ; EG-NEXT: AND_INT T1.Z, PV.Z, literal.x,
500 ; EG-NEXT: NOT_INT T1.W, PV.Z,
501 ; EG-NEXT: LSHR * T3.W, PV.Y, 1,
502 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
503 ; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
504 ; EG-NEXT: LSHL T3.Y, T1.Y, PV.Z,
505 ; EG-NEXT: XOR_INT T1.Z, PV.X, PV.Y,
506 ; EG-NEXT: XOR_INT T1.W, T2.X, PV.Y,
507 ; EG-NEXT: SUB_INT * T2.W, literal.x, T2.W,
508 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
509 ; EG-NEXT: AND_INT T1.X, T0.Z, literal.x,
510 ; EG-NEXT: AND_INT T4.Y, PS, literal.x,
511 ; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
512 ; EG-NEXT: SUB_INT T1.W, PV.W, T2.Y,
513 ; EG-NEXT: SUBB_UINT * T2.W, PV.Z, T2.Y,
514 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
515 ; EG-NEXT: SUB_INT T2.X, PV.W, PS,
516 ; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
517 ; EG-NEXT: CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
518 ; EG-NEXT: CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
519 ; EG-NEXT: SETGT_INT * T2.W, T0.Y, literal.x,
520 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
521 ; EG-NEXT: BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
522 ; EG-NEXT: AND_INT T3.Y, KC0[3].W, literal.y,
523 ; EG-NEXT: CNDE_INT T2.Z, PS, 0.0, PV.W,
524 ; EG-NEXT: CNDE_INT T1.W, PS, PV.Y, PV.Z,
525 ; EG-NEXT: ASHR * T2.W, KC0[3].Z, literal.z,
526 ; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
527 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
528 ; EG-NEXT: BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
529 ; EG-NEXT: XOR_INT T1.Y, PV.W, PS,
530 ; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
531 ; EG-NEXT: OR_INT T0.W, PV.Y, literal.y,
532 ; EG-NEXT: SUB_INT * T1.W, literal.z, PV.X,
533 ; EG-NEXT: 23(3.222986e-44), 8388608(1.175494e-38)
534 ; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
535 ; EG-NEXT: AND_INT T4.X, KC0[3].Y, literal.x,
536 ; EG-NEXT: AND_INT T3.Y, PS, literal.y,
537 ; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
538 ; EG-NEXT: SUB_INT T1.W, PV.Z, T2.W,
539 ; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
540 ; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
541 ; EG-NEXT: SUB_INT T5.X, PV.W, PS,
542 ; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
543 ; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
544 ; EG-NEXT: OR_INT T1.W, PV.X, literal.y,
545 ; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z,
546 ; EG-NEXT: -1(nan), 8388608(1.175494e-38)
547 ; EG-NEXT: -150(nan), 0(0.000000e+00)
548 ; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
549 ; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
550 ; EG-NEXT: AND_INT T2.Z, PS, literal.z,
551 ; EG-NEXT: NOT_INT T4.W, PS,
552 ; EG-NEXT: LSHR * T5.W, PV.W, 1,
553 ; EG-NEXT: -127(nan), 150(2.101948e-43)
554 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
555 ; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
556 ; EG-NEXT: LSHL T4.Y, T1.W, PV.Z,
557 ; EG-NEXT: AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
558 ; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
559 ; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
560 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
561 ; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
562 ; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0,
563 ; EG-NEXT: -150(nan), 0(0.000000e+00)
564 ; EG-NEXT: ALU clause starting at 108:
565 ; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0,
566 ; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
567 ; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
568 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
569 ; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
570 ; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z,
571 ; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
572 ; EG-NEXT: NOT_INT T1.W, T6.X,
573 ; EG-NEXT: LSHR * T3.W, T0.W, 1,
574 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
575 ; EG-NEXT: ASHR T7.X, KC0[3].Y, literal.x,
576 ; EG-NEXT: ADD_INT T4.Y, T1.X, literal.y,
577 ; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
578 ; EG-NEXT: LSHL T0.W, T0.W, PV.Z,
579 ; EG-NEXT: AND_INT * T1.W, T6.X, literal.z,
580 ; EG-NEXT: 31(4.344025e-44), -127(nan)
581 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
582 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
583 ; EG-NEXT: CNDE_INT T5.Y, PS, PV.Z, PV.W,
584 ; EG-NEXT: SETGT_INT T2.Z, PV.Y, literal.x,
585 ; EG-NEXT: XOR_INT T0.W, T3.Y, PV.X,
586 ; EG-NEXT: XOR_INT * T1.W, T3.X, PV.X,
587 ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
588 ; EG-NEXT: SUB_INT T3.X, PS, T7.X,
589 ; EG-NEXT: SUBB_UINT T3.Y, PV.W, T7.X,
590 ; EG-NEXT: CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
591 ; EG-NEXT: CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
592 ; EG-NEXT: ASHR * T3.W, KC0[3].W, literal.x,
593 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
594 ; EG-NEXT: XOR_INT T1.X, PV.W, PS,
595 ; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
596 ; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
597 ; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x,
598 ; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122
599 ; EG-NEXT: -1(nan), 0(0.000000e+00)
600 ; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x,
601 ; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z,
602 ; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
603 ; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
604 ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
605 ; EG-NEXT: -1(nan), 0(0.000000e+00)
606 ; EG-NEXT: SUB_INT T3.X, PV.W, PS,
607 ; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x,
608 ; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212
609 ; EG-NEXT: SUB_INT T0.W, T0.W, T7.X,
610 ; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122
611 ; EG-NEXT: -1(nan), 0(0.000000e+00)
612 ; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W,
613 ; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X,
614 ; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
615 ; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
616 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
617 ; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W,
618 ; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
619 ; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W,
620 ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
621 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
622 ; EG-NEXT: LSHR * T0.X, PV.W, literal.x,
623 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
624 %conv = fptoui <4 x float> %x to <4 x i64>
625 store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
626 ret void
627 }
629 define amdgpu_kernel void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
630 ; SI-LABEL: fp_to_uint_f32_to_i1:
631 ; SI: ; %bb.0:
632 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
633 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
634 ; SI-NEXT: s_mov_b32 s3, 0xf000
635 ; SI-NEXT: s_mov_b32 s2, -1
636 ; SI-NEXT: s_waitcnt lgkmcnt(0)
637 ; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, s4
638 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
639 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
640 ; SI-NEXT: s_endpgm
641 ;
642 ; VI-LABEL: fp_to_uint_f32_to_i1:
643 ; VI: ; %bb.0:
644 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
645 ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
646 ; VI-NEXT: s_mov_b32 s7, 0xf000
647 ; VI-NEXT: s_mov_b32 s6, -1
648 ; VI-NEXT: s_waitcnt lgkmcnt(0)
649 ; VI-NEXT: v_cmp_eq_f32_e64 s[0:1], 1.0, s0
650 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
651 ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0
652 ; VI-NEXT: s_endpgm
653 ;
654 ; EG-LABEL: fp_to_uint_f32_to_i1:
655 ; EG: ; %bb.0:
656 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
657 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
658 ; EG-NEXT: CF_END
659 ; EG-NEXT: PAD
660 ; EG-NEXT: ALU clause starting at 4:
661 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
662 ; EG-NEXT: SETE_DX10 * T1.W, KC0[2].Z, 1.0,
663 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
664 ; EG-NEXT: AND_INT T1.W, PS, 1,
665 ; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
666 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
667 ; EG-NEXT: LSHL T0.X, PV.W, PS,
668 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
669 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
670 ; EG-NEXT: MOV T0.Y, 0.0,
671 ; EG-NEXT: MOV * T0.Z, 0.0,
672 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
673 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
674 %conv = fptoui float %in to i1
675 store i1 %conv, i1 addrspace(1)* %out
676 ret void
677 }
679 define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
680 ; SI-LABEL: fp_to_uint_fabs_f32_to_i1:
681 ; SI: ; %bb.0:
682 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
683 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
684 ; SI-NEXT: s_mov_b32 s3, 0xf000
685 ; SI-NEXT: s_mov_b32 s2, -1
686 ; SI-NEXT: s_waitcnt lgkmcnt(0)
687 ; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, |s4|
688 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
689 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
690 ; SI-NEXT: s_endpgm
691 ;
692 ; VI-LABEL: fp_to_uint_fabs_f32_to_i1:
693 ; VI: ; %bb.0:
694 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
695 ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
696 ; VI-NEXT: s_mov_b32 s7, 0xf000
697 ; VI-NEXT: s_mov_b32 s6, -1
698 ; VI-NEXT: s_waitcnt lgkmcnt(0)
699 ; VI-NEXT: v_cmp_eq_f32_e64 s[0:1], 1.0, |s0|
700 ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
701 ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0
702 ; VI-NEXT: s_endpgm
703 ;
704 ; EG-LABEL: fp_to_uint_fabs_f32_to_i1:
705 ; EG: ; %bb.0:
706 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
707 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
708 ; EG-NEXT: CF_END
709 ; EG-NEXT: PAD
710 ; EG-NEXT: ALU clause starting at 4:
711 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
712 ; EG-NEXT: SETE_DX10 * T1.W, |KC0[2].Z|, 1.0,
713 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
714 ; EG-NEXT: AND_INT T1.W, PS, 1,
715 ; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
716 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
717 ; EG-NEXT: LSHL T0.X, PV.W, PS,
718 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
719 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
720 ; EG-NEXT: MOV T0.Y, 0.0,
721 ; EG-NEXT: MOV * T0.Z, 0.0,
722 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
723 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
724 %in.fabs = call float @llvm.fabs.f32(float %in)
725 %conv = fptoui float %in.fabs to i1
726 store i1 %conv, i1 addrspace(1)* %out
727 ret void
728 }
730 define amdgpu_kernel void @fp_to_uint_f32_to_i16(i16 addrspace(1)* %out, float %in) #0 {
731 ; SI-LABEL: fp_to_uint_f32_to_i16:
732 ; SI: ; %bb.0:
733 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
734 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
735 ; SI-NEXT: s_mov_b32 s3, 0xf000
736 ; SI-NEXT: s_mov_b32 s2, -1
737 ; SI-NEXT: s_waitcnt lgkmcnt(0)
738 ; SI-NEXT: v_cvt_u32_f32_e32 v0, s4
739 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
740 ; SI-NEXT: s_endpgm
741 ;
742 ; VI-LABEL: fp_to_uint_f32_to_i16:
743 ; VI: ; %bb.0:
744 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
745 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
746 ; VI-NEXT: s_mov_b32 s3, 0xf000
747 ; VI-NEXT: s_waitcnt lgkmcnt(0)
748 ; VI-NEXT: v_cvt_u32_f32_e32 v0, s2
749 ; VI-NEXT: s_mov_b32 s2, -1
750 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
751 ; VI-NEXT: s_endpgm
752 ;
753 ; EG-LABEL: fp_to_uint_f32_to_i16:
754 ; EG: ; %bb.0:
755 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
756 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
757 ; EG-NEXT: CF_END
758 ; EG-NEXT: PAD
759 ; EG-NEXT: ALU clause starting at 4:
760 ; EG-NEXT: TRUNC T0.W, KC0[2].Z,
761 ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
762 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
763 ; EG-NEXT: LSHL T1.W, PS, literal.x,
764 ; EG-NEXT: FLT_TO_UINT * T0.X, PV.W,
765 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
766 ; EG-NEXT: LSHL T0.X, PS, PV.W,
767 ; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
768 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
769 ; EG-NEXT: MOV T0.Y, 0.0,
770 ; EG-NEXT: MOV * T0.Z, 0.0,
771 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
772 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
773 %uint = fptoui float %in to i16
774 store i16 %uint, i16 addrspace(1)* %out
775 ret void
776 }
778 attributes #0 = { nounwind }
779 attributes #1 = { nounwind readnone }