| blob | 0d8c3424cb837aba2ee6654b2bd477b168b036a1 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -verify-machineinstrs < %s | FileCheck --check-prefix=GFX7 %s
4 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=GFX6 %s
5 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
7 define <3 x i32> @load_lds_v3i32(<3 x i32> addrspace(3)* %ptr) {
8 ; GFX9-LABEL: load_lds_v3i32:
9 ; GFX9: ; %bb.0:
10 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11 ; GFX9-NEXT: ds_read_b96 v[0:2], v0
12 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
13 ; GFX9-NEXT: s_setpc_b64 s[30:31]
14 ;
15 ; GFX7-LABEL: load_lds_v3i32:
16 ; GFX7: ; %bb.0:
17 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
18 ; GFX7-NEXT: s_mov_b32 m0, -1
19 ; GFX7-NEXT: ds_read_b96 v[0:2], v0
20 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
21 ; GFX7-NEXT: s_setpc_b64 s[30:31]
22 ;
23 ; GFX6-LABEL: load_lds_v3i32:
24 ; GFX6: ; %bb.0:
25 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
26 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
27 ; GFX6-NEXT: s_mov_b32 m0, -1
28 ; GFX6-NEXT: ds_read_b32 v2, v1
29 ; GFX6-NEXT: ds_read_b64 v[0:1], v0
30 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
31 ; GFX6-NEXT: s_setpc_b64 s[30:31]
32 ;
33 ; GFX10-LABEL: load_lds_v3i32:
34 ; GFX10: ; %bb.0:
35 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
36 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
37 ; GFX10-NEXT: ds_read_b96 v[0:2], v0
38 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
39 ; GFX10-NEXT: s_setpc_b64 s[30:31]
40 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr
41 ret <3 x i32> %load
42 }
44 define <3 x i32> @load_lds_v3i32_align1(<3 x i32> addrspace(3)* %ptr) {
45 ; GFX9-LABEL: load_lds_v3i32_align1:
46 ; GFX9: ; %bb.0:
47 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
48 ; GFX9-NEXT: ds_read_u8 v1, v0
49 ; GFX9-NEXT: ds_read_u8 v2, v0 offset:1
50 ; GFX9-NEXT: ds_read_u8 v3, v0 offset:2
51 ; GFX9-NEXT: ds_read_u8 v4, v0 offset:3
52 ; GFX9-NEXT: ds_read_u8 v5, v0 offset:4
53 ; GFX9-NEXT: ds_read_u8 v6, v0 offset:5
54 ; GFX9-NEXT: ds_read_u8 v7, v0 offset:6
55 ; GFX9-NEXT: ds_read_u8 v8, v0 offset:7
56 ; GFX9-NEXT: ds_read_u8 v9, v0 offset:8
57 ; GFX9-NEXT: ds_read_u8 v10, v0 offset:9
58 ; GFX9-NEXT: ds_read_u8 v11, v0 offset:10
59 ; GFX9-NEXT: ds_read_u8 v12, v0 offset:11
60 ; GFX9-NEXT: s_waitcnt lgkmcnt(10)
61 ; GFX9-NEXT: v_lshl_or_b32 v0, v2, 8, v1
62 ; GFX9-NEXT: s_waitcnt lgkmcnt(8)
63 ; GFX9-NEXT: v_lshl_or_b32 v1, v4, 8, v3
64 ; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
65 ; GFX9-NEXT: s_waitcnt lgkmcnt(6)
66 ; GFX9-NEXT: v_lshl_or_b32 v1, v6, 8, v5
67 ; GFX9-NEXT: s_waitcnt lgkmcnt(4)
68 ; GFX9-NEXT: v_lshl_or_b32 v2, v8, 8, v7
69 ; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
70 ; GFX9-NEXT: s_waitcnt lgkmcnt(2)
71 ; GFX9-NEXT: v_lshl_or_b32 v2, v10, 8, v9
72 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
73 ; GFX9-NEXT: v_lshl_or_b32 v3, v12, 8, v11
74 ; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
75 ; GFX9-NEXT: s_setpc_b64 s[30:31]
76 ;
77 ; GFX7-LABEL: load_lds_v3i32_align1:
78 ; GFX7: ; %bb.0:
79 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
80 ; GFX7-NEXT: s_mov_b32 m0, -1
81 ; GFX7-NEXT: ds_read_u8 v1, v0 offset:7
82 ; GFX7-NEXT: ds_read_u8 v2, v0 offset:6
83 ; GFX7-NEXT: ds_read_u8 v4, v0 offset:5
84 ; GFX7-NEXT: ds_read_u8 v5, v0 offset:4
85 ; GFX7-NEXT: ds_read_u8 v3, v0 offset:3
86 ; GFX7-NEXT: ds_read_u8 v6, v0 offset:2
87 ; GFX7-NEXT: ds_read_u8 v7, v0 offset:1
88 ; GFX7-NEXT: ds_read_u8 v8, v0
89 ; GFX7-NEXT: s_waitcnt lgkmcnt(7)
90 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1
91 ; GFX7-NEXT: s_waitcnt lgkmcnt(5)
92 ; GFX7-NEXT: v_lshlrev_b32_e32 v4, 8, v4
93 ; GFX7-NEXT: v_or_b32_e32 v1, v1, v2
94 ; GFX7-NEXT: s_waitcnt lgkmcnt(4)
95 ; GFX7-NEXT: v_or_b32_e32 v4, v4, v5
96 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
97 ; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
98 ; GFX7-NEXT: ds_read_u8 v2, v0 offset:11
99 ; GFX7-NEXT: ds_read_u8 v4, v0 offset:10
100 ; GFX7-NEXT: ds_read_u8 v5, v0 offset:9
101 ; GFX7-NEXT: ds_read_u8 v0, v0 offset:8
102 ; GFX7-NEXT: s_waitcnt lgkmcnt(7)
103 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3
104 ; GFX7-NEXT: s_waitcnt lgkmcnt(5)
105 ; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7
106 ; GFX7-NEXT: v_or_b32_e32 v3, v3, v6
107 ; GFX7-NEXT: s_waitcnt lgkmcnt(3)
108 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v2
109 ; GFX7-NEXT: s_waitcnt lgkmcnt(2)
110 ; GFX7-NEXT: v_or_b32_e32 v2, v2, v4
111 ; GFX7-NEXT: s_waitcnt lgkmcnt(1)
112 ; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5
113 ; GFX7-NEXT: v_or_b32_e32 v7, v7, v8
114 ; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3
115 ; GFX7-NEXT: v_or_b32_e32 v3, v3, v7
116 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
117 ; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
118 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
119 ; GFX7-NEXT: v_or_b32_e32 v2, v2, v0
120 ; GFX7-NEXT: v_mov_b32_e32 v0, v3
121 ; GFX7-NEXT: s_setpc_b64 s[30:31]
122 ;
123 ; GFX6-LABEL: load_lds_v3i32_align1:
124 ; GFX6: ; %bb.0:
125 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
126 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 5, v0
127 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
128 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 7, v0
129 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 6, v0
130 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 9, v0
131 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 8, v0
132 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, 11, v0
133 ; GFX6-NEXT: s_mov_b32 m0, -1
134 ; GFX6-NEXT: ds_read_u8 v2, v2
135 ; GFX6-NEXT: ds_read_u8 v3, v3
136 ; GFX6-NEXT: ds_read_u8 v4, v4
137 ; GFX6-NEXT: ds_read_u8 v5, v5
138 ; GFX6-NEXT: ds_read_u8 v6, v6
139 ; GFX6-NEXT: ds_read_u8 v7, v7
140 ; GFX6-NEXT: ds_read_u8 v1, v1
141 ; GFX6-NEXT: ds_read_u8 v8, v0
142 ; GFX6-NEXT: s_waitcnt lgkmcnt(1)
143 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
144 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
145 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v3
146 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
147 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
148 ; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
149 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v5
150 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v6
151 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 10, v0
152 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 3, v0
153 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 2, v0
154 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 1, v0
155 ; GFX6-NEXT: ds_read_u8 v4, v4
156 ; GFX6-NEXT: ds_read_u8 v5, v5
157 ; GFX6-NEXT: ds_read_u8 v6, v6
158 ; GFX6-NEXT: ds_read_u8 v0, v0
159 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v7
160 ; GFX6-NEXT: s_waitcnt lgkmcnt(3)
161 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
162 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
163 ; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
164 ; GFX6-NEXT: s_waitcnt lgkmcnt(2)
165 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v5
166 ; GFX6-NEXT: s_waitcnt lgkmcnt(1)
167 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v6
168 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
169 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
170 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
171 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v8
172 ; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
173 ; GFX6-NEXT: s_setpc_b64 s[30:31]
174 ;
175 ; GFX10-LABEL: load_lds_v3i32_align1:
176 ; GFX10: ; %bb.0:
177 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
178 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
179 ; GFX10-NEXT: ds_read_u8 v1, v0
180 ; GFX10-NEXT: ds_read_u8 v2, v0 offset:1
181 ; GFX10-NEXT: ds_read_u8 v3, v0 offset:2
182 ; GFX10-NEXT: ds_read_u8 v4, v0 offset:3
183 ; GFX10-NEXT: ds_read_u8 v5, v0 offset:4
184 ; GFX10-NEXT: ds_read_u8 v6, v0 offset:5
185 ; GFX10-NEXT: ds_read_u8 v7, v0 offset:6
186 ; GFX10-NEXT: ds_read_u8 v8, v0 offset:7
187 ; GFX10-NEXT: ds_read_u8 v9, v0 offset:8
188 ; GFX10-NEXT: ds_read_u8 v10, v0 offset:9
189 ; GFX10-NEXT: ds_read_u8 v11, v0 offset:10
190 ; GFX10-NEXT: ds_read_u8 v0, v0 offset:11
191 ; GFX10-NEXT: s_waitcnt lgkmcnt(10)
192 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 8, v1
193 ; GFX10-NEXT: s_waitcnt lgkmcnt(8)
194 ; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v3
195 ; GFX10-NEXT: s_waitcnt lgkmcnt(6)
196 ; GFX10-NEXT: v_lshl_or_b32 v3, v6, 8, v5
197 ; GFX10-NEXT: s_waitcnt lgkmcnt(4)
198 ; GFX10-NEXT: v_lshl_or_b32 v4, v8, 8, v7
199 ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
200 ; GFX10-NEXT: v_lshl_or_b32 v5, v10, 8, v9
201 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
202 ; GFX10-NEXT: v_lshl_or_b32 v6, v0, 8, v11
203 ; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v1
204 ; GFX10-NEXT: v_lshl_or_b32 v1, v4, 16, v3
205 ; GFX10-NEXT: v_lshl_or_b32 v2, v6, 16, v5
206 ; GFX10-NEXT: s_setpc_b64 s[30:31]
207 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 1
208 ret <3 x i32> %load
209 }
211 define <3 x i32> @load_lds_v3i32_align2(<3 x i32> addrspace(3)* %ptr) {
212 ; GFX9-LABEL: load_lds_v3i32_align2:
213 ; GFX9: ; %bb.0:
214 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
215 ; GFX9-NEXT: ds_read_u16 v1, v0
216 ; GFX9-NEXT: ds_read_u16 v2, v0 offset:2
217 ; GFX9-NEXT: ds_read_u16 v3, v0 offset:4
218 ; GFX9-NEXT: ds_read_u16 v4, v0 offset:6
219 ; GFX9-NEXT: ds_read_u16 v5, v0 offset:8
220 ; GFX9-NEXT: ds_read_u16 v6, v0 offset:10
221 ; GFX9-NEXT: s_waitcnt lgkmcnt(4)
222 ; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v1
223 ; GFX9-NEXT: s_waitcnt lgkmcnt(2)
224 ; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v3
225 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
226 ; GFX9-NEXT: v_lshl_or_b32 v2, v6, 16, v5
227 ; GFX9-NEXT: s_setpc_b64 s[30:31]
228 ;
229 ; GFX7-LABEL: load_lds_v3i32_align2:
230 ; GFX7: ; %bb.0:
231 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
232 ; GFX7-NEXT: s_mov_b32 m0, -1
233 ; GFX7-NEXT: ds_read_u16 v2, v0 offset:10
234 ; GFX7-NEXT: ds_read_u16 v3, v0 offset:8
235 ; GFX7-NEXT: ds_read_u16 v1, v0 offset:6
236 ; GFX7-NEXT: ds_read_u16 v4, v0 offset:4
237 ; GFX7-NEXT: ds_read_u16 v5, v0 offset:2
238 ; GFX7-NEXT: ds_read_u16 v0, v0
239 ; GFX7-NEXT: s_waitcnt lgkmcnt(5)
240 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2
241 ; GFX7-NEXT: s_waitcnt lgkmcnt(3)
242 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
243 ; GFX7-NEXT: s_waitcnt lgkmcnt(2)
244 ; GFX7-NEXT: v_or_b32_e32 v1, v1, v4
245 ; GFX7-NEXT: s_waitcnt lgkmcnt(1)
246 ; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5
247 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
248 ; GFX7-NEXT: v_or_b32_e32 v0, v5, v0
249 ; GFX7-NEXT: v_or_b32_e32 v2, v2, v3
250 ; GFX7-NEXT: s_setpc_b64 s[30:31]
251 ;
252 ; GFX6-LABEL: load_lds_v3i32_align2:
253 ; GFX6: ; %bb.0:
254 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
255 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 6, v0
256 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 4, v0
257 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 10, v0
258 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 8, v0
259 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0
260 ; GFX6-NEXT: s_mov_b32 m0, -1
261 ; GFX6-NEXT: ds_read_u16 v2, v2
262 ; GFX6-NEXT: ds_read_u16 v3, v3
263 ; GFX6-NEXT: ds_read_u16 v4, v4
264 ; GFX6-NEXT: ds_read_u16 v5, v5
265 ; GFX6-NEXT: ds_read_u16 v1, v1
266 ; GFX6-NEXT: ds_read_u16 v0, v0
267 ; GFX6-NEXT: s_waitcnt lgkmcnt(1)
268 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
269 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
270 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
271 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
272 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
273 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
274 ; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
275 ; GFX6-NEXT: s_setpc_b64 s[30:31]
276 ;
277 ; GFX10-LABEL: load_lds_v3i32_align2:
278 ; GFX10: ; %bb.0:
279 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
280 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
281 ; GFX10-NEXT: ds_read_u16 v1, v0
282 ; GFX10-NEXT: ds_read_u16 v2, v0 offset:2
283 ; GFX10-NEXT: ds_read_u16 v3, v0 offset:4
284 ; GFX10-NEXT: ds_read_u16 v4, v0 offset:6
285 ; GFX10-NEXT: ds_read_u16 v5, v0 offset:8
286 ; GFX10-NEXT: ds_read_u16 v6, v0 offset:10
287 ; GFX10-NEXT: s_waitcnt lgkmcnt(4)
288 ; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v1
289 ; GFX10-NEXT: s_waitcnt lgkmcnt(2)
290 ; GFX10-NEXT: v_lshl_or_b32 v1, v4, 16, v3
291 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
292 ; GFX10-NEXT: v_lshl_or_b32 v2, v6, 16, v5
293 ; GFX10-NEXT: s_setpc_b64 s[30:31]
294 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 2
295 ret <3 x i32> %load
296 }
298 define <3 x i32> @load_lds_v3i32_align4(<3 x i32> addrspace(3)* %ptr) {
299 ; GFX9-LABEL: load_lds_v3i32_align4:
300 ; GFX9: ; %bb.0:
301 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
302 ; GFX9-NEXT: v_mov_b32_e32 v2, v0
303 ; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
304 ; GFX9-NEXT: ds_read_b32 v2, v2 offset:8
305 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
306 ; GFX9-NEXT: s_setpc_b64 s[30:31]
307 ;
308 ; GFX7-LABEL: load_lds_v3i32_align4:
309 ; GFX7: ; %bb.0:
310 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
311 ; GFX7-NEXT: v_mov_b32_e32 v2, v0
312 ; GFX7-NEXT: s_mov_b32 m0, -1
313 ; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
314 ; GFX7-NEXT: ds_read_b32 v2, v2 offset:8
315 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
316 ; GFX7-NEXT: s_setpc_b64 s[30:31]
317 ;
318 ; GFX6-LABEL: load_lds_v3i32_align4:
319 ; GFX6: ; %bb.0:
320 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
321 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 4, v0
322 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 8, v0
323 ; GFX6-NEXT: s_mov_b32 m0, -1
324 ; GFX6-NEXT: ds_read_b32 v2, v2
325 ; GFX6-NEXT: ds_read_b32 v1, v1
326 ; GFX6-NEXT: ds_read_b32 v0, v0
327 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
328 ; GFX6-NEXT: s_setpc_b64 s[30:31]
329 ;
330 ; GFX10-LABEL: load_lds_v3i32_align4:
331 ; GFX10: ; %bb.0:
332 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
333 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
334 ; GFX10-NEXT: v_mov_b32_e32 v2, v0
335 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
336 ; GFX10-NEXT: ds_read_b32 v2, v2 offset:8
337 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
338 ; GFX10-NEXT: s_setpc_b64 s[30:31]
339 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4
340 ret <3 x i32> %load
341 }
343 define <3 x i32> @load_lds_v3i32_align8(<3 x i32> addrspace(3)* %ptr) {
344 ; GFX9-LABEL: load_lds_v3i32_align8:
345 ; GFX9: ; %bb.0:
346 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
347 ; GFX9-NEXT: v_mov_b32_e32 v2, v0
348 ; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
349 ; GFX9-NEXT: ds_read_b32 v2, v2 offset:8
350 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
351 ; GFX9-NEXT: s_setpc_b64 s[30:31]
352 ;
353 ; GFX7-LABEL: load_lds_v3i32_align8:
354 ; GFX7: ; %bb.0:
355 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
356 ; GFX7-NEXT: v_mov_b32_e32 v2, v0
357 ; GFX7-NEXT: s_mov_b32 m0, -1
358 ; GFX7-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
359 ; GFX7-NEXT: ds_read_b32 v2, v2 offset:8
360 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
361 ; GFX7-NEXT: s_setpc_b64 s[30:31]
362 ;
363 ; GFX6-LABEL: load_lds_v3i32_align8:
364 ; GFX6: ; %bb.0:
365 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
366 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 4, v0
367 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 8, v0
368 ; GFX6-NEXT: s_mov_b32 m0, -1
369 ; GFX6-NEXT: ds_read_b32 v2, v2
370 ; GFX6-NEXT: ds_read_b32 v1, v1
371 ; GFX6-NEXT: ds_read_b32 v0, v0
372 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
373 ; GFX6-NEXT: s_setpc_b64 s[30:31]
374 ;
375 ; GFX10-LABEL: load_lds_v3i32_align8:
376 ; GFX10: ; %bb.0:
377 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
378 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
379 ; GFX10-NEXT: v_mov_b32_e32 v2, v0
380 ; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset1:1
381 ; GFX10-NEXT: ds_read_b32 v2, v2 offset:8
382 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
383 ; GFX10-NEXT: s_setpc_b64 s[30:31]
384 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 8
385 ret <3 x i32> %load
386 }
388 define <3 x i32> @load_lds_v3i32_align16(<3 x i32> addrspace(3)* %ptr) {
389 ; GFX9-LABEL: load_lds_v3i32_align16:
390 ; GFX9: ; %bb.0:
391 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
392 ; GFX9-NEXT: ds_read_b96 v[0:2], v0
393 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
394 ; GFX9-NEXT: s_setpc_b64 s[30:31]
395 ;
396 ; GFX7-LABEL: load_lds_v3i32_align16:
397 ; GFX7: ; %bb.0:
398 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
399 ; GFX7-NEXT: s_mov_b32 m0, -1
400 ; GFX7-NEXT: ds_read_b96 v[0:2], v0
401 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
402 ; GFX7-NEXT: s_setpc_b64 s[30:31]
403 ;
404 ; GFX6-LABEL: load_lds_v3i32_align16:
405 ; GFX6: ; %bb.0:
406 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
407 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 8, v0
408 ; GFX6-NEXT: s_mov_b32 m0, -1
409 ; GFX6-NEXT: ds_read_b32 v2, v1
410 ; GFX6-NEXT: ds_read_b64 v[0:1], v0
411 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
412 ; GFX6-NEXT: s_setpc_b64 s[30:31]
413 ;
414 ; GFX10-LABEL: load_lds_v3i32_align16:
415 ; GFX10: ; %bb.0:
416 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
417 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
418 ; GFX10-NEXT: ds_read_b96 v[0:2], v0
419 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
420 ; GFX10-NEXT: s_setpc_b64 s[30:31]
421 %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16
422 ret <3 x i32> %load
423 }