| blob | 9bafe57b786e2e88f7ea52e0984d8d83a2f6b6db |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-mesa3d < %s | FileCheck %s
4 define i1 @test_srem_odd(i29 %X) nounwind {
5 ; CHECK-LABEL: test_srem_odd:
6 ; CHECK: ; %bb.0:
7 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8 ; CHECK-NEXT: s_mov_b32 s4, 0x1f5a814b
9 ; CHECK-NEXT: s_mov_b32 s5, 0x52bf5b
10 ; CHECK-NEXT: v_mul_lo_u32 v0, v0, s4
11 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, 0x295fad, v0
12 ; CHECK-NEXT: v_and_b32_e32 v0, 0x1fffffff, v0
13 ; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s5, v0
14 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
15 ; CHECK-NEXT: s_setpc_b64 s[30:31]
16 %srem = srem i29 %X, 99
17 %cmp = icmp eq i29 %srem, 0
18 ret i1 %cmp
19 }
21 define i1 @test_srem_even(i4 %X) nounwind {
22 ; CHECK-LABEL: test_srem_even:
23 ; CHECK: ; %bb.0:
24 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
25 ; CHECK-NEXT: v_bfe_i32 v0, v0, 0, 4
26 ; CHECK-NEXT: s_mov_b32 s4, 0x2aaaaaab
27 ; CHECK-NEXT: v_mul_hi_i32 v1, v0, s4
28 ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1
29 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
30 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, 6
31 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
32 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
33 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
34 ; CHECK-NEXT: s_setpc_b64 s[30:31]
35 %srem = srem i4 %X, 6
36 %cmp = icmp eq i4 %srem, 1
37 ret i1 %cmp
38 }
40 define i1 @test_srem_pow2_setne(i6 %X) nounwind {
41 ; CHECK-LABEL: test_srem_pow2_setne:
42 ; CHECK: ; %bb.0:
43 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
44 ; CHECK-NEXT: v_bfe_i32 v1, v0, 0, 6
45 ; CHECK-NEXT: v_bfe_u32 v1, v1, 9, 2
46 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v0, v1
47 ; CHECK-NEXT: v_and_b32_e32 v1, 60, v1
48 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
49 ; CHECK-NEXT: v_and_b32_e32 v0, 63, v0
50 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
51 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
52 ; CHECK-NEXT: s_setpc_b64 s[30:31]
53 %srem = srem i6 %X, 4
54 %cmp = icmp ne i6 %srem, 0
55 ret i1 %cmp
56 }
58 define <3 x i1> @test_srem_vec(<3 x i31> %X) nounwind {
59 ; CHECK-LABEL: test_srem_vec:
60 ; CHECK: ; %bb.0:
61 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
62 ; CHECK-NEXT: v_bfe_i32 v3, v2, 0, 31
63 ; CHECK-NEXT: v_bfe_i32 v4, v1, 0, 31
64 ; CHECK-NEXT: v_bfe_i32 v5, v0, 0, 31
65 ; CHECK-NEXT: s_mov_b32 s6, 0x38e38e39
66 ; CHECK-NEXT: s_mov_b32 s7, 0xc71c71c7
67 ; CHECK-NEXT: s_brev_b32 s4, -2
68 ; CHECK-NEXT: s_mov_b32 s5, 0x7ffffffd
69 ; CHECK-NEXT: v_mul_hi_i32 v5, v5, s6
70 ; CHECK-NEXT: v_mul_hi_i32 v4, v4, s6
71 ; CHECK-NEXT: v_mul_hi_i32 v3, v3, s7
72 ; CHECK-NEXT: v_lshrrev_b32_e32 v6, 31, v5
73 ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5
74 ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 31, v4
75 ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 1, v4
76 ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v3
77 ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 1, v3
78 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
79 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
80 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v8
81 ; CHECK-NEXT: v_mul_lo_u32 v5, v5, 9
82 ; CHECK-NEXT: v_mul_lo_u32 v4, v4, 9
83 ; CHECK-NEXT: v_mul_lo_u32 v3, v3, -9
84 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
85 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
86 ; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
87 ; CHECK-NEXT: v_and_b32_e32 v2, s4, v2
88 ; CHECK-NEXT: v_and_b32_e32 v1, s4, v1
89 ; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
90 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 3, v0
91 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
92 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s5, v1
93 ; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
94 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 3, v2
95 ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
96 ; CHECK-NEXT: s_setpc_b64 s[30:31]
97 %srem = srem <3 x i31> %X, <i31 9, i31 9, i31 -9>
98 %cmp = icmp ne <3 x i31> %srem, <i31 3, i31 -3, i31 3>
99 ret <3 x i1> %cmp
100 }