| blob | 73116bb4a985d2c962c8875c2436d780df48a7f4 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
4 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG
6 declare i32 @llvm.amdgcn.workitem.id.x() #0
8 define amdgpu_kernel void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
9 ; SI-LABEL: lshr_i32:
10 ; SI: ; %bb.0:
11 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
12 ; SI-NEXT: s_mov_b32 s3, 0xf000
13 ; SI-NEXT: s_mov_b32 s2, -1
14 ; SI-NEXT: s_waitcnt lgkmcnt(0)
15 ; SI-NEXT: s_mov_b32 s0, s4
16 ; SI-NEXT: s_mov_b32 s1, s5
17 ; SI-NEXT: s_mov_b32 s4, s6
18 ; SI-NEXT: s_mov_b32 s5, s7
19 ; SI-NEXT: s_mov_b32 s6, s2
20 ; SI-NEXT: s_mov_b32 s7, s3
21 ; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
22 ; SI-NEXT: s_waitcnt vmcnt(0)
23 ; SI-NEXT: v_lshrrev_b32_e32 v0, v1, v0
24 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
25 ; SI-NEXT: s_endpgm
26 ;
27 ; VI-LABEL: lshr_i32:
28 ; VI: ; %bb.0:
29 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
30 ; VI-NEXT: s_mov_b32 s7, 0xf000
31 ; VI-NEXT: s_mov_b32 s6, -1
32 ; VI-NEXT: s_waitcnt lgkmcnt(0)
33 ; VI-NEXT: s_mov_b32 s4, s0
34 ; VI-NEXT: s_mov_b32 s5, s1
35 ; VI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
36 ; VI-NEXT: s_waitcnt lgkmcnt(0)
37 ; VI-NEXT: s_lshr_b32 s0, s0, s1
38 ; VI-NEXT: v_mov_b32_e32 v0, s0
39 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
40 ; VI-NEXT: s_endpgm
41 ;
42 ; EG-LABEL: lshr_i32:
43 ; EG: ; %bb.0:
44 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
45 ; EG-NEXT: TEX 0 @6
46 ; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
47 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
48 ; EG-NEXT: CF_END
49 ; EG-NEXT: PAD
50 ; EG-NEXT: Fetch clause starting at 6:
51 ; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
52 ; EG-NEXT: ALU clause starting at 8:
53 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
54 ; EG-NEXT: ALU clause starting at 9:
55 ; EG-NEXT: LSHR T0.X, T0.X, T0.Y,
56 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
57 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
58 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
59 %a = load i32, i32 addrspace(1)* %in
60 %b = load i32, i32 addrspace(1)* %b_ptr
61 %result = lshr i32 %a, %b
62 store i32 %result, i32 addrspace(1)* %out
63 ret void
64 }
66 define amdgpu_kernel void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
67 ; SI-LABEL: lshr_v2i32:
68 ; SI: ; %bb.0:
69 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
70 ; SI-NEXT: s_mov_b32 s3, 0xf000
71 ; SI-NEXT: s_mov_b32 s2, -1
72 ; SI-NEXT: s_mov_b32 s10, s2
73 ; SI-NEXT: s_mov_b32 s11, s3
74 ; SI-NEXT: s_waitcnt lgkmcnt(0)
75 ; SI-NEXT: s_mov_b32 s8, s6
76 ; SI-NEXT: s_mov_b32 s9, s7
77 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
78 ; SI-NEXT: s_mov_b32 s0, s4
79 ; SI-NEXT: s_mov_b32 s1, s5
80 ; SI-NEXT: s_waitcnt vmcnt(0)
81 ; SI-NEXT: v_lshr_b32_e32 v1, v1, v3
82 ; SI-NEXT: v_lshr_b32_e32 v0, v0, v2
83 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
84 ; SI-NEXT: s_endpgm
85 ;
86 ; VI-LABEL: lshr_v2i32:
87 ; VI: ; %bb.0:
88 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
89 ; VI-NEXT: s_mov_b32 s3, 0xf000
90 ; VI-NEXT: s_mov_b32 s2, -1
91 ; VI-NEXT: s_waitcnt lgkmcnt(0)
92 ; VI-NEXT: s_load_dwordx2 s[8:9], s[6:7], 0x0
93 ; VI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x8
94 ; VI-NEXT: s_mov_b32 s0, s4
95 ; VI-NEXT: s_mov_b32 s1, s5
96 ; VI-NEXT: s_waitcnt lgkmcnt(0)
97 ; VI-NEXT: s_lshr_b32 s4, s9, s7
98 ; VI-NEXT: s_lshr_b32 s5, s8, s6
99 ; VI-NEXT: v_mov_b32_e32 v0, s5
100 ; VI-NEXT: v_mov_b32_e32 v1, s4
101 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
102 ; VI-NEXT: s_endpgm
103 ;
104 ; EG-LABEL: lshr_v2i32:
105 ; EG: ; %bb.0:
106 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
107 ; EG-NEXT: TEX 1 @6
108 ; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]
109 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
110 ; EG-NEXT: CF_END
111 ; EG-NEXT: PAD
112 ; EG-NEXT: Fetch clause starting at 6:
113 ; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1
114 ; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
115 ; EG-NEXT: ALU clause starting at 10:
116 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
117 ; EG-NEXT: ALU clause starting at 11:
118 ; EG-NEXT: LSHR * T0.Y, T0.Y, T1.Y,
119 ; EG-NEXT: LSHR T0.X, T0.X, T1.X,
120 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
121 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
122 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
123 %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
124 %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
125 %result = lshr <2 x i32> %a, %b
126 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
127 ret void
128 }
130 define amdgpu_kernel void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
131 ; SI-LABEL: lshr_v4i32:
132 ; SI: ; %bb.0:
133 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
134 ; SI-NEXT: s_mov_b32 s3, 0xf000
135 ; SI-NEXT: s_mov_b32 s2, -1
136 ; SI-NEXT: s_mov_b32 s10, s2
137 ; SI-NEXT: s_mov_b32 s11, s3
138 ; SI-NEXT: s_waitcnt lgkmcnt(0)
139 ; SI-NEXT: s_mov_b32 s8, s6
140 ; SI-NEXT: s_mov_b32 s9, s7
141 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
142 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
143 ; SI-NEXT: s_mov_b32 s0, s4
144 ; SI-NEXT: s_mov_b32 s1, s5
145 ; SI-NEXT: s_waitcnt vmcnt(0)
146 ; SI-NEXT: v_lshr_b32_e32 v3, v3, v7
147 ; SI-NEXT: v_lshr_b32_e32 v2, v2, v6
148 ; SI-NEXT: v_lshr_b32_e32 v1, v1, v5
149 ; SI-NEXT: v_lshr_b32_e32 v0, v0, v4
150 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
151 ; SI-NEXT: s_endpgm
152 ;
153 ; VI-LABEL: lshr_v4i32:
154 ; VI: ; %bb.0:
155 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
156 ; VI-NEXT: s_mov_b32 s3, 0xf000
157 ; VI-NEXT: s_mov_b32 s2, -1
158 ; VI-NEXT: s_waitcnt lgkmcnt(0)
159 ; VI-NEXT: s_mov_b32 s0, s4
160 ; VI-NEXT: s_mov_b32 s1, s5
161 ; VI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0
162 ; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x10
163 ; VI-NEXT: s_waitcnt lgkmcnt(0)
164 ; VI-NEXT: s_lshr_b32 s7, s11, s7
165 ; VI-NEXT: s_lshr_b32 s6, s10, s6
166 ; VI-NEXT: s_lshr_b32 s5, s9, s5
167 ; VI-NEXT: s_lshr_b32 s4, s8, s4
168 ; VI-NEXT: v_mov_b32_e32 v0, s4
169 ; VI-NEXT: v_mov_b32_e32 v1, s5
170 ; VI-NEXT: v_mov_b32_e32 v2, s6
171 ; VI-NEXT: v_mov_b32_e32 v3, s7
172 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
173 ; VI-NEXT: s_endpgm
174 ;
175 ; EG-LABEL: lshr_v4i32:
176 ; EG: ; %bb.0:
177 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
178 ; EG-NEXT: TEX 1 @6
179 ; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]
180 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
181 ; EG-NEXT: CF_END
182 ; EG-NEXT: PAD
183 ; EG-NEXT: Fetch clause starting at 6:
184 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
185 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
186 ; EG-NEXT: ALU clause starting at 10:
187 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
188 ; EG-NEXT: ALU clause starting at 11:
189 ; EG-NEXT: LSHR * T0.W, T0.W, T1.W,
190 ; EG-NEXT: LSHR * T0.Z, T0.Z, T1.Z,
191 ; EG-NEXT: LSHR * T0.Y, T0.Y, T1.Y,
192 ; EG-NEXT: LSHR T0.X, T0.X, T1.X,
193 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
194 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
195 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
196 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
197 %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
198 %result = lshr <4 x i32> %a, %b
199 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
200 ret void
201 }
203 define amdgpu_kernel void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
204 ; SI-LABEL: lshr_i64:
205 ; SI: ; %bb.0:
206 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
207 ; SI-NEXT: s_mov_b32 s3, 0xf000
208 ; SI-NEXT: s_mov_b32 s2, -1
209 ; SI-NEXT: s_mov_b32 s10, s2
210 ; SI-NEXT: s_mov_b32 s11, s3
211 ; SI-NEXT: s_waitcnt lgkmcnt(0)
212 ; SI-NEXT: s_mov_b32 s8, s6
213 ; SI-NEXT: s_mov_b32 s9, s7
214 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
215 ; SI-NEXT: s_mov_b32 s0, s4
216 ; SI-NEXT: s_mov_b32 s1, s5
217 ; SI-NEXT: s_waitcnt vmcnt(0)
218 ; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
219 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
220 ; SI-NEXT: s_endpgm
221 ;
222 ; VI-LABEL: lshr_i64:
223 ; VI: ; %bb.0:
224 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
225 ; VI-NEXT: s_mov_b32 s7, 0xf000
226 ; VI-NEXT: s_mov_b32 s6, -1
227 ; VI-NEXT: s_waitcnt lgkmcnt(0)
228 ; VI-NEXT: s_mov_b32 s4, s0
229 ; VI-NEXT: s_mov_b32 s5, s1
230 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
231 ; VI-NEXT: s_waitcnt lgkmcnt(0)
232 ; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
233 ; VI-NEXT: v_mov_b32_e32 v0, s0
234 ; VI-NEXT: v_mov_b32_e32 v1, s1
235 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
236 ; VI-NEXT: s_endpgm
237 ;
238 ; EG-LABEL: lshr_i64:
239 ; EG: ; %bb.0:
240 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
241 ; EG-NEXT: TEX 0 @6
242 ; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]
243 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
244 ; EG-NEXT: CF_END
245 ; EG-NEXT: PAD
246 ; EG-NEXT: Fetch clause starting at 6:
247 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
248 ; EG-NEXT: ALU clause starting at 8:
249 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
250 ; EG-NEXT: ALU clause starting at 9:
251 ; EG-NEXT: AND_INT * T0.W, T0.Z, literal.x,
252 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
253 ; EG-NEXT: LSHR T1.Z, T0.Y, PV.W,
254 ; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, T0.Z,
255 ; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,
256 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
257 ; EG-NEXT: CNDE_INT T0.X, PS, PV.W, PV.Z,
258 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
259 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
260 ; EG-NEXT: CNDE_INT * T0.Y, T1.W, T1.Z, 0.0,
261 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
262 %a = load i64, i64 addrspace(1)* %in
263 %b = load i64, i64 addrspace(1)* %b_ptr
264 %result = lshr i64 %a, %b
265 store i64 %result, i64 addrspace(1)* %out
266 ret void
267 }
269 define amdgpu_kernel void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
270 ; SI-LABEL: lshr_v4i64:
271 ; SI: ; %bb.0:
272 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
273 ; SI-NEXT: s_mov_b32 s3, 0xf000
274 ; SI-NEXT: s_mov_b32 s2, -1
275 ; SI-NEXT: s_mov_b32 s10, s2
276 ; SI-NEXT: s_mov_b32 s11, s3
277 ; SI-NEXT: s_waitcnt lgkmcnt(0)
278 ; SI-NEXT: s_mov_b32 s8, s6
279 ; SI-NEXT: s_mov_b32 s9, s7
280 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
281 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
282 ; SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
283 ; SI-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48
284 ; SI-NEXT: s_mov_b32 s0, s4
285 ; SI-NEXT: s_mov_b32 s1, s5
286 ; SI-NEXT: s_waitcnt vmcnt(1)
287 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], v10
288 ; SI-NEXT: s_waitcnt vmcnt(0)
289 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], v13
290 ; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], v11
291 ; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], v8
292 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
293 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
294 ; SI-NEXT: s_endpgm
295 ;
296 ; VI-LABEL: lshr_v4i64:
297 ; VI: ; %bb.0:
298 ; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
299 ; VI-NEXT: s_mov_b32 s19, 0xf000
300 ; VI-NEXT: s_mov_b32 s18, -1
301 ; VI-NEXT: s_waitcnt lgkmcnt(0)
302 ; VI-NEXT: s_mov_b32 s16, s8
303 ; VI-NEXT: s_mov_b32 s17, s9
304 ; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
305 ; VI-NEXT: s_load_dwordx8 s[8:15], s[10:11], 0x20
306 ; VI-NEXT: s_waitcnt lgkmcnt(0)
307 ; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
308 ; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
309 ; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
310 ; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s8
311 ; VI-NEXT: v_mov_b32_e32 v0, s4
312 ; VI-NEXT: v_mov_b32_e32 v1, s5
313 ; VI-NEXT: v_mov_b32_e32 v2, s6
314 ; VI-NEXT: v_mov_b32_e32 v3, s7
315 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
316 ; VI-NEXT: s_nop 0
317 ; VI-NEXT: v_mov_b32_e32 v0, s0
318 ; VI-NEXT: v_mov_b32_e32 v1, s1
319 ; VI-NEXT: v_mov_b32_e32 v2, s2
320 ; VI-NEXT: v_mov_b32_e32 v3, s3
321 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
322 ; VI-NEXT: s_endpgm
323 ;
324 ; EG-LABEL: lshr_v4i64:
325 ; EG: ; %bb.0:
326 ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
327 ; EG-NEXT: TEX 3 @6
328 ; EG-NEXT: ALU 34, @15, KC0[CB0:0-32], KC1[]
329 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0
330 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
331 ; EG-NEXT: CF_END
332 ; EG-NEXT: Fetch clause starting at 6:
333 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 32, #1
334 ; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 16, #1
335 ; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 48, #1
336 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
337 ; EG-NEXT: ALU clause starting at 14:
338 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
339 ; EG-NEXT: ALU clause starting at 15:
340 ; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,
341 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
342 ; EG-NEXT: LSHR T4.Z, T0.W, PV.W,
343 ; EG-NEXT: AND_INT T1.W, T1.Z, literal.x,
344 ; EG-NEXT: AND_INT * T3.W, T3.Z, literal.y,
345 ; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
346 ; EG-NEXT: BIT_ALIGN_INT T4.X, T0.W, T0.Z, T1.Z,
347 ; EG-NEXT: LSHR T1.Y, T2.W, PS, BS:VEC_120/SCL_212
348 ; EG-NEXT: AND_INT * T0.Z, T3.Z, literal.x,
349 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
350 ; EG-NEXT: BIT_ALIGN_INT T0.W, T2.W, T2.Z, T3.Z,
351 ; EG-NEXT: AND_INT * T2.W, T3.X, literal.x,
352 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
353 ; EG-NEXT: AND_INT T5.X, T1.X, literal.x,
354 ; EG-NEXT: LSHR T3.Y, T2.Y, PS,
355 ; EG-NEXT: CNDE_INT T2.Z, T0.Z, PV.W, T1.Y,
356 ; EG-NEXT: BIT_ALIGN_INT T0.W, T2.Y, T2.X, T3.X,
357 ; EG-NEXT: AND_INT * T3.W, T3.X, literal.y,
358 ; EG-NEXT: 31(4.344025e-44), 32(4.484155e-44)
359 ; EG-NEXT: CNDE_INT T2.X, PS, PV.W, PV.Y,
360 ; EG-NEXT: LSHR T4.Y, T0.Y, PV.X,
361 ; EG-NEXT: CNDE_INT T1.Z, T1.W, T4.X, T4.Z,
362 ; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, T1.X, BS:VEC_102/SCL_221
363 ; EG-NEXT: AND_INT * T4.W, T1.X, literal.x,
364 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
365 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, PV.Y,
366 ; EG-NEXT: ADD_INT T0.W, KC0[2].Y, literal.x,
367 ; EG-NEXT: CNDE_INT * T2.W, T0.Z, T1.Y, 0.0,
368 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
369 ; EG-NEXT: LSHR T0.X, PV.W, literal.x,
370 ; EG-NEXT: CNDE_INT T2.Y, T3.W, T3.Y, 0.0,
371 ; EG-NEXT: CNDE_INT T1.W, T1.W, T4.Z, 0.0, BS:VEC_120/SCL_212
372 ; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
373 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
374 ; EG-NEXT: CNDE_INT * T1.Y, T4.W, T4.Y, 0.0,
375 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
376 %a = load <4 x i64>, <4 x i64> addrspace(1)* %in
377 %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
378 %result = lshr <4 x i64> %a, %b
379 store <4 x i64> %result, <4 x i64> addrspace(1)* %out
380 ret void
381 }
383 ; Make sure load width gets reduced to i32 load.
384 define amdgpu_kernel void @s_lshr_32_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
385 ; SI-LABEL: s_lshr_32_i64:
386 ; SI: ; %bb.0:
387 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
388 ; SI-NEXT: s_load_dword s0, s[0:1], 0x14
389 ; SI-NEXT: s_mov_b32 s7, 0xf000
390 ; SI-NEXT: s_mov_b32 s6, -1
391 ; SI-NEXT: v_mov_b32_e32 v1, 0
392 ; SI-NEXT: s_waitcnt lgkmcnt(0)
393 ; SI-NEXT: v_mov_b32_e32 v0, s0
394 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
395 ; SI-NEXT: s_endpgm
396 ;
397 ; VI-LABEL: s_lshr_32_i64:
398 ; VI: ; %bb.0:
399 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
400 ; VI-NEXT: s_load_dword s0, s[0:1], 0x50
401 ; VI-NEXT: s_mov_b32 s7, 0xf000
402 ; VI-NEXT: s_mov_b32 s6, -1
403 ; VI-NEXT: v_mov_b32_e32 v1, 0
404 ; VI-NEXT: s_waitcnt lgkmcnt(0)
405 ; VI-NEXT: v_mov_b32_e32 v0, s0
406 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
407 ; VI-NEXT: s_endpgm
408 ;
409 ; EG-LABEL: s_lshr_32_i64:
410 ; EG: ; %bb.0:
411 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
412 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
413 ; EG-NEXT: CF_END
414 ; EG-NEXT: PAD
415 ; EG-NEXT: ALU clause starting at 4:
416 ; EG-NEXT: MOV T0.X, KC0[5].X,
417 ; EG-NEXT: MOV T0.Y, 0.0,
418 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
419 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
420 %result = lshr i64 %a, 32
421 store i64 %result, i64 addrspace(1)* %out
422 ret void
423 }
425 define amdgpu_kernel void @v_lshr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
426 ; SI-LABEL: v_lshr_32_i64:
427 ; SI: ; %bb.0:
428 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
429 ; SI-NEXT: s_mov_b32 s6, 0
430 ; SI-NEXT: s_mov_b32 s7, 0xf000
431 ; SI-NEXT: v_mov_b32_e32 v1, 0
432 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
433 ; SI-NEXT: s_waitcnt lgkmcnt(0)
434 ; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
435 ; SI-NEXT: s_mov_b64 s[0:1], s[2:3]
436 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
437 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 offset:4
438 ; SI-NEXT: v_mov_b32_e32 v3, v1
439 ; SI-NEXT: s_waitcnt vmcnt(0)
440 ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
441 ; SI-NEXT: s_endpgm
442 ;
443 ; VI-LABEL: v_lshr_32_i64:
444 ; VI: ; %bb.0:
445 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
446 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
447 ; VI-NEXT: v_mov_b32_e32 v1, 0
448 ; VI-NEXT: s_waitcnt lgkmcnt(0)
449 ; VI-NEXT: v_mov_b32_e32 v2, s3
450 ; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0
451 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
452 ; VI-NEXT: v_mov_b32_e32 v3, s1
453 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0
454 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
455 ; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v4
456 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
457 ; VI-NEXT: flat_load_dword v0, v[4:5]
458 ; VI-NEXT: s_waitcnt vmcnt(0)
459 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
460 ; VI-NEXT: s_endpgm
461 ;
462 ; EG-LABEL: v_lshr_32_i64:
463 ; EG: ; %bb.0:
464 ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
465 ; EG-NEXT: TEX 0 @6
466 ; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]
467 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
468 ; EG-NEXT: CF_END
469 ; EG-NEXT: PAD
470 ; EG-NEXT: Fetch clause starting at 6:
471 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1
472 ; EG-NEXT: ALU clause starting at 8:
473 ; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
474 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
475 ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
476 ; EG-NEXT: ALU clause starting at 11:
477 ; EG-NEXT: MOV T0.Y, 0.0,
478 ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,
479 ; EG-NEXT: LSHR * T1.X, PV.W, literal.x,
480 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
481 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
482 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
483 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
484 %a = load i64, i64 addrspace(1)* %gep.in
485 %result = lshr i64 %a, 32
486 store i64 %result, i64 addrspace(1)* %gep.out
487 ret void
488 }
490 attributes #0 = { nounwind readnone }