| blob | 3a50f89dbabaf7b32447fdd48c8d0d74383613e3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
6 define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
7 ; GFX6-LABEL: v_uaddsat_i8:
8 ; GFX6: ; %bb.0:
9 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10 ; GFX6-NEXT: s_movk_i32 s4, 0xff
11 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
12 ; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
13 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
14 ; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
15 ; GFX6-NEXT: s_setpc_b64 s[30:31]
16 ;
17 ; GFX8-LABEL: v_uaddsat_i8:
18 ; GFX8: ; %bb.0:
19 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20 ; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
21 ; GFX8-NEXT: v_min_u16_e32 v0, 0xff, v0
22 ; GFX8-NEXT: s_setpc_b64 s[30:31]
23 ;
24 ; GFX9-LABEL: v_uaddsat_i8:
25 ; GFX9: ; %bb.0:
26 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27 ; GFX9-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
28 ; GFX9-NEXT: v_min_u16_e32 v0, 0xff, v0
29 ; GFX9-NEXT: s_setpc_b64 s[30:31]
30 %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
31 ret i8 %result
32 }
34 define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
35 ; GFX6-LABEL: v_uaddsat_i16:
36 ; GFX6: ; %bb.0:
37 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
38 ; GFX6-NEXT: s_mov_b32 s4, 0xffff
39 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
40 ; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
41 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
42 ; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
43 ; GFX6-NEXT: s_setpc_b64 s[30:31]
44 ;
45 ; GFX8-LABEL: v_uaddsat_i16:
46 ; GFX8: ; %bb.0:
47 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
48 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
49 ; GFX8-NEXT: s_setpc_b64 s[30:31]
50 ;
51 ; GFX9-LABEL: v_uaddsat_i16:
52 ; GFX9: ; %bb.0:
53 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
54 ; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
55 ; GFX9-NEXT: s_setpc_b64 s[30:31]
56 %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
57 ret i16 %result
58 }
60 define i32 @v_uaddsat_i32(i32 %lhs, i32 %rhs) {
61 ; GFX6-LABEL: v_uaddsat_i32:
62 ; GFX6: ; %bb.0:
63 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
64 ; GFX6-NEXT: v_not_b32_e32 v2, v1
65 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v2
66 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
67 ; GFX6-NEXT: s_setpc_b64 s[30:31]
68 ;
69 ; GFX8-LABEL: v_uaddsat_i32:
70 ; GFX8: ; %bb.0:
71 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
72 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp
73 ; GFX8-NEXT: s_setpc_b64 s[30:31]
74 ;
75 ; GFX9-LABEL: v_uaddsat_i32:
76 ; GFX9: ; %bb.0:
77 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
78 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp
79 ; GFX9-NEXT: s_setpc_b64 s[30:31]
80 %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
81 ret i32 %result
82 }
84 define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
85 ; GFX6-LABEL: v_uaddsat_v2i16:
86 ; GFX6: ; %bb.0:
87 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
88 ; GFX6-NEXT: s_mov_b32 s4, 0xffff
89 ; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
90 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
91 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
92 ; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
93 ; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
94 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
95 ; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
96 ; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
97 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
98 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
99 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
100 ; GFX6-NEXT: s_setpc_b64 s[30:31]
101 ;
102 ; GFX8-LABEL: v_uaddsat_v2i16:
103 ; GFX8: ; %bb.0:
104 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
105 ; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
106 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
107 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
108 ; GFX8-NEXT: s_setpc_b64 s[30:31]
109 ;
110 ; GFX9-LABEL: v_uaddsat_v2i16:
111 ; GFX9: ; %bb.0:
112 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
114 ; GFX9-NEXT: s_setpc_b64 s[30:31]
115 %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
116 ret <2 x i16> %result
117 }
119 define <3 x i16> @v_uaddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
120 ; GFX6-LABEL: v_uaddsat_v3i16:
121 ; GFX6: ; %bb.0:
122 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
123 ; GFX6-NEXT: s_mov_b32 s4, 0xffff
124 ; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
125 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
126 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
127 ; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
128 ; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
129 ; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
130 ; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
131 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
132 ; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
133 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
134 ; GFX6-NEXT: v_min_u32_e32 v3, s4, v2
135 ; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
136 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
137 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
138 ; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v3
139 ; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16
140 ; GFX6-NEXT: s_setpc_b64 s[30:31]
141 ;
142 ; GFX8-LABEL: v_uaddsat_v3i16:
143 ; GFX8: ; %bb.0:
144 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
145 ; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
146 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp
147 ; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp
148 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
149 ; GFX8-NEXT: s_setpc_b64 s[30:31]
150 ;
151 ; GFX9-LABEL: v_uaddsat_v3i16:
152 ; GFX9: ; %bb.0:
153 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
154 ; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
155 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
156 ; GFX9-NEXT: s_setpc_b64 s[30:31]
157 %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
158 ret <3 x i16> %result
159 }
161 define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
162 ; GFX6-LABEL: v_uaddsat_v4i16:
163 ; GFX6: ; %bb.0:
164 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
165 ; GFX6-NEXT: s_mov_b32 s4, 0xffff
166 ; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
167 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
168 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
169 ; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
170 ; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
171 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
172 ; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
173 ; GFX6-NEXT: v_and_b32_e32 v7, s4, v7
174 ; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
175 ; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
176 ; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
177 ; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
178 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
179 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
180 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v6
181 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v7
182 ; GFX6-NEXT: v_min_u32_e32 v2, s4, v2
183 ; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
184 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
185 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
186 ; GFX6-NEXT: s_setpc_b64 s[30:31]
187 ;
188 ; GFX8-LABEL: v_uaddsat_v4i16:
189 ; GFX8: ; %bb.0:
190 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
191 ; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
192 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp
193 ; GFX8-NEXT: v_add_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
194 ; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp
195 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
196 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
197 ; GFX8-NEXT: s_setpc_b64 s[30:31]
198 ;
199 ; GFX9-LABEL: v_uaddsat_v4i16:
200 ; GFX9: ; %bb.0:
201 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
202 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
203 ; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
204 ; GFX9-NEXT: s_setpc_b64 s[30:31]
205 %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
206 %cast = bitcast <4 x i16> %result to <2 x float>
207 ret <2 x float> %cast
208 }
210 define <2 x i32> @v_uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
211 ; GFX6-LABEL: v_uaddsat_v2i32:
212 ; GFX6: ; %bb.0:
213 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
214 ; GFX6-NEXT: v_not_b32_e32 v4, v2
215 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v4
216 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
217 ; GFX6-NEXT: v_not_b32_e32 v2, v3
218 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v2
219 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
220 ; GFX6-NEXT: s_setpc_b64 s[30:31]
221 ;
222 ; GFX8-LABEL: v_uaddsat_v2i32:
223 ; GFX8: ; %bb.0:
224 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
225 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v2 clamp
226 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v3 clamp
227 ; GFX8-NEXT: s_setpc_b64 s[30:31]
228 ;
229 ; GFX9-LABEL: v_uaddsat_v2i32:
230 ; GFX9: ; %bb.0:
231 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
232 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v2 clamp
233 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v3 clamp
234 ; GFX9-NEXT: s_setpc_b64 s[30:31]
235 %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
236 ret <2 x i32> %result
237 }
239 define <3 x i32> @v_uaddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
240 ; GFX6-LABEL: v_uaddsat_v3i32:
241 ; GFX6: ; %bb.0:
242 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
243 ; GFX6-NEXT: v_not_b32_e32 v6, v3
244 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v6
245 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
246 ; GFX6-NEXT: v_not_b32_e32 v3, v4
247 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v3
248 ; GFX6-NEXT: v_not_b32_e32 v3, v5
249 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v3
250 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
251 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
252 ; GFX6-NEXT: s_setpc_b64 s[30:31]
253 ;
254 ; GFX8-LABEL: v_uaddsat_v3i32:
255 ; GFX8: ; %bb.0:
256 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
257 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v3 clamp
258 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v4 clamp
259 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v5 clamp
260 ; GFX8-NEXT: s_setpc_b64 s[30:31]
261 ;
262 ; GFX9-LABEL: v_uaddsat_v3i32:
263 ; GFX9: ; %bb.0:
264 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
265 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v3 clamp
266 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v4 clamp
267 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v5 clamp
268 ; GFX9-NEXT: s_setpc_b64 s[30:31]
269 %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
270 ret <3 x i32> %result
271 }
273 define <4 x i32> @v_uaddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
274 ; GFX6-LABEL: v_uaddsat_v4i32:
275 ; GFX6: ; %bb.0:
276 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
277 ; GFX6-NEXT: v_not_b32_e32 v8, v4
278 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v8
279 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
280 ; GFX6-NEXT: v_not_b32_e32 v4, v5
281 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v4
282 ; GFX6-NEXT: v_not_b32_e32 v4, v6
283 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v4
284 ; GFX6-NEXT: v_not_b32_e32 v4, v7
285 ; GFX6-NEXT: v_min_u32_e32 v3, v3, v4
286 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
287 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6
288 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7
289 ; GFX6-NEXT: s_setpc_b64 s[30:31]
290 ;
291 ; GFX8-LABEL: v_uaddsat_v4i32:
292 ; GFX8: ; %bb.0:
293 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
294 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v4 clamp
295 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v5 clamp
296 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v6 clamp
297 ; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v7 clamp
298 ; GFX8-NEXT: s_setpc_b64 s[30:31]
299 ;
300 ; GFX9-LABEL: v_uaddsat_v4i32:
301 ; GFX9: ; %bb.0:
302 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
303 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v4 clamp
304 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v5 clamp
305 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v6 clamp
306 ; GFX9-NEXT: v_add_u32_e64 v3, v3, v7 clamp
307 ; GFX9-NEXT: s_setpc_b64 s[30:31]
308 %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
309 ret <4 x i32> %result
310 }
312 define <8 x i32> @v_uaddsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {
313 ; GFX6-LABEL: v_uaddsat_v8i32:
314 ; GFX6: ; %bb.0:
315 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
316 ; GFX6-NEXT: v_not_b32_e32 v16, v8
317 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v16
318 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v8
319 ; GFX6-NEXT: v_not_b32_e32 v8, v9
320 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v8
321 ; GFX6-NEXT: v_not_b32_e32 v8, v10
322 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v8
323 ; GFX6-NEXT: v_not_b32_e32 v8, v11
324 ; GFX6-NEXT: v_min_u32_e32 v3, v3, v8
325 ; GFX6-NEXT: v_not_b32_e32 v8, v12
326 ; GFX6-NEXT: v_min_u32_e32 v4, v4, v8
327 ; GFX6-NEXT: v_not_b32_e32 v8, v13
328 ; GFX6-NEXT: v_min_u32_e32 v5, v5, v8
329 ; GFX6-NEXT: v_not_b32_e32 v8, v14
330 ; GFX6-NEXT: v_min_u32_e32 v6, v6, v8
331 ; GFX6-NEXT: v_not_b32_e32 v8, v15
332 ; GFX6-NEXT: v_min_u32_e32 v7, v7, v8
333 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v9
334 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v10
335 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v11
336 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v12
337 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v13
338 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v14
339 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v15
340 ; GFX6-NEXT: s_setpc_b64 s[30:31]
341 ;
342 ; GFX8-LABEL: v_uaddsat_v8i32:
343 ; GFX8: ; %bb.0:
344 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
345 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v8 clamp
346 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v9 clamp
347 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v10 clamp
348 ; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v11 clamp
349 ; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v12 clamp
350 ; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v13 clamp
351 ; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v14 clamp
352 ; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v15 clamp
353 ; GFX8-NEXT: s_setpc_b64 s[30:31]
354 ;
355 ; GFX9-LABEL: v_uaddsat_v8i32:
356 ; GFX9: ; %bb.0:
357 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
358 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v8 clamp
359 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v9 clamp
360 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v10 clamp
361 ; GFX9-NEXT: v_add_u32_e64 v3, v3, v11 clamp
362 ; GFX9-NEXT: v_add_u32_e64 v4, v4, v12 clamp
363 ; GFX9-NEXT: v_add_u32_e64 v5, v5, v13 clamp
364 ; GFX9-NEXT: v_add_u32_e64 v6, v6, v14 clamp
365 ; GFX9-NEXT: v_add_u32_e64 v7, v7, v15 clamp
366 ; GFX9-NEXT: s_setpc_b64 s[30:31]
367 %result = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)
368 ret <8 x i32> %result
369 }
371 define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
372 ; GFX6-LABEL: v_uaddsat_v16i32:
373 ; GFX6: ; %bb.0:
374 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
375 ; GFX6-NEXT: v_not_b32_e32 v32, v16
376 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v32
377 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16
378 ; GFX6-NEXT: v_not_b32_e32 v16, v17
379 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v16
380 ; GFX6-NEXT: v_not_b32_e32 v16, v18
381 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v16
382 ; GFX6-NEXT: v_not_b32_e32 v16, v19
383 ; GFX6-NEXT: v_min_u32_e32 v3, v3, v16
384 ; GFX6-NEXT: v_not_b32_e32 v16, v20
385 ; GFX6-NEXT: v_min_u32_e32 v4, v4, v16
386 ; GFX6-NEXT: v_not_b32_e32 v16, v21
387 ; GFX6-NEXT: v_min_u32_e32 v5, v5, v16
388 ; GFX6-NEXT: v_not_b32_e32 v16, v22
389 ; GFX6-NEXT: v_min_u32_e32 v6, v6, v16
390 ; GFX6-NEXT: v_not_b32_e32 v16, v23
391 ; GFX6-NEXT: v_min_u32_e32 v7, v7, v16
392 ; GFX6-NEXT: v_not_b32_e32 v16, v24
393 ; GFX6-NEXT: v_min_u32_e32 v8, v8, v16
394 ; GFX6-NEXT: v_not_b32_e32 v16, v25
395 ; GFX6-NEXT: v_min_u32_e32 v9, v9, v16
396 ; GFX6-NEXT: v_not_b32_e32 v16, v26
397 ; GFX6-NEXT: v_min_u32_e32 v10, v10, v16
398 ; GFX6-NEXT: v_not_b32_e32 v16, v27
399 ; GFX6-NEXT: v_min_u32_e32 v11, v11, v16
400 ; GFX6-NEXT: v_not_b32_e32 v16, v28
401 ; GFX6-NEXT: v_min_u32_e32 v12, v12, v16
402 ; GFX6-NEXT: v_not_b32_e32 v16, v29
403 ; GFX6-NEXT: v_min_u32_e32 v13, v13, v16
404 ; GFX6-NEXT: v_not_b32_e32 v16, v30
405 ; GFX6-NEXT: v_min_u32_e32 v14, v14, v16
406 ; GFX6-NEXT: v_not_b32_e32 v16, v31
407 ; GFX6-NEXT: v_min_u32_e32 v15, v15, v16
408 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v17
409 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v18
410 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v19
411 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v20
412 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v21
413 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v22
414 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v23
415 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v24
416 ; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v25
417 ; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v26
418 ; GFX6-NEXT: v_add_i32_e32 v11, vcc, v11, v27
419 ; GFX6-NEXT: v_add_i32_e32 v12, vcc, v12, v28
420 ; GFX6-NEXT: v_add_i32_e32 v13, vcc, v13, v29
421 ; GFX6-NEXT: v_add_i32_e32 v14, vcc, v14, v30
422 ; GFX6-NEXT: v_add_i32_e32 v15, vcc, v15, v31
423 ; GFX6-NEXT: s_setpc_b64 s[30:31]
424 ;
425 ; GFX8-LABEL: v_uaddsat_v16i32:
426 ; GFX8: ; %bb.0:
427 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
428 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v16 clamp
429 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v17 clamp
430 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v18 clamp
431 ; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v19 clamp
432 ; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v20 clamp
433 ; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v21 clamp
434 ; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v22 clamp
435 ; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v23 clamp
436 ; GFX8-NEXT: v_add_u32_e64 v8, s[4:5], v8, v24 clamp
437 ; GFX8-NEXT: v_add_u32_e64 v9, s[4:5], v9, v25 clamp
438 ; GFX8-NEXT: v_add_u32_e64 v10, s[4:5], v10, v26 clamp
439 ; GFX8-NEXT: v_add_u32_e64 v11, s[4:5], v11, v27 clamp
440 ; GFX8-NEXT: v_add_u32_e64 v12, s[4:5], v12, v28 clamp
441 ; GFX8-NEXT: v_add_u32_e64 v13, s[4:5], v13, v29 clamp
442 ; GFX8-NEXT: v_add_u32_e64 v14, s[4:5], v14, v30 clamp
443 ; GFX8-NEXT: v_add_u32_e64 v15, s[4:5], v15, v31 clamp
444 ; GFX8-NEXT: s_setpc_b64 s[30:31]
445 ;
446 ; GFX9-LABEL: v_uaddsat_v16i32:
447 ; GFX9: ; %bb.0:
448 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
449 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v16 clamp
450 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v17 clamp
451 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v18 clamp
452 ; GFX9-NEXT: v_add_u32_e64 v3, v3, v19 clamp
453 ; GFX9-NEXT: v_add_u32_e64 v4, v4, v20 clamp
454 ; GFX9-NEXT: v_add_u32_e64 v5, v5, v21 clamp
455 ; GFX9-NEXT: v_add_u32_e64 v6, v6, v22 clamp
456 ; GFX9-NEXT: v_add_u32_e64 v7, v7, v23 clamp
457 ; GFX9-NEXT: v_add_u32_e64 v8, v8, v24 clamp
458 ; GFX9-NEXT: v_add_u32_e64 v9, v9, v25 clamp
459 ; GFX9-NEXT: v_add_u32_e64 v10, v10, v26 clamp
460 ; GFX9-NEXT: v_add_u32_e64 v11, v11, v27 clamp
461 ; GFX9-NEXT: v_add_u32_e64 v12, v12, v28 clamp
462 ; GFX9-NEXT: v_add_u32_e64 v13, v13, v29 clamp
463 ; GFX9-NEXT: v_add_u32_e64 v14, v14, v30 clamp
464 ; GFX9-NEXT: v_add_u32_e64 v15, v15, v31 clamp
465 ; GFX9-NEXT: s_setpc_b64 s[30:31]
466 %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
467 ret <16 x i32> %result
468 }
471 define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
472 ; GFX6-LABEL: v_uaddsat_i64:
473 ; GFX6: ; %bb.0:
474 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
475 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v0, v2
476 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
477 ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
478 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
479 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
480 ; GFX6-NEXT: s_setpc_b64 s[30:31]
481 ;
482 ; GFX8-LABEL: v_uaddsat_i64:
483 ; GFX8: ; %bb.0:
484 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
485 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v2
486 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
487 ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
488 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
489 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
490 ; GFX8-NEXT: s_setpc_b64 s[30:31]
491 ;
492 ; GFX9-LABEL: v_uaddsat_i64:
493 ; GFX9: ; %bb.0:
494 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
495 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
496 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc
497 ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
498 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
499 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
500 ; GFX9-NEXT: s_setpc_b64 s[30:31]
501 %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
502 ret i64 %result
503 }
505 declare i8 @llvm.uadd.sat.i8(i8, i8) #0
506 declare i16 @llvm.uadd.sat.i16(i16, i16) #0
507 declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>) #0
508 declare <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16>, <3 x i16>) #0
509 declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>) #0
510 declare i32 @llvm.uadd.sat.i32(i32, i32) #0
511 declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>) #0
512 declare <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32>, <3 x i32>) #0
513 declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #0
514 declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>) #0
515 declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>) #0
516 declare i64 @llvm.uadd.sat.i64(i64, i64) #0
518 attributes #0 = { nounwind readnone speculatable willreturn }