| blob | 287e52d5044d621bdc9e02a36ba28988a559e822 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
6 ; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
7 ; RUN: llc < %s -mtriple=armv5te-none-eabi -mattr=+dsp | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
8 ; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
10 declare i4 @llvm.sadd.sat.i4(i4, i4)
11 declare i8 @llvm.sadd.sat.i8(i8, i8)
12 declare i16 @llvm.sadd.sat.i16(i16, i16)
13 declare i32 @llvm.sadd.sat.i32(i32, i32)
14 declare i64 @llvm.sadd.sat.i64(i64, i64)
16 define i32 @func(i32 %x, i32 %y) nounwind {
17 ; CHECK-T1-LABEL: func:
18 ; CHECK-T1: @ %bb.0:
19 ; CHECK-T1-NEXT: adds r0, r0, r1
20 ; CHECK-T1-NEXT: bvc .LBB0_2
21 ; CHECK-T1-NEXT: @ %bb.1:
22 ; CHECK-T1-NEXT: asrs r1, r0, #31
23 ; CHECK-T1-NEXT: movs r0, #1
24 ; CHECK-T1-NEXT: lsls r0, r0, #31
25 ; CHECK-T1-NEXT: eors r0, r1
26 ; CHECK-T1-NEXT: .LBB0_2:
27 ; CHECK-T1-NEXT: bx lr
28 ;
29 ; CHECK-T2NODSP-LABEL: func:
30 ; CHECK-T2NODSP: @ %bb.0:
31 ; CHECK-T2NODSP-NEXT: adds r0, r0, r1
32 ; CHECK-T2NODSP-NEXT: mov.w r1, #-2147483648
33 ; CHECK-T2NODSP-NEXT: it vs
34 ; CHECK-T2NODSP-NEXT: eorvs.w r0, r1, r0, asr #31
35 ; CHECK-T2NODSP-NEXT: bx lr
36 ;
37 ; CHECK-T2DSP-LABEL: func:
38 ; CHECK-T2DSP: @ %bb.0:
39 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
40 ; CHECK-T2DSP-NEXT: bx lr
41 ;
42 ; CHECK-ARMNODPS-LABEL: func:
43 ; CHECK-ARMNODPS: @ %bb.0:
44 ; CHECK-ARMNODPS-NEXT: adds r0, r0, r1
45 ; CHECK-ARMNODPS-NEXT: mov r1, #-2147483648
46 ; CHECK-ARMNODPS-NEXT: eorvs r0, r1, r0, asr #31
47 ; CHECK-ARMNODPS-NEXT: bx lr
48 ;
49 ; CHECK-ARMBASEDSP-LABEL: func:
50 ; CHECK-ARMBASEDSP: @ %bb.0:
51 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
52 ; CHECK-ARMBASEDSP-NEXT: bx lr
53 ;
54 ; CHECK-ARMDSP-LABEL: func:
55 ; CHECK-ARMDSP: @ %bb.0:
56 ; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
57 ; CHECK-ARMDSP-NEXT: bx lr
58 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
59 ret i32 %tmp
60 }
62 define i64 @func2(i64 %x, i64 %y) nounwind {
63 ; CHECK-T1-LABEL: func2:
64 ; CHECK-T1: @ %bb.0:
65 ; CHECK-T1-NEXT: .save {r4, lr}
66 ; CHECK-T1-NEXT: push {r4, lr}
67 ; CHECK-T1-NEXT: mov r4, r1
68 ; CHECK-T1-NEXT: eors r1, r3
69 ; CHECK-T1-NEXT: adds r2, r0, r2
70 ; CHECK-T1-NEXT: adcs r3, r4
71 ; CHECK-T1-NEXT: eors r4, r3
72 ; CHECK-T1-NEXT: bics r4, r1
73 ; CHECK-T1-NEXT: asrs r1, r3, #31
74 ; CHECK-T1-NEXT: cmp r4, #0
75 ; CHECK-T1-NEXT: mov r0, r1
76 ; CHECK-T1-NEXT: bmi .LBB1_2
77 ; CHECK-T1-NEXT: @ %bb.1:
78 ; CHECK-T1-NEXT: mov r0, r2
79 ; CHECK-T1-NEXT: .LBB1_2:
80 ; CHECK-T1-NEXT: cmp r4, #0
81 ; CHECK-T1-NEXT: bmi .LBB1_4
82 ; CHECK-T1-NEXT: @ %bb.3:
83 ; CHECK-T1-NEXT: mov r1, r3
84 ; CHECK-T1-NEXT: pop {r4, pc}
85 ; CHECK-T1-NEXT: .LBB1_4:
86 ; CHECK-T1-NEXT: movs r2, #1
87 ; CHECK-T1-NEXT: lsls r2, r2, #31
88 ; CHECK-T1-NEXT: eors r1, r2
89 ; CHECK-T1-NEXT: pop {r4, pc}
90 ;
91 ; CHECK-T2-LABEL: func2:
92 ; CHECK-T2: @ %bb.0:
93 ; CHECK-T2-NEXT: adds r0, r0, r2
94 ; CHECK-T2-NEXT: eor.w r12, r1, r3
95 ; CHECK-T2-NEXT: adc.w r2, r1, r3
96 ; CHECK-T2-NEXT: eors r1, r2
97 ; CHECK-T2-NEXT: bic.w r1, r1, r12
98 ; CHECK-T2-NEXT: cmp r1, #0
99 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
100 ; CHECK-T2-NEXT: it mi
101 ; CHECK-T2-NEXT: asrmi r0, r2, #31
102 ; CHECK-T2-NEXT: it mi
103 ; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
104 ; CHECK-T2-NEXT: mov r1, r2
105 ; CHECK-T2-NEXT: bx lr
106 ;
107 ; CHECK-ARM-LABEL: func2:
108 ; CHECK-ARM: @ %bb.0:
109 ; CHECK-ARM-NEXT: adds r0, r0, r2
110 ; CHECK-ARM-NEXT: eor r12, r1, r3
111 ; CHECK-ARM-NEXT: adc r2, r1, r3
112 ; CHECK-ARM-NEXT: eor r1, r1, r2
113 ; CHECK-ARM-NEXT: bic r1, r1, r12
114 ; CHECK-ARM-NEXT: cmp r1, #0
115 ; CHECK-ARM-NEXT: mov r1, #-2147483648
116 ; CHECK-ARM-NEXT: asrmi r0, r2, #31
117 ; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
118 ; CHECK-ARM-NEXT: mov r1, r2
119 ; CHECK-ARM-NEXT: bx lr
120 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
121 ret i64 %tmp
122 }
124 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
125 ; CHECK-T1-LABEL: func16:
126 ; CHECK-T1: @ %bb.0:
127 ; CHECK-T1-NEXT: adds r0, r0, r1
128 ; CHECK-T1-NEXT: ldr r1, .LCPI2_0
129 ; CHECK-T1-NEXT: cmp r0, r1
130 ; CHECK-T1-NEXT: blt .LBB2_2
131 ; CHECK-T1-NEXT: @ %bb.1:
132 ; CHECK-T1-NEXT: mov r0, r1
133 ; CHECK-T1-NEXT: .LBB2_2:
134 ; CHECK-T1-NEXT: ldr r1, .LCPI2_1
135 ; CHECK-T1-NEXT: cmp r0, r1
136 ; CHECK-T1-NEXT: bgt .LBB2_4
137 ; CHECK-T1-NEXT: @ %bb.3:
138 ; CHECK-T1-NEXT: mov r0, r1
139 ; CHECK-T1-NEXT: .LBB2_4:
140 ; CHECK-T1-NEXT: bx lr
141 ; CHECK-T1-NEXT: .p2align 2
142 ; CHECK-T1-NEXT: @ %bb.5:
143 ; CHECK-T1-NEXT: .LCPI2_0:
144 ; CHECK-T1-NEXT: .long 32767 @ 0x7fff
145 ; CHECK-T1-NEXT: .LCPI2_1:
146 ; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
147 ;
148 ; CHECK-T2NODSP-LABEL: func16:
149 ; CHECK-T2NODSP: @ %bb.0:
150 ; CHECK-T2NODSP-NEXT: add r0, r1
151 ; CHECK-T2NODSP-NEXT: movw r1, #32767
152 ; CHECK-T2NODSP-NEXT: cmp r0, r1
153 ; CHECK-T2NODSP-NEXT: it lt
154 ; CHECK-T2NODSP-NEXT: movlt r1, r0
155 ; CHECK-T2NODSP-NEXT: movw r0, #32768
156 ; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
157 ; CHECK-T2NODSP-NEXT: movt r0, #65535
158 ; CHECK-T2NODSP-NEXT: it gt
159 ; CHECK-T2NODSP-NEXT: movgt r0, r1
160 ; CHECK-T2NODSP-NEXT: bx lr
161 ;
162 ; CHECK-T2DSP-LABEL: func16:
163 ; CHECK-T2DSP: @ %bb.0:
164 ; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1
165 ; CHECK-T2DSP-NEXT: sxth r0, r0
166 ; CHECK-T2DSP-NEXT: bx lr
167 ;
168 ; CHECK-ARMNODPS-LABEL: func16:
169 ; CHECK-ARMNODPS: @ %bb.0:
170 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
171 ; CHECK-ARMNODPS-NEXT: mov r1, #255
172 ; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
173 ; CHECK-ARMNODPS-NEXT: cmp r0, r1
174 ; CHECK-ARMNODPS-NEXT: movlt r1, r0
175 ; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
176 ; CHECK-ARMNODPS-NEXT: cmn r1, #32768
177 ; CHECK-ARMNODPS-NEXT: movgt r0, r1
178 ; CHECK-ARMNODPS-NEXT: bx lr
179 ; CHECK-ARMNODPS-NEXT: .p2align 2
180 ; CHECK-ARMNODPS-NEXT: @ %bb.1:
181 ; CHECK-ARMNODPS-NEXT: .LCPI2_0:
182 ; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000
183 ;
184 ; CHECK-ARMBASEDSP-LABEL: func16:
185 ; CHECK-ARMBASEDSP: @ %bb.0:
186 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #16
187 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #16
188 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
189 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #16
190 ; CHECK-ARMBASEDSP-NEXT: bx lr
191 ;
192 ; CHECK-ARMDSP-LABEL: func16:
193 ; CHECK-ARMDSP: @ %bb.0:
194 ; CHECK-ARMDSP-NEXT: qadd16 r0, r0, r1
195 ; CHECK-ARMDSP-NEXT: sxth r0, r0
196 ; CHECK-ARMDSP-NEXT: bx lr
197 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
198 ret i16 %tmp
199 }
201 define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
202 ; CHECK-T1-LABEL: func8:
203 ; CHECK-T1: @ %bb.0:
204 ; CHECK-T1-NEXT: adds r0, r0, r1
205 ; CHECK-T1-NEXT: movs r1, #127
206 ; CHECK-T1-NEXT: cmp r0, #127
207 ; CHECK-T1-NEXT: blt .LBB3_2
208 ; CHECK-T1-NEXT: @ %bb.1:
209 ; CHECK-T1-NEXT: mov r0, r1
210 ; CHECK-T1-NEXT: .LBB3_2:
211 ; CHECK-T1-NEXT: mvns r1, r1
212 ; CHECK-T1-NEXT: cmp r0, r1
213 ; CHECK-T1-NEXT: bgt .LBB3_4
214 ; CHECK-T1-NEXT: @ %bb.3:
215 ; CHECK-T1-NEXT: mov r0, r1
216 ; CHECK-T1-NEXT: .LBB3_4:
217 ; CHECK-T1-NEXT: bx lr
218 ;
219 ; CHECK-T2NODSP-LABEL: func8:
220 ; CHECK-T2NODSP: @ %bb.0:
221 ; CHECK-T2NODSP-NEXT: add r0, r1
222 ; CHECK-T2NODSP-NEXT: cmp r0, #127
223 ; CHECK-T2NODSP-NEXT: it ge
224 ; CHECK-T2NODSP-NEXT: movge r0, #127
225 ; CHECK-T2NODSP-NEXT: cmn.w r0, #128
226 ; CHECK-T2NODSP-NEXT: it le
227 ; CHECK-T2NODSP-NEXT: mvnle r0, #127
228 ; CHECK-T2NODSP-NEXT: bx lr
229 ;
230 ; CHECK-T2DSP-LABEL: func8:
231 ; CHECK-T2DSP: @ %bb.0:
232 ; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1
233 ; CHECK-T2DSP-NEXT: sxtb r0, r0
234 ; CHECK-T2DSP-NEXT: bx lr
235 ;
236 ; CHECK-ARMNODPS-LABEL: func8:
237 ; CHECK-ARMNODPS: @ %bb.0:
238 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
239 ; CHECK-ARMNODPS-NEXT: cmp r0, #127
240 ; CHECK-ARMNODPS-NEXT: movge r0, #127
241 ; CHECK-ARMNODPS-NEXT: cmn r0, #128
242 ; CHECK-ARMNODPS-NEXT: mvnle r0, #127
243 ; CHECK-ARMNODPS-NEXT: bx lr
244 ;
245 ; CHECK-ARMBASEDSP-LABEL: func8:
246 ; CHECK-ARMBASEDSP: @ %bb.0:
247 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #24
248 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #24
249 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
250 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #24
251 ; CHECK-ARMBASEDSP-NEXT: bx lr
252 ;
253 ; CHECK-ARMDSP-LABEL: func8:
254 ; CHECK-ARMDSP: @ %bb.0:
255 ; CHECK-ARMDSP-NEXT: qadd8 r0, r0, r1
256 ; CHECK-ARMDSP-NEXT: sxtb r0, r0
257 ; CHECK-ARMDSP-NEXT: bx lr
258 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
259 ret i8 %tmp
260 }
262 define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
263 ; CHECK-T1-LABEL: func3:
264 ; CHECK-T1: @ %bb.0:
265 ; CHECK-T1-NEXT: adds r0, r0, r1
266 ; CHECK-T1-NEXT: movs r1, #7
267 ; CHECK-T1-NEXT: cmp r0, #7
268 ; CHECK-T1-NEXT: blt .LBB4_2
269 ; CHECK-T1-NEXT: @ %bb.1:
270 ; CHECK-T1-NEXT: mov r0, r1
271 ; CHECK-T1-NEXT: .LBB4_2:
272 ; CHECK-T1-NEXT: mvns r1, r1
273 ; CHECK-T1-NEXT: cmp r0, r1
274 ; CHECK-T1-NEXT: bgt .LBB4_4
275 ; CHECK-T1-NEXT: @ %bb.3:
276 ; CHECK-T1-NEXT: mov r0, r1
277 ; CHECK-T1-NEXT: .LBB4_4:
278 ; CHECK-T1-NEXT: bx lr
279 ;
280 ; CHECK-T2NODSP-LABEL: func3:
281 ; CHECK-T2NODSP: @ %bb.0:
282 ; CHECK-T2NODSP-NEXT: add r0, r1
283 ; CHECK-T2NODSP-NEXT: cmp r0, #7
284 ; CHECK-T2NODSP-NEXT: it ge
285 ; CHECK-T2NODSP-NEXT: movge r0, #7
286 ; CHECK-T2NODSP-NEXT: cmn.w r0, #8
287 ; CHECK-T2NODSP-NEXT: it le
288 ; CHECK-T2NODSP-NEXT: mvnle r0, #7
289 ; CHECK-T2NODSP-NEXT: bx lr
290 ;
291 ; CHECK-T2DSP-LABEL: func3:
292 ; CHECK-T2DSP: @ %bb.0:
293 ; CHECK-T2DSP-NEXT: lsls r1, r1, #28
294 ; CHECK-T2DSP-NEXT: lsls r0, r0, #28
295 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
296 ; CHECK-T2DSP-NEXT: asrs r0, r0, #28
297 ; CHECK-T2DSP-NEXT: bx lr
298 ;
299 ; CHECK-ARMNODPS-LABEL: func3:
300 ; CHECK-ARMNODPS: @ %bb.0:
301 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
302 ; CHECK-ARMNODPS-NEXT: cmp r0, #7
303 ; CHECK-ARMNODPS-NEXT: movge r0, #7
304 ; CHECK-ARMNODPS-NEXT: cmn r0, #8
305 ; CHECK-ARMNODPS-NEXT: mvnle r0, #7
306 ; CHECK-ARMNODPS-NEXT: bx lr
307 ;
308 ; CHECK-ARMBASEDSP-LABEL: func3:
309 ; CHECK-ARMBASEDSP: @ %bb.0:
310 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #28
311 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #28
312 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
313 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #28
314 ; CHECK-ARMBASEDSP-NEXT: bx lr
315 ;
316 ; CHECK-ARMDSP-LABEL: func3:
317 ; CHECK-ARMDSP: @ %bb.0:
318 ; CHECK-ARMDSP-NEXT: lsl r0, r0, #28
319 ; CHECK-ARMDSP-NEXT: lsl r1, r1, #28
320 ; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
321 ; CHECK-ARMDSP-NEXT: asr r0, r0, #28
322 ; CHECK-ARMDSP-NEXT: bx lr
323 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y)
324 ret i4 %tmp
325 }