| blob | 5ba72fcb427c60c6b3306a554fb1e6eb80e5321f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv5-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM5
3 ; RUN: llc -mtriple=armv6-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM6
4 ; RUN: llc -mtriple=armv7-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM7
5 ; RUN: llc -mtriple=armv8-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM8
6 ; RUN: llc -mtriple=armv7-unknown-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=NEON7
7 ; RUN: llc -mtriple=armv8-unknown-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=NEON8
9 define i1 @test_srem_odd(i29 %X) nounwind {
10 ; ARM5-LABEL: test_srem_odd:
11 ; ARM5: @ %bb.0:
12 ; ARM5-NEXT: ldr r2, .LCPI0_1
13 ; ARM5-NEXT: ldr r1, .LCPI0_0
14 ; ARM5-NEXT: mla r3, r0, r2, r1
15 ; ARM5-NEXT: ldr r2, .LCPI0_2
16 ; ARM5-NEXT: mov r0, #0
17 ; ARM5-NEXT: bic r1, r3, #-536870912
18 ; ARM5-NEXT: cmp r1, r2
19 ; ARM5-NEXT: movlo r0, #1
20 ; ARM5-NEXT: bx lr
21 ; ARM5-NEXT: .p2align 2
22 ; ARM5-NEXT: @ %bb.1:
23 ; ARM5-NEXT: .LCPI0_0:
24 ; ARM5-NEXT: .long 2711469 @ 0x295fad
25 ; ARM5-NEXT: .LCPI0_1:
26 ; ARM5-NEXT: .long 526025035 @ 0x1f5a814b
27 ; ARM5-NEXT: .LCPI0_2:
28 ; ARM5-NEXT: .long 5422939 @ 0x52bf5b
29 ;
30 ; ARM6-LABEL: test_srem_odd:
31 ; ARM6: @ %bb.0:
32 ; ARM6-NEXT: ldr r2, .LCPI0_1
33 ; ARM6-NEXT: ldr r1, .LCPI0_0
34 ; ARM6-NEXT: mla r0, r0, r2, r1
35 ; ARM6-NEXT: ldr r2, .LCPI0_2
36 ; ARM6-NEXT: bic r1, r0, #-536870912
37 ; ARM6-NEXT: mov r0, #0
38 ; ARM6-NEXT: cmp r1, r2
39 ; ARM6-NEXT: movlo r0, #1
40 ; ARM6-NEXT: bx lr
41 ; ARM6-NEXT: .p2align 2
42 ; ARM6-NEXT: @ %bb.1:
43 ; ARM6-NEXT: .LCPI0_0:
44 ; ARM6-NEXT: .long 2711469 @ 0x295fad
45 ; ARM6-NEXT: .LCPI0_1:
46 ; ARM6-NEXT: .long 526025035 @ 0x1f5a814b
47 ; ARM6-NEXT: .LCPI0_2:
48 ; ARM6-NEXT: .long 5422939 @ 0x52bf5b
49 ;
50 ; ARM7-LABEL: test_srem_odd:
51 ; ARM7: @ %bb.0:
52 ; ARM7-NEXT: movw r1, #24493
53 ; ARM7-NEXT: movw r2, #33099
54 ; ARM7-NEXT: movt r1, #41
55 ; ARM7-NEXT: movt r2, #8026
56 ; ARM7-NEXT: mla r0, r0, r2, r1
57 ; ARM7-NEXT: movw r2, #48987
58 ; ARM7-NEXT: movt r2, #82
59 ; ARM7-NEXT: bic r1, r0, #-536870912
60 ; ARM7-NEXT: mov r0, #0
61 ; ARM7-NEXT: cmp r1, r2
62 ; ARM7-NEXT: movwlo r0, #1
63 ; ARM7-NEXT: bx lr
64 ;
65 ; ARM8-LABEL: test_srem_odd:
66 ; ARM8: @ %bb.0:
67 ; ARM8-NEXT: movw r1, #24493
68 ; ARM8-NEXT: movw r2, #33099
69 ; ARM8-NEXT: movt r1, #41
70 ; ARM8-NEXT: movt r2, #8026
71 ; ARM8-NEXT: mla r0, r0, r2, r1
72 ; ARM8-NEXT: movw r2, #48987
73 ; ARM8-NEXT: movt r2, #82
74 ; ARM8-NEXT: bic r1, r0, #-536870912
75 ; ARM8-NEXT: mov r0, #0
76 ; ARM8-NEXT: cmp r1, r2
77 ; ARM8-NEXT: movwlo r0, #1
78 ; ARM8-NEXT: bx lr
79 ;
80 ; NEON7-LABEL: test_srem_odd:
81 ; NEON7: @ %bb.0:
82 ; NEON7-NEXT: movw r1, #24493
83 ; NEON7-NEXT: movw r2, #33099
84 ; NEON7-NEXT: movt r1, #41
85 ; NEON7-NEXT: movt r2, #8026
86 ; NEON7-NEXT: mla r0, r0, r2, r1
87 ; NEON7-NEXT: movw r2, #48987
88 ; NEON7-NEXT: movt r2, #82
89 ; NEON7-NEXT: bic r1, r0, #-536870912
90 ; NEON7-NEXT: mov r0, #0
91 ; NEON7-NEXT: cmp r1, r2
92 ; NEON7-NEXT: movwlo r0, #1
93 ; NEON7-NEXT: bx lr
94 ;
95 ; NEON8-LABEL: test_srem_odd:
96 ; NEON8: @ %bb.0:
97 ; NEON8-NEXT: movw r1, #24493
98 ; NEON8-NEXT: movw r2, #33099
99 ; NEON8-NEXT: movt r1, #41
100 ; NEON8-NEXT: movt r2, #8026
101 ; NEON8-NEXT: mla r0, r0, r2, r1
102 ; NEON8-NEXT: movw r2, #48987
103 ; NEON8-NEXT: movt r2, #82
104 ; NEON8-NEXT: bic r1, r0, #-536870912
105 ; NEON8-NEXT: mov r0, #0
106 ; NEON8-NEXT: cmp r1, r2
107 ; NEON8-NEXT: movwlo r0, #1
108 ; NEON8-NEXT: bx lr
109 %srem = srem i29 %X, 99
110 %cmp = icmp eq i29 %srem, 0
111 ret i1 %cmp
112 }
114 define i1 @test_srem_even(i4 %X) nounwind {
115 ; ARM5-LABEL: test_srem_even:
116 ; ARM5: @ %bb.0:
117 ; ARM5-NEXT: ldr r2, .LCPI1_0
118 ; ARM5-NEXT: lsl r0, r0, #28
119 ; ARM5-NEXT: asr r12, r0, #28
120 ; ARM5-NEXT: smull r3, r1, r12, r2
121 ; ARM5-NEXT: add r1, r1, r1, lsr #31
122 ; ARM5-NEXT: add r1, r1, r1, lsl #1
123 ; ARM5-NEXT: mvn r1, r1, lsl #1
124 ; ARM5-NEXT: add r0, r1, r0, asr #28
125 ; ARM5-NEXT: clz r0, r0
126 ; ARM5-NEXT: lsr r0, r0, #5
127 ; ARM5-NEXT: bx lr
128 ; ARM5-NEXT: .p2align 2
129 ; ARM5-NEXT: @ %bb.1:
130 ; ARM5-NEXT: .LCPI1_0:
131 ; ARM5-NEXT: .long 715827883 @ 0x2aaaaaab
132 ;
133 ; ARM6-LABEL: test_srem_even:
134 ; ARM6: @ %bb.0:
135 ; ARM6-NEXT: ldr r2, .LCPI1_0
136 ; ARM6-NEXT: lsl r0, r0, #28
137 ; ARM6-NEXT: asr r1, r0, #28
138 ; ARM6-NEXT: smmul r1, r1, r2
139 ; ARM6-NEXT: add r1, r1, r1, lsr #31
140 ; ARM6-NEXT: add r1, r1, r1, lsl #1
141 ; ARM6-NEXT: mvn r1, r1, lsl #1
142 ; ARM6-NEXT: add r0, r1, r0, asr #28
143 ; ARM6-NEXT: clz r0, r0
144 ; ARM6-NEXT: lsr r0, r0, #5
145 ; ARM6-NEXT: bx lr
146 ; ARM6-NEXT: .p2align 2
147 ; ARM6-NEXT: @ %bb.1:
148 ; ARM6-NEXT: .LCPI1_0:
149 ; ARM6-NEXT: .long 715827883 @ 0x2aaaaaab
150 ;
151 ; ARM7-LABEL: test_srem_even:
152 ; ARM7: @ %bb.0:
153 ; ARM7-NEXT: movw r2, #43691
154 ; ARM7-NEXT: sbfx r1, r0, #0, #4
155 ; ARM7-NEXT: movt r2, #10922
156 ; ARM7-NEXT: lsl r0, r0, #28
157 ; ARM7-NEXT: smmul r1, r1, r2
158 ; ARM7-NEXT: add r1, r1, r1, lsr #31
159 ; ARM7-NEXT: add r1, r1, r1, lsl #1
160 ; ARM7-NEXT: mvn r1, r1, lsl #1
161 ; ARM7-NEXT: add r0, r1, r0, asr #28
162 ; ARM7-NEXT: clz r0, r0
163 ; ARM7-NEXT: lsr r0, r0, #5
164 ; ARM7-NEXT: bx lr
165 ;
166 ; ARM8-LABEL: test_srem_even:
167 ; ARM8: @ %bb.0:
168 ; ARM8-NEXT: movw r2, #43691
169 ; ARM8-NEXT: sbfx r1, r0, #0, #4
170 ; ARM8-NEXT: movt r2, #10922
171 ; ARM8-NEXT: lsl r0, r0, #28
172 ; ARM8-NEXT: smmul r1, r1, r2
173 ; ARM8-NEXT: add r1, r1, r1, lsr #31
174 ; ARM8-NEXT: add r1, r1, r1, lsl #1
175 ; ARM8-NEXT: mvn r1, r1, lsl #1
176 ; ARM8-NEXT: add r0, r1, r0, asr #28
177 ; ARM8-NEXT: clz r0, r0
178 ; ARM8-NEXT: lsr r0, r0, #5
179 ; ARM8-NEXT: bx lr
180 ;
181 ; NEON7-LABEL: test_srem_even:
182 ; NEON7: @ %bb.0:
183 ; NEON7-NEXT: movw r2, #43691
184 ; NEON7-NEXT: sbfx r1, r0, #0, #4
185 ; NEON7-NEXT: movt r2, #10922
186 ; NEON7-NEXT: lsl r0, r0, #28
187 ; NEON7-NEXT: smmul r1, r1, r2
188 ; NEON7-NEXT: add r1, r1, r1, lsr #31
189 ; NEON7-NEXT: add r1, r1, r1, lsl #1
190 ; NEON7-NEXT: mvn r1, r1, lsl #1
191 ; NEON7-NEXT: add r0, r1, r0, asr #28
192 ; NEON7-NEXT: clz r0, r0
193 ; NEON7-NEXT: lsr r0, r0, #5
194 ; NEON7-NEXT: bx lr
195 ;
196 ; NEON8-LABEL: test_srem_even:
197 ; NEON8: @ %bb.0:
198 ; NEON8-NEXT: movw r2, #43691
199 ; NEON8-NEXT: sbfx r1, r0, #0, #4
200 ; NEON8-NEXT: movt r2, #10922
201 ; NEON8-NEXT: lsl r0, r0, #28
202 ; NEON8-NEXT: smmul r1, r1, r2
203 ; NEON8-NEXT: add r1, r1, r1, lsr #31
204 ; NEON8-NEXT: add r1, r1, r1, lsl #1
205 ; NEON8-NEXT: mvn r1, r1, lsl #1
206 ; NEON8-NEXT: add r0, r1, r0, asr #28
207 ; NEON8-NEXT: clz r0, r0
208 ; NEON8-NEXT: lsr r0, r0, #5
209 ; NEON8-NEXT: bx lr
210 %srem = srem i4 %X, 6
211 %cmp = icmp eq i4 %srem, 1
212 ret i1 %cmp
213 }
215 define i1 @test_srem_pow2_setne(i6 %X) nounwind {
216 ; ARM5-LABEL: test_srem_pow2_setne:
217 ; ARM5: @ %bb.0:
218 ; ARM5-NEXT: lsl r1, r0, #26
219 ; ARM5-NEXT: mov r2, #3
220 ; ARM5-NEXT: asr r1, r1, #26
221 ; ARM5-NEXT: and r1, r2, r1, lsr #9
222 ; ARM5-NEXT: add r1, r0, r1
223 ; ARM5-NEXT: and r1, r1, #60
224 ; ARM5-NEXT: sub r0, r0, r1
225 ; ARM5-NEXT: ands r0, r0, #63
226 ; ARM5-NEXT: movne r0, #1
227 ; ARM5-NEXT: bx lr
228 ;
229 ; ARM6-LABEL: test_srem_pow2_setne:
230 ; ARM6: @ %bb.0:
231 ; ARM6-NEXT: lsl r1, r0, #26
232 ; ARM6-NEXT: mov r2, #3
233 ; ARM6-NEXT: asr r1, r1, #26
234 ; ARM6-NEXT: and r1, r2, r1, lsr #9
235 ; ARM6-NEXT: add r1, r0, r1
236 ; ARM6-NEXT: and r1, r1, #60
237 ; ARM6-NEXT: sub r0, r0, r1
238 ; ARM6-NEXT: ands r0, r0, #63
239 ; ARM6-NEXT: movne r0, #1
240 ; ARM6-NEXT: bx lr
241 ;
242 ; ARM7-LABEL: test_srem_pow2_setne:
243 ; ARM7: @ %bb.0:
244 ; ARM7-NEXT: sbfx r1, r0, #0, #6
245 ; ARM7-NEXT: ubfx r1, r1, #9, #2
246 ; ARM7-NEXT: add r1, r0, r1
247 ; ARM7-NEXT: and r1, r1, #60
248 ; ARM7-NEXT: sub r0, r0, r1
249 ; ARM7-NEXT: ands r0, r0, #63
250 ; ARM7-NEXT: movwne r0, #1
251 ; ARM7-NEXT: bx lr
252 ;
253 ; ARM8-LABEL: test_srem_pow2_setne:
254 ; ARM8: @ %bb.0:
255 ; ARM8-NEXT: sbfx r1, r0, #0, #6
256 ; ARM8-NEXT: ubfx r1, r1, #9, #2
257 ; ARM8-NEXT: add r1, r0, r1
258 ; ARM8-NEXT: and r1, r1, #60
259 ; ARM8-NEXT: sub r0, r0, r1
260 ; ARM8-NEXT: ands r0, r0, #63
261 ; ARM8-NEXT: movwne r0, #1
262 ; ARM8-NEXT: bx lr
263 ;
264 ; NEON7-LABEL: test_srem_pow2_setne:
265 ; NEON7: @ %bb.0:
266 ; NEON7-NEXT: sbfx r1, r0, #0, #6
267 ; NEON7-NEXT: ubfx r1, r1, #9, #2
268 ; NEON7-NEXT: add r1, r0, r1
269 ; NEON7-NEXT: and r1, r1, #60
270 ; NEON7-NEXT: sub r0, r0, r1
271 ; NEON7-NEXT: ands r0, r0, #63
272 ; NEON7-NEXT: movwne r0, #1
273 ; NEON7-NEXT: bx lr
274 ;
275 ; NEON8-LABEL: test_srem_pow2_setne:
276 ; NEON8: @ %bb.0:
277 ; NEON8-NEXT: sbfx r1, r0, #0, #6
278 ; NEON8-NEXT: ubfx r1, r1, #9, #2
279 ; NEON8-NEXT: add r1, r0, r1
280 ; NEON8-NEXT: and r1, r1, #60
281 ; NEON8-NEXT: sub r0, r0, r1
282 ; NEON8-NEXT: ands r0, r0, #63
283 ; NEON8-NEXT: movwne r0, #1
284 ; NEON8-NEXT: bx lr
285 %srem = srem i6 %X, 4
286 %cmp = icmp ne i6 %srem, 0
287 ret i1 %cmp
288 }
290 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
291 ; ARM5-LABEL: test_srem_vec:
292 ; ARM5: @ %bb.0:
293 ; ARM5-NEXT: push {r4, r5, r6, lr}
294 ; ARM5-NEXT: and r1, r1, #1
295 ; ARM5-NEXT: mov r5, r3
296 ; ARM5-NEXT: rsb r1, r1, #0
297 ; ARM5-NEXT: mov r6, r2
298 ; ARM5-NEXT: mov r2, #9
299 ; ARM5-NEXT: mov r3, #0
300 ; ARM5-NEXT: bl __moddi3
301 ; ARM5-NEXT: eor r0, r0, #3
302 ; ARM5-NEXT: mov r2, #9
303 ; ARM5-NEXT: orrs r4, r0, r1
304 ; ARM5-NEXT: and r0, r5, #1
305 ; ARM5-NEXT: rsb r1, r0, #0
306 ; ARM5-NEXT: mov r0, r6
307 ; ARM5-NEXT: mov r3, #0
308 ; ARM5-NEXT: movne r4, #1
309 ; ARM5-NEXT: bl __moddi3
310 ; ARM5-NEXT: mov r2, #1
311 ; ARM5-NEXT: bic r1, r2, r1
312 ; ARM5-NEXT: mvn r2, #2
313 ; ARM5-NEXT: eor r0, r0, r2
314 ; ARM5-NEXT: orrs r5, r0, r1
315 ; ARM5-NEXT: ldr r0, [sp, #20]
316 ; ARM5-NEXT: mvn r2, #8
317 ; ARM5-NEXT: mvn r3, #0
318 ; ARM5-NEXT: and r0, r0, #1
319 ; ARM5-NEXT: movne r5, #1
320 ; ARM5-NEXT: rsb r1, r0, #0
321 ; ARM5-NEXT: ldr r0, [sp, #16]
322 ; ARM5-NEXT: bl __moddi3
323 ; ARM5-NEXT: eor r0, r0, #3
324 ; ARM5-NEXT: orrs r2, r0, r1
325 ; ARM5-NEXT: mov r0, r4
326 ; ARM5-NEXT: movne r2, #1
327 ; ARM5-NEXT: mov r1, r5
328 ; ARM5-NEXT: pop {r4, r5, r6, pc}
329 ;
330 ; ARM6-LABEL: test_srem_vec:
331 ; ARM6: @ %bb.0:
332 ; ARM6-NEXT: push {r4, r5, r6, lr}
333 ; ARM6-NEXT: and r1, r1, #1
334 ; ARM6-NEXT: mov r5, r3
335 ; ARM6-NEXT: rsb r1, r1, #0
336 ; ARM6-NEXT: mov r6, r2
337 ; ARM6-NEXT: mov r2, #9
338 ; ARM6-NEXT: mov r3, #0
339 ; ARM6-NEXT: bl __moddi3
340 ; ARM6-NEXT: eor r0, r0, #3
341 ; ARM6-NEXT: mov r2, #9
342 ; ARM6-NEXT: orrs r4, r0, r1
343 ; ARM6-NEXT: and r0, r5, #1
344 ; ARM6-NEXT: rsb r1, r0, #0
345 ; ARM6-NEXT: mov r0, r6
346 ; ARM6-NEXT: mov r3, #0
347 ; ARM6-NEXT: movne r4, #1
348 ; ARM6-NEXT: bl __moddi3
349 ; ARM6-NEXT: mov r2, #1
350 ; ARM6-NEXT: bic r1, r2, r1
351 ; ARM6-NEXT: mvn r2, #2
352 ; ARM6-NEXT: eor r0, r0, r2
353 ; ARM6-NEXT: orrs r5, r0, r1
354 ; ARM6-NEXT: ldr r0, [sp, #20]
355 ; ARM6-NEXT: mvn r2, #8
356 ; ARM6-NEXT: mvn r3, #0
357 ; ARM6-NEXT: and r0, r0, #1
358 ; ARM6-NEXT: movne r5, #1
359 ; ARM6-NEXT: rsb r1, r0, #0
360 ; ARM6-NEXT: ldr r0, [sp, #16]
361 ; ARM6-NEXT: bl __moddi3
362 ; ARM6-NEXT: eor r0, r0, #3
363 ; ARM6-NEXT: orrs r2, r0, r1
364 ; ARM6-NEXT: mov r0, r4
365 ; ARM6-NEXT: movne r2, #1
366 ; ARM6-NEXT: mov r1, r5
367 ; ARM6-NEXT: pop {r4, r5, r6, pc}
368 ;
369 ; ARM7-LABEL: test_srem_vec:
370 ; ARM7: @ %bb.0:
371 ; ARM7-NEXT: push {r4, r5, r6, r7, r11, lr}
372 ; ARM7-NEXT: vpush {d8, d9}
373 ; ARM7-NEXT: mov r5, r0
374 ; ARM7-NEXT: and r0, r3, #1
375 ; ARM7-NEXT: mov r4, r1
376 ; ARM7-NEXT: rsb r1, r0, #0
377 ; ARM7-NEXT: mov r0, r2
378 ; ARM7-NEXT: mov r2, #9
379 ; ARM7-NEXT: mov r3, #0
380 ; ARM7-NEXT: bl __moddi3
381 ; ARM7-NEXT: mov r6, r0
382 ; ARM7-NEXT: and r0, r4, #1
383 ; ARM7-NEXT: mov r7, r1
384 ; ARM7-NEXT: rsb r1, r0, #0
385 ; ARM7-NEXT: mov r0, r5
386 ; ARM7-NEXT: mov r2, #9
387 ; ARM7-NEXT: mov r3, #0
388 ; ARM7-NEXT: bl __moddi3
389 ; ARM7-NEXT: vmov.32 d8[0], r0
390 ; ARM7-NEXT: ldr r0, [sp, #44]
391 ; ARM7-NEXT: ldr r2, [sp, #40]
392 ; ARM7-NEXT: mov r4, r1
393 ; ARM7-NEXT: and r0, r0, #1
394 ; ARM7-NEXT: mvn r3, #0
395 ; ARM7-NEXT: rsb r1, r0, #0
396 ; ARM7-NEXT: vmov.32 d9[0], r6
397 ; ARM7-NEXT: mov r0, r2
398 ; ARM7-NEXT: mvn r2, #8
399 ; ARM7-NEXT: bl __moddi3
400 ; ARM7-NEXT: vmov.32 d16[0], r0
401 ; ARM7-NEXT: adr r0, .LCPI3_0
402 ; ARM7-NEXT: vmov.32 d9[1], r7
403 ; ARM7-NEXT: vld1.64 {d18, d19}, [r0:128]
404 ; ARM7-NEXT: adr r0, .LCPI3_1
405 ; ARM7-NEXT: vmov.32 d16[1], r1
406 ; ARM7-NEXT: vmov.32 d8[1], r4
407 ; ARM7-NEXT: vand q8, q8, q9
408 ; ARM7-NEXT: vld1.64 {d20, d21}, [r0:128]
409 ; ARM7-NEXT: adr r0, .LCPI3_2
410 ; ARM7-NEXT: vand q11, q4, q9
411 ; ARM7-NEXT: vld1.64 {d18, d19}, [r0:128]
412 ; ARM7-NEXT: vceq.i32 q10, q11, q10
413 ; ARM7-NEXT: vceq.i32 q8, q8, q9
414 ; ARM7-NEXT: vrev64.32 q9, q10
415 ; ARM7-NEXT: vrev64.32 q11, q8
416 ; ARM7-NEXT: vand q9, q10, q9
417 ; ARM7-NEXT: vand q8, q8, q11
418 ; ARM7-NEXT: vmvn q9, q9
419 ; ARM7-NEXT: vmvn q8, q8
420 ; ARM7-NEXT: vmovn.i64 d18, q9
421 ; ARM7-NEXT: vmovn.i64 d16, q8
422 ; ARM7-NEXT: vmov.32 r0, d18[0]
423 ; ARM7-NEXT: vmov.32 r1, d18[1]
424 ; ARM7-NEXT: vmov.32 r2, d16[0]
425 ; ARM7-NEXT: vpop {d8, d9}
426 ; ARM7-NEXT: pop {r4, r5, r6, r7, r11, pc}
427 ; ARM7-NEXT: .p2align 4
428 ; ARM7-NEXT: @ %bb.1:
429 ; ARM7-NEXT: .LCPI3_0:
430 ; ARM7-NEXT: .long 4294967295 @ 0xffffffff
431 ; ARM7-NEXT: .long 1 @ 0x1
432 ; ARM7-NEXT: .long 4294967295 @ 0xffffffff
433 ; ARM7-NEXT: .long 1 @ 0x1
434 ; ARM7-NEXT: .LCPI3_1:
435 ; ARM7-NEXT: .long 3 @ 0x3
436 ; ARM7-NEXT: .long 0 @ 0x0
437 ; ARM7-NEXT: .long 4294967293 @ 0xfffffffd
438 ; ARM7-NEXT: .long 1 @ 0x1
439 ; ARM7-NEXT: .LCPI3_2:
440 ; ARM7-NEXT: .long 3 @ 0x3
441 ; ARM7-NEXT: .long 0 @ 0x0
442 ; ARM7-NEXT: .zero 4
443 ; ARM7-NEXT: .long 0 @ 0x0
444 ;
445 ; ARM8-LABEL: test_srem_vec:
446 ; ARM8: @ %bb.0:
447 ; ARM8-NEXT: push {r4, r5, r6, r7, r11, lr}
448 ; ARM8-NEXT: vpush {d8, d9}
449 ; ARM8-NEXT: mov r5, r0
450 ; ARM8-NEXT: and r0, r3, #1
451 ; ARM8-NEXT: mov r4, r1
452 ; ARM8-NEXT: rsb r1, r0, #0
453 ; ARM8-NEXT: mov r0, r2
454 ; ARM8-NEXT: mov r2, #9
455 ; ARM8-NEXT: mov r3, #0
456 ; ARM8-NEXT: bl __moddi3
457 ; ARM8-NEXT: mov r6, r0
458 ; ARM8-NEXT: and r0, r4, #1
459 ; ARM8-NEXT: mov r7, r1
460 ; ARM8-NEXT: rsb r1, r0, #0
461 ; ARM8-NEXT: mov r0, r5
462 ; ARM8-NEXT: mov r2, #9
463 ; ARM8-NEXT: mov r3, #0
464 ; ARM8-NEXT: bl __moddi3
465 ; ARM8-NEXT: vmov.32 d8[0], r0
466 ; ARM8-NEXT: ldr r0, [sp, #44]
467 ; ARM8-NEXT: ldr r2, [sp, #40]
468 ; ARM8-NEXT: mov r4, r1
469 ; ARM8-NEXT: and r0, r0, #1
470 ; ARM8-NEXT: mvn r3, #0
471 ; ARM8-NEXT: rsb r1, r0, #0
472 ; ARM8-NEXT: vmov.32 d9[0], r6
473 ; ARM8-NEXT: mov r0, r2
474 ; ARM8-NEXT: mvn r2, #8
475 ; ARM8-NEXT: bl __moddi3
476 ; ARM8-NEXT: vmov.32 d16[0], r0
477 ; ARM8-NEXT: adr r0, .LCPI3_0
478 ; ARM8-NEXT: vmov.32 d9[1], r7
479 ; ARM8-NEXT: vld1.64 {d18, d19}, [r0:128]
480 ; ARM8-NEXT: adr r0, .LCPI3_1
481 ; ARM8-NEXT: vmov.32 d16[1], r1
482 ; ARM8-NEXT: vmov.32 d8[1], r4
483 ; ARM8-NEXT: vand q8, q8, q9
484 ; ARM8-NEXT: vld1.64 {d20, d21}, [r0:128]
485 ; ARM8-NEXT: adr r0, .LCPI3_2
486 ; ARM8-NEXT: vand q11, q4, q9
487 ; ARM8-NEXT: vld1.64 {d18, d19}, [r0:128]
488 ; ARM8-NEXT: vceq.i32 q10, q11, q10
489 ; ARM8-NEXT: vceq.i32 q8, q8, q9
490 ; ARM8-NEXT: vrev64.32 q9, q10
491 ; ARM8-NEXT: vrev64.32 q11, q8
492 ; ARM8-NEXT: vand q9, q10, q9
493 ; ARM8-NEXT: vand q8, q8, q11
494 ; ARM8-NEXT: vmvn q9, q9
495 ; ARM8-NEXT: vmvn q8, q8
496 ; ARM8-NEXT: vmovn.i64 d18, q9
497 ; ARM8-NEXT: vmovn.i64 d16, q8
498 ; ARM8-NEXT: vmov.32 r0, d18[0]
499 ; ARM8-NEXT: vmov.32 r1, d18[1]
500 ; ARM8-NEXT: vmov.32 r2, d16[0]
501 ; ARM8-NEXT: vpop {d8, d9}
502 ; ARM8-NEXT: pop {r4, r5, r6, r7, r11, pc}
503 ; ARM8-NEXT: .p2align 4
504 ; ARM8-NEXT: @ %bb.1:
505 ; ARM8-NEXT: .LCPI3_0:
506 ; ARM8-NEXT: .long 4294967295 @ 0xffffffff
507 ; ARM8-NEXT: .long 1 @ 0x1
508 ; ARM8-NEXT: .long 4294967295 @ 0xffffffff
509 ; ARM8-NEXT: .long 1 @ 0x1
510 ; ARM8-NEXT: .LCPI3_1:
511 ; ARM8-NEXT: .long 3 @ 0x3
512 ; ARM8-NEXT: .long 0 @ 0x0
513 ; ARM8-NEXT: .long 4294967293 @ 0xfffffffd
514 ; ARM8-NEXT: .long 1 @ 0x1
515 ; ARM8-NEXT: .LCPI3_2:
516 ; ARM8-NEXT: .long 3 @ 0x3
517 ; ARM8-NEXT: .long 0 @ 0x0
518 ; ARM8-NEXT: .zero 4
519 ; ARM8-NEXT: .long 0 @ 0x0
520 ;
521 ; NEON7-LABEL: test_srem_vec:
522 ; NEON7: @ %bb.0:
523 ; NEON7-NEXT: push {r4, r5, r6, r7, r11, lr}
524 ; NEON7-NEXT: vpush {d8, d9}
525 ; NEON7-NEXT: mov r5, r0
526 ; NEON7-NEXT: and r0, r3, #1
527 ; NEON7-NEXT: mov r4, r1
528 ; NEON7-NEXT: rsb r1, r0, #0
529 ; NEON7-NEXT: mov r0, r2
530 ; NEON7-NEXT: mov r2, #9
531 ; NEON7-NEXT: mov r3, #0
532 ; NEON7-NEXT: bl __moddi3
533 ; NEON7-NEXT: mov r6, r0
534 ; NEON7-NEXT: and r0, r4, #1
535 ; NEON7-NEXT: mov r7, r1
536 ; NEON7-NEXT: rsb r1, r0, #0
537 ; NEON7-NEXT: mov r0, r5
538 ; NEON7-NEXT: mov r2, #9
539 ; NEON7-NEXT: mov r3, #0
540 ; NEON7-NEXT: bl __moddi3
541 ; NEON7-NEXT: vmov.32 d8[0], r0
542 ; NEON7-NEXT: ldr r0, [sp, #44]
543 ; NEON7-NEXT: ldr r2, [sp, #40]
544 ; NEON7-NEXT: mov r4, r1
545 ; NEON7-NEXT: and r0, r0, #1
546 ; NEON7-NEXT: mvn r3, #0
547 ; NEON7-NEXT: rsb r1, r0, #0
548 ; NEON7-NEXT: vmov.32 d9[0], r6
549 ; NEON7-NEXT: mov r0, r2
550 ; NEON7-NEXT: mvn r2, #8
551 ; NEON7-NEXT: bl __moddi3
552 ; NEON7-NEXT: vmov.32 d16[0], r0
553 ; NEON7-NEXT: adr r0, .LCPI3_0
554 ; NEON7-NEXT: vmov.32 d9[1], r7
555 ; NEON7-NEXT: vld1.64 {d18, d19}, [r0:128]
556 ; NEON7-NEXT: adr r0, .LCPI3_1
557 ; NEON7-NEXT: vmov.32 d16[1], r1
558 ; NEON7-NEXT: vmov.32 d8[1], r4
559 ; NEON7-NEXT: vand q8, q8, q9
560 ; NEON7-NEXT: vld1.64 {d20, d21}, [r0:128]
561 ; NEON7-NEXT: adr r0, .LCPI3_2
562 ; NEON7-NEXT: vand q11, q4, q9
563 ; NEON7-NEXT: vld1.64 {d18, d19}, [r0:128]
564 ; NEON7-NEXT: vceq.i32 q10, q11, q10
565 ; NEON7-NEXT: vceq.i32 q8, q8, q9
566 ; NEON7-NEXT: vrev64.32 q9, q10
567 ; NEON7-NEXT: vrev64.32 q11, q8
568 ; NEON7-NEXT: vand q9, q10, q9
569 ; NEON7-NEXT: vand q8, q8, q11
570 ; NEON7-NEXT: vmvn q9, q9
571 ; NEON7-NEXT: vmvn q8, q8
572 ; NEON7-NEXT: vmovn.i64 d18, q9
573 ; NEON7-NEXT: vmovn.i64 d16, q8
574 ; NEON7-NEXT: vmov.32 r0, d18[0]
575 ; NEON7-NEXT: vmov.32 r1, d18[1]
576 ; NEON7-NEXT: vmov.32 r2, d16[0]
577 ; NEON7-NEXT: vpop {d8, d9}
578 ; NEON7-NEXT: pop {r4, r5, r6, r7, r11, pc}
579 ; NEON7-NEXT: .p2align 4
580 ; NEON7-NEXT: @ %bb.1:
581 ; NEON7-NEXT: .LCPI3_0:
582 ; NEON7-NEXT: .long 4294967295 @ 0xffffffff
583 ; NEON7-NEXT: .long 1 @ 0x1
584 ; NEON7-NEXT: .long 4294967295 @ 0xffffffff
585 ; NEON7-NEXT: .long 1 @ 0x1
586 ; NEON7-NEXT: .LCPI3_1:
587 ; NEON7-NEXT: .long 3 @ 0x3
588 ; NEON7-NEXT: .long 0 @ 0x0
589 ; NEON7-NEXT: .long 4294967293 @ 0xfffffffd
590 ; NEON7-NEXT: .long 1 @ 0x1
591 ; NEON7-NEXT: .LCPI3_2:
592 ; NEON7-NEXT: .long 3 @ 0x3
593 ; NEON7-NEXT: .long 0 @ 0x0
594 ; NEON7-NEXT: .zero 4
595 ; NEON7-NEXT: .long 0 @ 0x0
596 ;
597 ; NEON8-LABEL: test_srem_vec:
598 ; NEON8: @ %bb.0:
599 ; NEON8-NEXT: push {r4, r5, r6, r7, r11, lr}
600 ; NEON8-NEXT: vpush {d8, d9}
601 ; NEON8-NEXT: mov r5, r0
602 ; NEON8-NEXT: and r0, r3, #1
603 ; NEON8-NEXT: mov r4, r1
604 ; NEON8-NEXT: rsb r1, r0, #0
605 ; NEON8-NEXT: mov r0, r2
606 ; NEON8-NEXT: mov r2, #9
607 ; NEON8-NEXT: mov r3, #0
608 ; NEON8-NEXT: bl __moddi3
609 ; NEON8-NEXT: mov r6, r0
610 ; NEON8-NEXT: and r0, r4, #1
611 ; NEON8-NEXT: mov r7, r1
612 ; NEON8-NEXT: rsb r1, r0, #0
613 ; NEON8-NEXT: mov r0, r5
614 ; NEON8-NEXT: mov r2, #9
615 ; NEON8-NEXT: mov r3, #0
616 ; NEON8-NEXT: bl __moddi3
617 ; NEON8-NEXT: vmov.32 d8[0], r0
618 ; NEON8-NEXT: ldr r0, [sp, #44]
619 ; NEON8-NEXT: ldr r2, [sp, #40]
620 ; NEON8-NEXT: mov r4, r1
621 ; NEON8-NEXT: and r0, r0, #1
622 ; NEON8-NEXT: mvn r3, #0
623 ; NEON8-NEXT: rsb r1, r0, #0
624 ; NEON8-NEXT: vmov.32 d9[0], r6
625 ; NEON8-NEXT: mov r0, r2
626 ; NEON8-NEXT: mvn r2, #8
627 ; NEON8-NEXT: bl __moddi3
628 ; NEON8-NEXT: vmov.32 d16[0], r0
629 ; NEON8-NEXT: adr r0, .LCPI3_0
630 ; NEON8-NEXT: vmov.32 d9[1], r7
631 ; NEON8-NEXT: vld1.64 {d18, d19}, [r0:128]
632 ; NEON8-NEXT: adr r0, .LCPI3_1
633 ; NEON8-NEXT: vmov.32 d16[1], r1
634 ; NEON8-NEXT: vmov.32 d8[1], r4
635 ; NEON8-NEXT: vand q8, q8, q9
636 ; NEON8-NEXT: vld1.64 {d20, d21}, [r0:128]
637 ; NEON8-NEXT: adr r0, .LCPI3_2
638 ; NEON8-NEXT: vand q11, q4, q9
639 ; NEON8-NEXT: vld1.64 {d18, d19}, [r0:128]
640 ; NEON8-NEXT: vceq.i32 q10, q11, q10
641 ; NEON8-NEXT: vceq.i32 q8, q8, q9
642 ; NEON8-NEXT: vrev64.32 q9, q10
643 ; NEON8-NEXT: vrev64.32 q11, q8
644 ; NEON8-NEXT: vand q9, q10, q9
645 ; NEON8-NEXT: vand q8, q8, q11
646 ; NEON8-NEXT: vmvn q9, q9
647 ; NEON8-NEXT: vmvn q8, q8
648 ; NEON8-NEXT: vmovn.i64 d18, q9
649 ; NEON8-NEXT: vmovn.i64 d16, q8
650 ; NEON8-NEXT: vmov.32 r0, d18[0]
651 ; NEON8-NEXT: vmov.32 r1, d18[1]
652 ; NEON8-NEXT: vmov.32 r2, d16[0]
653 ; NEON8-NEXT: vpop {d8, d9}
654 ; NEON8-NEXT: pop {r4, r5, r6, r7, r11, pc}
655 ; NEON8-NEXT: .p2align 4
656 ; NEON8-NEXT: @ %bb.1:
657 ; NEON8-NEXT: .LCPI3_0:
658 ; NEON8-NEXT: .long 4294967295 @ 0xffffffff
659 ; NEON8-NEXT: .long 1 @ 0x1
660 ; NEON8-NEXT: .long 4294967295 @ 0xffffffff
661 ; NEON8-NEXT: .long 1 @ 0x1
662 ; NEON8-NEXT: .LCPI3_1:
663 ; NEON8-NEXT: .long 3 @ 0x3
664 ; NEON8-NEXT: .long 0 @ 0x0
665 ; NEON8-NEXT: .long 4294967293 @ 0xfffffffd
666 ; NEON8-NEXT: .long 1 @ 0x1
667 ; NEON8-NEXT: .LCPI3_2:
668 ; NEON8-NEXT: .long 3 @ 0x3
669 ; NEON8-NEXT: .long 0 @ 0x0
670 ; NEON8-NEXT: .zero 4
671 ; NEON8-NEXT: .long 0 @ 0x0
672 %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
673 %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
674 ret <3 x i1> %cmp
675 }