| blob | 30d7a683654a9becd296be1465dce7926fe1567d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
6 ; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
7 ; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
9 declare i4 @llvm.ssub.sat.i4(i4, i4)
10 declare i8 @llvm.ssub.sat.i8(i8, i8)
11 declare i16 @llvm.ssub.sat.i16(i16, i16)
12 declare i32 @llvm.ssub.sat.i32(i32, i32)
13 declare i64 @llvm.ssub.sat.i64(i64, i64)
14 declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
16 define i32 @func(i32 %x, i32 %y) nounwind {
17 ; CHECK-T1-LABEL: func:
18 ; CHECK-T1: @ %bb.0:
19 ; CHECK-T1-NEXT: subs r0, r0, r1
20 ; CHECK-T1-NEXT: bvc .LBB0_2
21 ; CHECK-T1-NEXT: @ %bb.1:
22 ; CHECK-T1-NEXT: asrs r1, r0, #31
23 ; CHECK-T1-NEXT: movs r0, #1
24 ; CHECK-T1-NEXT: lsls r0, r0, #31
25 ; CHECK-T1-NEXT: eors r0, r1
26 ; CHECK-T1-NEXT: .LBB0_2:
27 ; CHECK-T1-NEXT: bx lr
28 ;
29 ; CHECK-T2NODSP-LABEL: func:
30 ; CHECK-T2NODSP: @ %bb.0:
31 ; CHECK-T2NODSP-NEXT: subs r0, r0, r1
32 ; CHECK-T2NODSP-NEXT: mov.w r1, #-2147483648
33 ; CHECK-T2NODSP-NEXT: it vs
34 ; CHECK-T2NODSP-NEXT: eorvs.w r0, r1, r0, asr #31
35 ; CHECK-T2NODSP-NEXT: bx lr
36 ;
37 ; CHECK-T2DSP-LABEL: func:
38 ; CHECK-T2DSP: @ %bb.0:
39 ; CHECK-T2DSP-NEXT: qsub r0, r0, r1
40 ; CHECK-T2DSP-NEXT: bx lr
41 ;
42 ; CHECK-ARMNODPS-LABEL: func:
43 ; CHECK-ARMNODPS: @ %bb.0:
44 ; CHECK-ARMNODPS-NEXT: subs r0, r0, r1
45 ; CHECK-ARMNODPS-NEXT: mov r1, #-2147483648
46 ; CHECK-ARMNODPS-NEXT: eorvs r0, r1, r0, asr #31
47 ; CHECK-ARMNODPS-NEXT: bx lr
48 ;
49 ; CHECK-ARMBASEDSP-LABEL: func:
50 ; CHECK-ARMBASEDSP: @ %bb.0:
51 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
52 ; CHECK-ARMBASEDSP-NEXT: bx lr
53 ;
54 ; CHECK-ARMDSP-LABEL: func:
55 ; CHECK-ARMDSP: @ %bb.0:
56 ; CHECK-ARMDSP-NEXT: qsub r0, r0, r1
57 ; CHECK-ARMDSP-NEXT: bx lr
58 %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y)
59 ret i32 %tmp
60 }
62 define i64 @func2(i64 %x, i64 %y) nounwind {
63 ; CHECK-T1-LABEL: func2:
64 ; CHECK-T1: @ %bb.0:
65 ; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
66 ; CHECK-T1-NEXT: push {r4, r5, r7, lr}
67 ; CHECK-T1-NEXT: mov r4, r1
68 ; CHECK-T1-NEXT: eors r1, r3
69 ; CHECK-T1-NEXT: subs r5, r0, r2
70 ; CHECK-T1-NEXT: mov r2, r4
71 ; CHECK-T1-NEXT: sbcs r2, r3
72 ; CHECK-T1-NEXT: eors r4, r2
73 ; CHECK-T1-NEXT: ands r4, r1
74 ; CHECK-T1-NEXT: asrs r1, r2, #31
75 ; CHECK-T1-NEXT: cmp r4, #0
76 ; CHECK-T1-NEXT: mov r0, r1
77 ; CHECK-T1-NEXT: bmi .LBB1_2
78 ; CHECK-T1-NEXT: @ %bb.1:
79 ; CHECK-T1-NEXT: mov r0, r5
80 ; CHECK-T1-NEXT: .LBB1_2:
81 ; CHECK-T1-NEXT: cmp r4, #0
82 ; CHECK-T1-NEXT: bmi .LBB1_4
83 ; CHECK-T1-NEXT: @ %bb.3:
84 ; CHECK-T1-NEXT: mov r1, r2
85 ; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
86 ; CHECK-T1-NEXT: .LBB1_4:
87 ; CHECK-T1-NEXT: movs r2, #1
88 ; CHECK-T1-NEXT: lsls r2, r2, #31
89 ; CHECK-T1-NEXT: eors r1, r2
90 ; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
91 ;
92 ; CHECK-T2-LABEL: func2:
93 ; CHECK-T2: @ %bb.0:
94 ; CHECK-T2-NEXT: subs r0, r0, r2
95 ; CHECK-T2-NEXT: eor.w r12, r1, r3
96 ; CHECK-T2-NEXT: sbc.w r2, r1, r3
97 ; CHECK-T2-NEXT: eors r1, r2
98 ; CHECK-T2-NEXT: ands.w r1, r1, r12
99 ; CHECK-T2-NEXT: it mi
100 ; CHECK-T2-NEXT: asrmi r0, r2, #31
101 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
102 ; CHECK-T2-NEXT: it mi
103 ; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
104 ; CHECK-T2-NEXT: mov r1, r2
105 ; CHECK-T2-NEXT: bx lr
106 ;
107 ; CHECK-ARM-LABEL: func2:
108 ; CHECK-ARM: @ %bb.0:
109 ; CHECK-ARM-NEXT: subs r0, r0, r2
110 ; CHECK-ARM-NEXT: eor r12, r1, r3
111 ; CHECK-ARM-NEXT: sbc r2, r1, r3
112 ; CHECK-ARM-NEXT: eor r1, r1, r2
113 ; CHECK-ARM-NEXT: ands r1, r12, r1
114 ; CHECK-ARM-NEXT: asrmi r0, r2, #31
115 ; CHECK-ARM-NEXT: mov r1, #-2147483648
116 ; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
117 ; CHECK-ARM-NEXT: mov r1, r2
118 ; CHECK-ARM-NEXT: bx lr
119 %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)
120 ret i64 %tmp
121 }
123 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
124 ; CHECK-T1-LABEL: func16:
125 ; CHECK-T1: @ %bb.0:
126 ; CHECK-T1-NEXT: subs r0, r0, r1
127 ; CHECK-T1-NEXT: ldr r1, .LCPI2_0
128 ; CHECK-T1-NEXT: cmp r0, r1
129 ; CHECK-T1-NEXT: blt .LBB2_2
130 ; CHECK-T1-NEXT: @ %bb.1:
131 ; CHECK-T1-NEXT: mov r0, r1
132 ; CHECK-T1-NEXT: .LBB2_2:
133 ; CHECK-T1-NEXT: ldr r1, .LCPI2_1
134 ; CHECK-T1-NEXT: cmp r0, r1
135 ; CHECK-T1-NEXT: bgt .LBB2_4
136 ; CHECK-T1-NEXT: @ %bb.3:
137 ; CHECK-T1-NEXT: mov r0, r1
138 ; CHECK-T1-NEXT: .LBB2_4:
139 ; CHECK-T1-NEXT: bx lr
140 ; CHECK-T1-NEXT: .p2align 2
141 ; CHECK-T1-NEXT: @ %bb.5:
142 ; CHECK-T1-NEXT: .LCPI2_0:
143 ; CHECK-T1-NEXT: .long 32767 @ 0x7fff
144 ; CHECK-T1-NEXT: .LCPI2_1:
145 ; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
146 ;
147 ; CHECK-T2NODSP-LABEL: func16:
148 ; CHECK-T2NODSP: @ %bb.0:
149 ; CHECK-T2NODSP-NEXT: subs r0, r0, r1
150 ; CHECK-T2NODSP-NEXT: movw r1, #32767
151 ; CHECK-T2NODSP-NEXT: cmp r0, r1
152 ; CHECK-T2NODSP-NEXT: it lt
153 ; CHECK-T2NODSP-NEXT: movlt r1, r0
154 ; CHECK-T2NODSP-NEXT: movw r0, #32768
155 ; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
156 ; CHECK-T2NODSP-NEXT: movt r0, #65535
157 ; CHECK-T2NODSP-NEXT: it gt
158 ; CHECK-T2NODSP-NEXT: movgt r0, r1
159 ; CHECK-T2NODSP-NEXT: bx lr
160 ;
161 ; CHECK-T2DSP-LABEL: func16:
162 ; CHECK-T2DSP: @ %bb.0:
163 ; CHECK-T2DSP-NEXT: qsub16 r0, r0, r1
164 ; CHECK-T2DSP-NEXT: sxth r0, r0
165 ; CHECK-T2DSP-NEXT: bx lr
166 ;
167 ; CHECK-ARMNODPS-LABEL: func16:
168 ; CHECK-ARMNODPS: @ %bb.0:
169 ; CHECK-ARMNODPS-NEXT: sub r0, r0, r1
170 ; CHECK-ARMNODPS-NEXT: mov r1, #255
171 ; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
172 ; CHECK-ARMNODPS-NEXT: cmp r0, r1
173 ; CHECK-ARMNODPS-NEXT: movlt r1, r0
174 ; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
175 ; CHECK-ARMNODPS-NEXT: cmn r1, #32768
176 ; CHECK-ARMNODPS-NEXT: movgt r0, r1
177 ; CHECK-ARMNODPS-NEXT: bx lr
178 ; CHECK-ARMNODPS-NEXT: .p2align 2
179 ; CHECK-ARMNODPS-NEXT: @ %bb.1:
180 ; CHECK-ARMNODPS-NEXT: .LCPI2_0:
181 ; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000
182 ;
183 ; CHECK-ARMBASEDSP-LABEL: func16:
184 ; CHECK-ARMBASEDSP: @ %bb.0:
185 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #16
186 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #16
187 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
188 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #16
189 ; CHECK-ARMBASEDSP-NEXT: bx lr
190 ;
191 ; CHECK-ARMDSP-LABEL: func16:
192 ; CHECK-ARMDSP: @ %bb.0:
193 ; CHECK-ARMDSP-NEXT: qsub16 r0, r0, r1
194 ; CHECK-ARMDSP-NEXT: sxth r0, r0
195 ; CHECK-ARMDSP-NEXT: bx lr
196 %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
197 ret i16 %tmp
198 }
200 define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
201 ; CHECK-T1-LABEL: func8:
202 ; CHECK-T1: @ %bb.0:
203 ; CHECK-T1-NEXT: subs r0, r0, r1
204 ; CHECK-T1-NEXT: movs r1, #127
205 ; CHECK-T1-NEXT: cmp r0, #127
206 ; CHECK-T1-NEXT: blt .LBB3_2
207 ; CHECK-T1-NEXT: @ %bb.1:
208 ; CHECK-T1-NEXT: mov r0, r1
209 ; CHECK-T1-NEXT: .LBB3_2:
210 ; CHECK-T1-NEXT: mvns r1, r1
211 ; CHECK-T1-NEXT: cmp r0, r1
212 ; CHECK-T1-NEXT: bgt .LBB3_4
213 ; CHECK-T1-NEXT: @ %bb.3:
214 ; CHECK-T1-NEXT: mov r0, r1
215 ; CHECK-T1-NEXT: .LBB3_4:
216 ; CHECK-T1-NEXT: bx lr
217 ;
218 ; CHECK-T2NODSP-LABEL: func8:
219 ; CHECK-T2NODSP: @ %bb.0:
220 ; CHECK-T2NODSP-NEXT: subs r0, r0, r1
221 ; CHECK-T2NODSP-NEXT: cmp r0, #127
222 ; CHECK-T2NODSP-NEXT: it ge
223 ; CHECK-T2NODSP-NEXT: movge r0, #127
224 ; CHECK-T2NODSP-NEXT: cmn.w r0, #128
225 ; CHECK-T2NODSP-NEXT: it le
226 ; CHECK-T2NODSP-NEXT: mvnle r0, #127
227 ; CHECK-T2NODSP-NEXT: bx lr
228 ;
229 ; CHECK-T2DSP-LABEL: func8:
230 ; CHECK-T2DSP: @ %bb.0:
231 ; CHECK-T2DSP-NEXT: qsub8 r0, r0, r1
232 ; CHECK-T2DSP-NEXT: sxtb r0, r0
233 ; CHECK-T2DSP-NEXT: bx lr
234 ;
235 ; CHECK-ARMNODPS-LABEL: func8:
236 ; CHECK-ARMNODPS: @ %bb.0:
237 ; CHECK-ARMNODPS-NEXT: sub r0, r0, r1
238 ; CHECK-ARMNODPS-NEXT: cmp r0, #127
239 ; CHECK-ARMNODPS-NEXT: movge r0, #127
240 ; CHECK-ARMNODPS-NEXT: cmn r0, #128
241 ; CHECK-ARMNODPS-NEXT: mvnle r0, #127
242 ; CHECK-ARMNODPS-NEXT: bx lr
243 ;
244 ; CHECK-ARMBASEDSP-LABEL: func8:
245 ; CHECK-ARMBASEDSP: @ %bb.0:
246 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #24
247 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #24
248 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
249 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #24
250 ; CHECK-ARMBASEDSP-NEXT: bx lr
251 ;
252 ; CHECK-ARMDSP-LABEL: func8:
253 ; CHECK-ARMDSP: @ %bb.0:
254 ; CHECK-ARMDSP-NEXT: qsub8 r0, r0, r1
255 ; CHECK-ARMDSP-NEXT: sxtb r0, r0
256 ; CHECK-ARMDSP-NEXT: bx lr
257 %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y)
258 ret i8 %tmp
259 }
261 define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
262 ; CHECK-T1-LABEL: func3:
263 ; CHECK-T1: @ %bb.0:
264 ; CHECK-T1-NEXT: subs r0, r0, r1
265 ; CHECK-T1-NEXT: movs r1, #7
266 ; CHECK-T1-NEXT: cmp r0, #7
267 ; CHECK-T1-NEXT: blt .LBB4_2
268 ; CHECK-T1-NEXT: @ %bb.1:
269 ; CHECK-T1-NEXT: mov r0, r1
270 ; CHECK-T1-NEXT: .LBB4_2:
271 ; CHECK-T1-NEXT: mvns r1, r1
272 ; CHECK-T1-NEXT: cmp r0, r1
273 ; CHECK-T1-NEXT: bgt .LBB4_4
274 ; CHECK-T1-NEXT: @ %bb.3:
275 ; CHECK-T1-NEXT: mov r0, r1
276 ; CHECK-T1-NEXT: .LBB4_4:
277 ; CHECK-T1-NEXT: bx lr
278 ;
279 ; CHECK-T2NODSP-LABEL: func3:
280 ; CHECK-T2NODSP: @ %bb.0:
281 ; CHECK-T2NODSP-NEXT: subs r0, r0, r1
282 ; CHECK-T2NODSP-NEXT: cmp r0, #7
283 ; CHECK-T2NODSP-NEXT: it ge
284 ; CHECK-T2NODSP-NEXT: movge r0, #7
285 ; CHECK-T2NODSP-NEXT: cmn.w r0, #8
286 ; CHECK-T2NODSP-NEXT: it le
287 ; CHECK-T2NODSP-NEXT: mvnle r0, #7
288 ; CHECK-T2NODSP-NEXT: bx lr
289 ;
290 ; CHECK-T2DSP-LABEL: func3:
291 ; CHECK-T2DSP: @ %bb.0:
292 ; CHECK-T2DSP-NEXT: lsls r1, r1, #28
293 ; CHECK-T2DSP-NEXT: lsls r0, r0, #28
294 ; CHECK-T2DSP-NEXT: qsub r0, r0, r1
295 ; CHECK-T2DSP-NEXT: asrs r0, r0, #28
296 ; CHECK-T2DSP-NEXT: bx lr
297 ;
298 ; CHECK-ARMNODPS-LABEL: func3:
299 ; CHECK-ARMNODPS: @ %bb.0:
300 ; CHECK-ARMNODPS-NEXT: sub r0, r0, r1
301 ; CHECK-ARMNODPS-NEXT: cmp r0, #7
302 ; CHECK-ARMNODPS-NEXT: movge r0, #7
303 ; CHECK-ARMNODPS-NEXT: cmn r0, #8
304 ; CHECK-ARMNODPS-NEXT: mvnle r0, #7
305 ; CHECK-ARMNODPS-NEXT: bx lr
306 ;
307 ; CHECK-ARMBASEDSP-LABEL: func3:
308 ; CHECK-ARMBASEDSP: @ %bb.0:
309 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #28
310 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #28
311 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
312 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #28
313 ; CHECK-ARMBASEDSP-NEXT: bx lr
314 ;
315 ; CHECK-ARMDSP-LABEL: func3:
316 ; CHECK-ARMDSP: @ %bb.0:
317 ; CHECK-ARMDSP-NEXT: lsl r0, r0, #28
318 ; CHECK-ARMDSP-NEXT: lsl r1, r1, #28
319 ; CHECK-ARMDSP-NEXT: qsub r0, r0, r1
320 ; CHECK-ARMDSP-NEXT: asr r0, r0, #28
321 ; CHECK-ARMDSP-NEXT: bx lr
322 %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y)
323 ret i4 %tmp
324 }
326 define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
327 ; CHECK-T1-LABEL: vec:
328 ; CHECK-T1: @ %bb.0:
329 ; CHECK-T1-NEXT: .save {r4, r5, r6, lr}
330 ; CHECK-T1-NEXT: push {r4, r5, r6, lr}
331 ; CHECK-T1-NEXT: mov r4, r0
332 ; CHECK-T1-NEXT: ldr r6, [sp, #16]
333 ; CHECK-T1-NEXT: subs r0, r0, r6
334 ; CHECK-T1-NEXT: movs r5, #1
335 ; CHECK-T1-NEXT: lsls r5, r5, #31
336 ; CHECK-T1-NEXT: cmp r4, r6
337 ; CHECK-T1-NEXT: bvc .LBB5_2
338 ; CHECK-T1-NEXT: @ %bb.1:
339 ; CHECK-T1-NEXT: asrs r0, r0, #31
340 ; CHECK-T1-NEXT: eors r0, r5
341 ; CHECK-T1-NEXT: .LBB5_2:
342 ; CHECK-T1-NEXT: ldr r4, [sp, #20]
343 ; CHECK-T1-NEXT: subs r1, r1, r4
344 ; CHECK-T1-NEXT: bvc .LBB5_4
345 ; CHECK-T1-NEXT: @ %bb.3:
346 ; CHECK-T1-NEXT: asrs r1, r1, #31
347 ; CHECK-T1-NEXT: eors r1, r5
348 ; CHECK-T1-NEXT: .LBB5_4:
349 ; CHECK-T1-NEXT: ldr r4, [sp, #24]
350 ; CHECK-T1-NEXT: subs r2, r2, r4
351 ; CHECK-T1-NEXT: bvc .LBB5_6
352 ; CHECK-T1-NEXT: @ %bb.5:
353 ; CHECK-T1-NEXT: asrs r2, r2, #31
354 ; CHECK-T1-NEXT: eors r2, r5
355 ; CHECK-T1-NEXT: .LBB5_6:
356 ; CHECK-T1-NEXT: ldr r4, [sp, #28]
357 ; CHECK-T1-NEXT: subs r3, r3, r4
358 ; CHECK-T1-NEXT: bvc .LBB5_8
359 ; CHECK-T1-NEXT: @ %bb.7:
360 ; CHECK-T1-NEXT: asrs r3, r3, #31
361 ; CHECK-T1-NEXT: eors r3, r5
362 ; CHECK-T1-NEXT: .LBB5_8:
363 ; CHECK-T1-NEXT: pop {r4, r5, r6, pc}
364 ;
365 ; CHECK-T2NODSP-LABEL: vec:
366 ; CHECK-T2NODSP: @ %bb.0:
367 ; CHECK-T2NODSP-NEXT: .save {r7, lr}
368 ; CHECK-T2NODSP-NEXT: push {r7, lr}
369 ; CHECK-T2NODSP-NEXT: ldr.w r12, [sp, #8]
370 ; CHECK-T2NODSP-NEXT: ldr.w lr, [sp, #12]
371 ; CHECK-T2NODSP-NEXT: subs.w r0, r0, r12
372 ; CHECK-T2NODSP-NEXT: mov.w r12, #-2147483648
373 ; CHECK-T2NODSP-NEXT: it vs
374 ; CHECK-T2NODSP-NEXT: eorvs.w r0, r12, r0, asr #31
375 ; CHECK-T2NODSP-NEXT: subs.w r1, r1, lr
376 ; CHECK-T2NODSP-NEXT: ldr.w lr, [sp, #16]
377 ; CHECK-T2NODSP-NEXT: it vs
378 ; CHECK-T2NODSP-NEXT: eorvs.w r1, r12, r1, asr #31
379 ; CHECK-T2NODSP-NEXT: subs.w r2, r2, lr
380 ; CHECK-T2NODSP-NEXT: ldr.w lr, [sp, #20]
381 ; CHECK-T2NODSP-NEXT: it vs
382 ; CHECK-T2NODSP-NEXT: eorvs.w r2, r12, r2, asr #31
383 ; CHECK-T2NODSP-NEXT: subs.w r3, r3, lr
384 ; CHECK-T2NODSP-NEXT: it vs
385 ; CHECK-T2NODSP-NEXT: eorvs.w r3, r12, r3, asr #31
386 ; CHECK-T2NODSP-NEXT: pop {r7, pc}
387 ;
388 ; CHECK-T2DSP-LABEL: vec:
389 ; CHECK-T2DSP: @ %bb.0:
390 ; CHECK-T2DSP-NEXT: ldr.w r12, [sp]
391 ; CHECK-T2DSP-NEXT: qsub r0, r0, r12
392 ; CHECK-T2DSP-NEXT: ldr.w r12, [sp, #4]
393 ; CHECK-T2DSP-NEXT: qsub r1, r1, r12
394 ; CHECK-T2DSP-NEXT: ldr.w r12, [sp, #8]
395 ; CHECK-T2DSP-NEXT: qsub r2, r2, r12
396 ; CHECK-T2DSP-NEXT: ldr.w r12, [sp, #12]
397 ; CHECK-T2DSP-NEXT: qsub r3, r3, r12
398 ; CHECK-T2DSP-NEXT: bx lr
399 ;
400 ; CHECK-ARMNODPS-LABEL: vec:
401 ; CHECK-ARMNODPS: @ %bb.0:
402 ; CHECK-ARMNODPS-NEXT: .save {r11, lr}
403 ; CHECK-ARMNODPS-NEXT: push {r11, lr}
404 ; CHECK-ARMNODPS-NEXT: ldr r12, [sp, #8]
405 ; CHECK-ARMNODPS-NEXT: ldr lr, [sp, #12]
406 ; CHECK-ARMNODPS-NEXT: subs r0, r0, r12
407 ; CHECK-ARMNODPS-NEXT: mov r12, #-2147483648
408 ; CHECK-ARMNODPS-NEXT: eorvs r0, r12, r0, asr #31
409 ; CHECK-ARMNODPS-NEXT: subs r1, r1, lr
410 ; CHECK-ARMNODPS-NEXT: ldr lr, [sp, #16]
411 ; CHECK-ARMNODPS-NEXT: eorvs r1, r12, r1, asr #31
412 ; CHECK-ARMNODPS-NEXT: subs r2, r2, lr
413 ; CHECK-ARMNODPS-NEXT: ldr lr, [sp, #20]
414 ; CHECK-ARMNODPS-NEXT: eorvs r2, r12, r2, asr #31
415 ; CHECK-ARMNODPS-NEXT: subs r3, r3, lr
416 ; CHECK-ARMNODPS-NEXT: eorvs r3, r12, r3, asr #31
417 ; CHECK-ARMNODPS-NEXT: pop {r11, pc}
418 ;
419 ; CHECK-ARMBASEDSP-LABEL: vec:
420 ; CHECK-ARMBASEDSP: @ %bb.0:
421 ; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp]
422 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r12
423 ; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp, #4]
424 ; CHECK-ARMBASEDSP-NEXT: qsub r1, r1, r12
425 ; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp, #8]
426 ; CHECK-ARMBASEDSP-NEXT: qsub r2, r2, r12
427 ; CHECK-ARMBASEDSP-NEXT: ldr r12, [sp, #12]
428 ; CHECK-ARMBASEDSP-NEXT: qsub r3, r3, r12
429 ; CHECK-ARMBASEDSP-NEXT: bx lr
430 ;
431 ; CHECK-ARMDSP-LABEL: vec:
432 ; CHECK-ARMDSP: @ %bb.0:
433 ; CHECK-ARMDSP-NEXT: ldr r12, [sp]
434 ; CHECK-ARMDSP-NEXT: qsub r0, r0, r12
435 ; CHECK-ARMDSP-NEXT: ldr r12, [sp, #4]
436 ; CHECK-ARMDSP-NEXT: qsub r1, r1, r12
437 ; CHECK-ARMDSP-NEXT: ldr r12, [sp, #8]
438 ; CHECK-ARMDSP-NEXT: qsub r2, r2, r12
439 ; CHECK-ARMDSP-NEXT: ldr r12, [sp, #12]
440 ; CHECK-ARMDSP-NEXT: qsub r3, r3, r12
441 ; CHECK-ARMDSP-NEXT: bx lr
442 %tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
443 ret <4 x i32> %tmp
444 }