| blob | dd20fd07dff03a152e825b7fffb2630419a892a0 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv5-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM5
3 ; RUN: llc -mtriple=armv6-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM6
4 ; RUN: llc -mtriple=armv7-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM7
5 ; RUN: llc -mtriple=armv8-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM8
6 ; RUN: llc -mtriple=armv7-unknown-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=NEON7
7 ; RUN: llc -mtriple=armv8-unknown-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=NEON8
9 define i1 @test_urem_odd(i13 %X) nounwind {
10 ; ARM5-LABEL: test_urem_odd:
11 ; ARM5: @ %bb.0:
12 ; ARM5-NEXT: mov r1, #205
13 ; ARM5-NEXT: orr r1, r1, #3072
14 ; ARM5-NEXT: mul r2, r0, r1
15 ; ARM5-NEXT: mov r0, #255
16 ; ARM5-NEXT: orr r0, r0, #7936
17 ; ARM5-NEXT: and r1, r2, r0
18 ; ARM5-NEXT: mov r2, #103
19 ; ARM5-NEXT: orr r2, r2, #1536
20 ; ARM5-NEXT: mov r0, #0
21 ; ARM5-NEXT: cmp r1, r2
22 ; ARM5-NEXT: movlo r0, #1
23 ; ARM5-NEXT: bx lr
24 ;
25 ; ARM6-LABEL: test_urem_odd:
26 ; ARM6: @ %bb.0:
27 ; ARM6-NEXT: mov r1, #205
28 ; ARM6-NEXT: mov r2, #103
29 ; ARM6-NEXT: orr r1, r1, #3072
30 ; ARM6-NEXT: orr r2, r2, #1536
31 ; ARM6-NEXT: mul r0, r0, r1
32 ; ARM6-NEXT: mov r1, #255
33 ; ARM6-NEXT: orr r1, r1, #7936
34 ; ARM6-NEXT: and r1, r0, r1
35 ; ARM6-NEXT: mov r0, #0
36 ; ARM6-NEXT: cmp r1, r2
37 ; ARM6-NEXT: movlo r0, #1
38 ; ARM6-NEXT: bx lr
39 ;
40 ; ARM7-LABEL: test_urem_odd:
41 ; ARM7: @ %bb.0:
42 ; ARM7-NEXT: movw r1, #3277
43 ; ARM7-NEXT: movw r2, #1639
44 ; ARM7-NEXT: mul r1, r0, r1
45 ; ARM7-NEXT: mov r0, #0
46 ; ARM7-NEXT: bfc r1, #13, #19
47 ; ARM7-NEXT: cmp r1, r2
48 ; ARM7-NEXT: movwlo r0, #1
49 ; ARM7-NEXT: bx lr
50 ;
51 ; ARM8-LABEL: test_urem_odd:
52 ; ARM8: @ %bb.0:
53 ; ARM8-NEXT: movw r1, #3277
54 ; ARM8-NEXT: movw r2, #1639
55 ; ARM8-NEXT: mul r1, r0, r1
56 ; ARM8-NEXT: mov r0, #0
57 ; ARM8-NEXT: bfc r1, #13, #19
58 ; ARM8-NEXT: cmp r1, r2
59 ; ARM8-NEXT: movwlo r0, #1
60 ; ARM8-NEXT: bx lr
61 ;
62 ; NEON7-LABEL: test_urem_odd:
63 ; NEON7: @ %bb.0:
64 ; NEON7-NEXT: movw r1, #3277
65 ; NEON7-NEXT: movw r2, #1639
66 ; NEON7-NEXT: mul r1, r0, r1
67 ; NEON7-NEXT: mov r0, #0
68 ; NEON7-NEXT: bfc r1, #13, #19
69 ; NEON7-NEXT: cmp r1, r2
70 ; NEON7-NEXT: movwlo r0, #1
71 ; NEON7-NEXT: bx lr
72 ;
73 ; NEON8-LABEL: test_urem_odd:
74 ; NEON8: @ %bb.0:
75 ; NEON8-NEXT: movw r1, #3277
76 ; NEON8-NEXT: movw r2, #1639
77 ; NEON8-NEXT: mul r1, r0, r1
78 ; NEON8-NEXT: mov r0, #0
79 ; NEON8-NEXT: bfc r1, #13, #19
80 ; NEON8-NEXT: cmp r1, r2
81 ; NEON8-NEXT: movwlo r0, #1
82 ; NEON8-NEXT: bx lr
83 %urem = urem i13 %X, 5
84 %cmp = icmp eq i13 %urem, 0
85 ret i1 %cmp
86 }
88 define i1 @test_urem_even(i27 %X) nounwind {
89 ; ARM5-LABEL: test_urem_even:
90 ; ARM5: @ %bb.0:
91 ; ARM5-NEXT: ldr r1, .LCPI1_0
92 ; ARM5-NEXT: mul r2, r0, r1
93 ; ARM5-NEXT: bic r0, r2, #-134217727
94 ; ARM5-NEXT: lsr r0, r0, #1
95 ; ARM5-NEXT: orr r0, r0, r2, lsl #26
96 ; ARM5-NEXT: ldr r2, .LCPI1_1
97 ; ARM5-NEXT: bic r1, r0, #-134217728
98 ; ARM5-NEXT: mov r0, #0
99 ; ARM5-NEXT: cmp r1, r2
100 ; ARM5-NEXT: movlo r0, #1
101 ; ARM5-NEXT: bx lr
102 ; ARM5-NEXT: .p2align 2
103 ; ARM5-NEXT: @ %bb.1:
104 ; ARM5-NEXT: .LCPI1_0:
105 ; ARM5-NEXT: .long 115043767 @ 0x6db6db7
106 ; ARM5-NEXT: .LCPI1_1:
107 ; ARM5-NEXT: .long 9586981 @ 0x924925
108 ;
109 ; ARM6-LABEL: test_urem_even:
110 ; ARM6: @ %bb.0:
111 ; ARM6-NEXT: ldr r1, .LCPI1_0
112 ; ARM6-NEXT: ldr r2, .LCPI1_1
113 ; ARM6-NEXT: mul r0, r0, r1
114 ; ARM6-NEXT: bic r1, r0, #-134217727
115 ; ARM6-NEXT: lsr r1, r1, #1
116 ; ARM6-NEXT: orr r0, r1, r0, lsl #26
117 ; ARM6-NEXT: bic r1, r0, #-134217728
118 ; ARM6-NEXT: mov r0, #0
119 ; ARM6-NEXT: cmp r1, r2
120 ; ARM6-NEXT: movlo r0, #1
121 ; ARM6-NEXT: bx lr
122 ; ARM6-NEXT: .p2align 2
123 ; ARM6-NEXT: @ %bb.1:
124 ; ARM6-NEXT: .LCPI1_0:
125 ; ARM6-NEXT: .long 115043767 @ 0x6db6db7
126 ; ARM6-NEXT: .LCPI1_1:
127 ; ARM6-NEXT: .long 9586981 @ 0x924925
128 ;
129 ; ARM7-LABEL: test_urem_even:
130 ; ARM7: @ %bb.0:
131 ; ARM7-NEXT: movw r1, #28087
132 ; ARM7-NEXT: movw r2, #18725
133 ; ARM7-NEXT: movt r1, #1755
134 ; ARM7-NEXT: movt r2, #146
135 ; ARM7-NEXT: mul r0, r0, r1
136 ; ARM7-NEXT: ubfx r1, r0, #1, #26
137 ; ARM7-NEXT: orr r0, r1, r0, lsl #26
138 ; ARM7-NEXT: bic r1, r0, #-134217728
139 ; ARM7-NEXT: mov r0, #0
140 ; ARM7-NEXT: cmp r1, r2
141 ; ARM7-NEXT: movwlo r0, #1
142 ; ARM7-NEXT: bx lr
143 ;
144 ; ARM8-LABEL: test_urem_even:
145 ; ARM8: @ %bb.0:
146 ; ARM8-NEXT: movw r1, #28087
147 ; ARM8-NEXT: movw r2, #18725
148 ; ARM8-NEXT: movt r1, #1755
149 ; ARM8-NEXT: movt r2, #146
150 ; ARM8-NEXT: mul r0, r0, r1
151 ; ARM8-NEXT: ubfx r1, r0, #1, #26
152 ; ARM8-NEXT: orr r0, r1, r0, lsl #26
153 ; ARM8-NEXT: bic r1, r0, #-134217728
154 ; ARM8-NEXT: mov r0, #0
155 ; ARM8-NEXT: cmp r1, r2
156 ; ARM8-NEXT: movwlo r0, #1
157 ; ARM8-NEXT: bx lr
158 ;
159 ; NEON7-LABEL: test_urem_even:
160 ; NEON7: @ %bb.0:
161 ; NEON7-NEXT: movw r1, #28087
162 ; NEON7-NEXT: movw r2, #18725
163 ; NEON7-NEXT: movt r1, #1755
164 ; NEON7-NEXT: movt r2, #146
165 ; NEON7-NEXT: mul r0, r0, r1
166 ; NEON7-NEXT: ubfx r1, r0, #1, #26
167 ; NEON7-NEXT: orr r0, r1, r0, lsl #26
168 ; NEON7-NEXT: bic r1, r0, #-134217728
169 ; NEON7-NEXT: mov r0, #0
170 ; NEON7-NEXT: cmp r1, r2
171 ; NEON7-NEXT: movwlo r0, #1
172 ; NEON7-NEXT: bx lr
173 ;
174 ; NEON8-LABEL: test_urem_even:
175 ; NEON8: @ %bb.0:
176 ; NEON8-NEXT: movw r1, #28087
177 ; NEON8-NEXT: movw r2, #18725
178 ; NEON8-NEXT: movt r1, #1755
179 ; NEON8-NEXT: movt r2, #146
180 ; NEON8-NEXT: mul r0, r0, r1
181 ; NEON8-NEXT: ubfx r1, r0, #1, #26
182 ; NEON8-NEXT: orr r0, r1, r0, lsl #26
183 ; NEON8-NEXT: bic r1, r0, #-134217728
184 ; NEON8-NEXT: mov r0, #0
185 ; NEON8-NEXT: cmp r1, r2
186 ; NEON8-NEXT: movwlo r0, #1
187 ; NEON8-NEXT: bx lr
188 %urem = urem i27 %X, 14
189 %cmp = icmp eq i27 %urem, 0
190 ret i1 %cmp
191 }
193 define i1 @test_urem_odd_setne(i4 %X) nounwind {
194 ; ARM5-LABEL: test_urem_odd_setne:
195 ; ARM5: @ %bb.0:
196 ; ARM5-NEXT: mov r1, #13
197 ; ARM5-NEXT: mul r2, r0, r1
198 ; ARM5-NEXT: mov r0, #0
199 ; ARM5-NEXT: and r1, r2, #15
200 ; ARM5-NEXT: cmp r1, #3
201 ; ARM5-NEXT: movhi r0, #1
202 ; ARM5-NEXT: bx lr
203 ;
204 ; ARM6-LABEL: test_urem_odd_setne:
205 ; ARM6: @ %bb.0:
206 ; ARM6-NEXT: mov r1, #13
207 ; ARM6-NEXT: mul r0, r0, r1
208 ; ARM6-NEXT: and r1, r0, #15
209 ; ARM6-NEXT: mov r0, #0
210 ; ARM6-NEXT: cmp r1, #3
211 ; ARM6-NEXT: movhi r0, #1
212 ; ARM6-NEXT: bx lr
213 ;
214 ; ARM7-LABEL: test_urem_odd_setne:
215 ; ARM7: @ %bb.0:
216 ; ARM7-NEXT: mov r1, #13
217 ; ARM7-NEXT: mul r0, r0, r1
218 ; ARM7-NEXT: and r1, r0, #15
219 ; ARM7-NEXT: mov r0, #0
220 ; ARM7-NEXT: cmp r1, #3
221 ; ARM7-NEXT: movwhi r0, #1
222 ; ARM7-NEXT: bx lr
223 ;
224 ; ARM8-LABEL: test_urem_odd_setne:
225 ; ARM8: @ %bb.0:
226 ; ARM8-NEXT: mov r1, #13
227 ; ARM8-NEXT: mul r0, r0, r1
228 ; ARM8-NEXT: and r1, r0, #15
229 ; ARM8-NEXT: mov r0, #0
230 ; ARM8-NEXT: cmp r1, #3
231 ; ARM8-NEXT: movwhi r0, #1
232 ; ARM8-NEXT: bx lr
233 ;
234 ; NEON7-LABEL: test_urem_odd_setne:
235 ; NEON7: @ %bb.0:
236 ; NEON7-NEXT: mov r1, #13
237 ; NEON7-NEXT: mul r0, r0, r1
238 ; NEON7-NEXT: and r1, r0, #15
239 ; NEON7-NEXT: mov r0, #0
240 ; NEON7-NEXT: cmp r1, #3
241 ; NEON7-NEXT: movwhi r0, #1
242 ; NEON7-NEXT: bx lr
243 ;
244 ; NEON8-LABEL: test_urem_odd_setne:
245 ; NEON8: @ %bb.0:
246 ; NEON8-NEXT: mov r1, #13
247 ; NEON8-NEXT: mul r0, r0, r1
248 ; NEON8-NEXT: and r1, r0, #15
249 ; NEON8-NEXT: mov r0, #0
250 ; NEON8-NEXT: cmp r1, #3
251 ; NEON8-NEXT: movwhi r0, #1
252 ; NEON8-NEXT: bx lr
253 %urem = urem i4 %X, 5
254 %cmp = icmp ne i4 %urem, 0
255 ret i1 %cmp
256 }
258 define i1 @test_urem_negative_odd(i9 %X) nounwind {
259 ; ARM5-LABEL: test_urem_negative_odd:
260 ; ARM5: @ %bb.0:
261 ; ARM5-NEXT: mov r1, #51
262 ; ARM5-NEXT: orr r1, r1, #256
263 ; ARM5-NEXT: mul r2, r0, r1
264 ; ARM5-NEXT: mov r0, #255
265 ; ARM5-NEXT: orr r0, r0, #256
266 ; ARM5-NEXT: and r1, r2, r0
267 ; ARM5-NEXT: mov r0, #0
268 ; ARM5-NEXT: cmp r1, #1
269 ; ARM5-NEXT: movhi r0, #1
270 ; ARM5-NEXT: bx lr
271 ;
272 ; ARM6-LABEL: test_urem_negative_odd:
273 ; ARM6: @ %bb.0:
274 ; ARM6-NEXT: mov r1, #51
275 ; ARM6-NEXT: orr r1, r1, #256
276 ; ARM6-NEXT: mul r0, r0, r1
277 ; ARM6-NEXT: mov r1, #255
278 ; ARM6-NEXT: orr r1, r1, #256
279 ; ARM6-NEXT: and r1, r0, r1
280 ; ARM6-NEXT: mov r0, #0
281 ; ARM6-NEXT: cmp r1, #1
282 ; ARM6-NEXT: movhi r0, #1
283 ; ARM6-NEXT: bx lr
284 ;
285 ; ARM7-LABEL: test_urem_negative_odd:
286 ; ARM7: @ %bb.0:
287 ; ARM7-NEXT: movw r1, #307
288 ; ARM7-NEXT: mul r1, r0, r1
289 ; ARM7-NEXT: mov r0, #0
290 ; ARM7-NEXT: bfc r1, #9, #23
291 ; ARM7-NEXT: cmp r1, #1
292 ; ARM7-NEXT: movwhi r0, #1
293 ; ARM7-NEXT: bx lr
294 ;
295 ; ARM8-LABEL: test_urem_negative_odd:
296 ; ARM8: @ %bb.0:
297 ; ARM8-NEXT: movw r1, #307
298 ; ARM8-NEXT: mul r1, r0, r1
299 ; ARM8-NEXT: mov r0, #0
300 ; ARM8-NEXT: bfc r1, #9, #23
301 ; ARM8-NEXT: cmp r1, #1
302 ; ARM8-NEXT: movwhi r0, #1
303 ; ARM8-NEXT: bx lr
304 ;
305 ; NEON7-LABEL: test_urem_negative_odd:
306 ; NEON7: @ %bb.0:
307 ; NEON7-NEXT: movw r1, #307
308 ; NEON7-NEXT: mul r1, r0, r1
309 ; NEON7-NEXT: mov r0, #0
310 ; NEON7-NEXT: bfc r1, #9, #23
311 ; NEON7-NEXT: cmp r1, #1
312 ; NEON7-NEXT: movwhi r0, #1
313 ; NEON7-NEXT: bx lr
314 ;
315 ; NEON8-LABEL: test_urem_negative_odd:
316 ; NEON8: @ %bb.0:
317 ; NEON8-NEXT: movw r1, #307
318 ; NEON8-NEXT: mul r1, r0, r1
319 ; NEON8-NEXT: mov r0, #0
320 ; NEON8-NEXT: bfc r1, #9, #23
321 ; NEON8-NEXT: cmp r1, #1
322 ; NEON8-NEXT: movwhi r0, #1
323 ; NEON8-NEXT: bx lr
324 %urem = urem i9 %X, -5
325 %cmp = icmp ne i9 %urem, 0
326 ret i1 %cmp
327 }
329 define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
330 ; ARM5-LABEL: test_urem_vec:
331 ; ARM5: @ %bb.0:
332 ; ARM5-NEXT: push {r4, r5, r11, lr}
333 ; ARM5-NEXT: mov r3, #183
334 ; ARM5-NEXT: mvn r12, #182
335 ; ARM5-NEXT: orr r3, r3, #1280
336 ; ARM5-NEXT: sub r12, r12, #1280
337 ; ARM5-NEXT: mov r4, #51
338 ; ARM5-NEXT: mla lr, r1, r3, r12
339 ; ARM5-NEXT: mov r12, #255
340 ; ARM5-NEXT: orr r12, r12, #1792
341 ; ARM5-NEXT: orr r4, r4, #768
342 ; ARM5-NEXT: mov r3, #0
343 ; ARM5-NEXT: and r1, lr, r12
344 ; ARM5-NEXT: mvn lr, #101
345 ; ARM5-NEXT: sub lr, lr, #1536
346 ; ARM5-NEXT: cmp r1, #292
347 ; ARM5-NEXT: mla r5, r2, r4, lr
348 ; ARM5-NEXT: mov r1, #0
349 ; ARM5-NEXT: movhi r1, #1
350 ; ARM5-NEXT: and r2, r5, r12
351 ; ARM5-NEXT: mov r5, #171
352 ; ARM5-NEXT: orr r5, r5, #512
353 ; ARM5-NEXT: cmp r2, #1
354 ; ARM5-NEXT: mov r2, #0
355 ; ARM5-NEXT: mul r4, r0, r5
356 ; ARM5-NEXT: mov r0, #1020
357 ; ARM5-NEXT: orr r0, r0, #1024
358 ; ARM5-NEXT: mov r5, #254
359 ; ARM5-NEXT: movhi r2, #1
360 ; ARM5-NEXT: orr r5, r5, #1792
361 ; ARM5-NEXT: and r0, r4, r0
362 ; ARM5-NEXT: lsr r0, r0, #1
363 ; ARM5-NEXT: orr r0, r0, r4, lsl #10
364 ; ARM5-NEXT: and r0, r0, r5
365 ; ARM5-NEXT: lsr r0, r0, #1
366 ; ARM5-NEXT: cmp r0, #170
367 ; ARM5-NEXT: movhi r3, #1
368 ; ARM5-NEXT: mov r0, r3
369 ; ARM5-NEXT: pop {r4, r5, r11, pc}
370 ;
371 ; ARM6-LABEL: test_urem_vec:
372 ; ARM6: @ %bb.0:
373 ; ARM6-NEXT: push {r4, lr}
374 ; ARM6-NEXT: mov r4, #51
375 ; ARM6-NEXT: mvn lr, #101
376 ; ARM6-NEXT: orr r4, r4, #768
377 ; ARM6-NEXT: sub lr, lr, #1536
378 ; ARM6-NEXT: mov r3, #183
379 ; ARM6-NEXT: mvn r12, #182
380 ; ARM6-NEXT: mla r2, r2, r4, lr
381 ; ARM6-NEXT: mov r4, #171
382 ; ARM6-NEXT: orr r4, r4, #512
383 ; ARM6-NEXT: orr r3, r3, #1280
384 ; ARM6-NEXT: sub r12, r12, #1280
385 ; ARM6-NEXT: mul r0, r0, r4
386 ; ARM6-NEXT: mov r4, #1020
387 ; ARM6-NEXT: orr r4, r4, #1024
388 ; ARM6-NEXT: mla r1, r1, r3, r12
389 ; ARM6-NEXT: mov r12, #255
390 ; ARM6-NEXT: orr r12, r12, #1792
391 ; ARM6-NEXT: and r2, r2, r12
392 ; ARM6-NEXT: mov r3, #0
393 ; ARM6-NEXT: and r4, r0, r4
394 ; ARM6-NEXT: lsr r4, r4, #1
395 ; ARM6-NEXT: orr r0, r4, r0, lsl #10
396 ; ARM6-NEXT: mov r4, #254
397 ; ARM6-NEXT: and r1, r1, r12
398 ; ARM6-NEXT: orr r4, r4, #1792
399 ; ARM6-NEXT: cmp r1, #292
400 ; ARM6-NEXT: mov r1, #0
401 ; ARM6-NEXT: and r0, r0, r4
402 ; ARM6-NEXT: movhi r1, #1
403 ; ARM6-NEXT: cmp r2, #1
404 ; ARM6-NEXT: mov r2, #0
405 ; ARM6-NEXT: lsr r0, r0, #1
406 ; ARM6-NEXT: movhi r2, #1
407 ; ARM6-NEXT: cmp r0, #170
408 ; ARM6-NEXT: movhi r3, #1
409 ; ARM6-NEXT: mov r0, r3
410 ; ARM6-NEXT: pop {r4, pc}
411 ;
412 ; ARM7-LABEL: test_urem_vec:
413 ; ARM7: @ %bb.0:
414 ; ARM7-NEXT: vmov.16 d16[0], r0
415 ; ARM7-NEXT: vldr d17, .LCPI4_0
416 ; ARM7-NEXT: vmov.16 d16[1], r1
417 ; ARM7-NEXT: vldr d19, .LCPI4_3
418 ; ARM7-NEXT: vmov.16 d16[2], r2
419 ; ARM7-NEXT: vsub.i16 d16, d16, d17
420 ; ARM7-NEXT: vldr d17, .LCPI4_1
421 ; ARM7-NEXT: vmul.i16 d16, d16, d17
422 ; ARM7-NEXT: vldr d17, .LCPI4_2
423 ; ARM7-NEXT: vneg.s16 d17, d17
424 ; ARM7-NEXT: vshl.i16 d18, d16, #1
425 ; ARM7-NEXT: vbic.i16 d16, #0xf800
426 ; ARM7-NEXT: vshl.u16 d16, d16, d17
427 ; ARM7-NEXT: vshl.u16 d17, d18, d19
428 ; ARM7-NEXT: vorr d16, d16, d17
429 ; ARM7-NEXT: vldr d17, .LCPI4_4
430 ; ARM7-NEXT: vbic.i16 d16, #0xf800
431 ; ARM7-NEXT: vcgt.u16 d16, d16, d17
432 ; ARM7-NEXT: vmov.u16 r0, d16[0]
433 ; ARM7-NEXT: vmov.u16 r1, d16[1]
434 ; ARM7-NEXT: vmov.u16 r2, d16[2]
435 ; ARM7-NEXT: bx lr
436 ; ARM7-NEXT: .p2align 3
437 ; ARM7-NEXT: @ %bb.1:
438 ; ARM7-NEXT: .LCPI4_0:
439 ; ARM7-NEXT: .short 0 @ 0x0
440 ; ARM7-NEXT: .short 1 @ 0x1
441 ; ARM7-NEXT: .short 2 @ 0x2
442 ; ARM7-NEXT: .zero 2
443 ; ARM7-NEXT: .LCPI4_1:
444 ; ARM7-NEXT: .short 683 @ 0x2ab
445 ; ARM7-NEXT: .short 1463 @ 0x5b7
446 ; ARM7-NEXT: .short 819 @ 0x333
447 ; ARM7-NEXT: .zero 2
448 ; ARM7-NEXT: .LCPI4_2:
449 ; ARM7-NEXT: .short 1 @ 0x1
450 ; ARM7-NEXT: .short 0 @ 0x0
451 ; ARM7-NEXT: .short 0 @ 0x0
452 ; ARM7-NEXT: .short 0 @ 0x0
453 ; ARM7-NEXT: .LCPI4_3:
454 ; ARM7-NEXT: .short 9 @ 0x9
455 ; ARM7-NEXT: .short 10 @ 0xa
456 ; ARM7-NEXT: .short 10 @ 0xa
457 ; ARM7-NEXT: .short 10 @ 0xa
458 ; ARM7-NEXT: .LCPI4_4:
459 ; ARM7-NEXT: .short 341 @ 0x155
460 ; ARM7-NEXT: .short 292 @ 0x124
461 ; ARM7-NEXT: .short 1 @ 0x1
462 ; ARM7-NEXT: .short 0 @ 0x0
463 ;
464 ; ARM8-LABEL: test_urem_vec:
465 ; ARM8: @ %bb.0:
466 ; ARM8-NEXT: vmov.16 d16[0], r0
467 ; ARM8-NEXT: vldr d17, .LCPI4_0
468 ; ARM8-NEXT: vmov.16 d16[1], r1
469 ; ARM8-NEXT: vldr d19, .LCPI4_3
470 ; ARM8-NEXT: vmov.16 d16[2], r2
471 ; ARM8-NEXT: vsub.i16 d16, d16, d17
472 ; ARM8-NEXT: vldr d17, .LCPI4_1
473 ; ARM8-NEXT: vmul.i16 d16, d16, d17
474 ; ARM8-NEXT: vldr d17, .LCPI4_2
475 ; ARM8-NEXT: vneg.s16 d17, d17
476 ; ARM8-NEXT: vshl.i16 d18, d16, #1
477 ; ARM8-NEXT: vbic.i16 d16, #0xf800
478 ; ARM8-NEXT: vshl.u16 d16, d16, d17
479 ; ARM8-NEXT: vshl.u16 d17, d18, d19
480 ; ARM8-NEXT: vorr d16, d16, d17
481 ; ARM8-NEXT: vldr d17, .LCPI4_4
482 ; ARM8-NEXT: vbic.i16 d16, #0xf800
483 ; ARM8-NEXT: vcgt.u16 d16, d16, d17
484 ; ARM8-NEXT: vmov.u16 r0, d16[0]
485 ; ARM8-NEXT: vmov.u16 r1, d16[1]
486 ; ARM8-NEXT: vmov.u16 r2, d16[2]
487 ; ARM8-NEXT: bx lr
488 ; ARM8-NEXT: .p2align 3
489 ; ARM8-NEXT: @ %bb.1:
490 ; ARM8-NEXT: .LCPI4_0:
491 ; ARM8-NEXT: .short 0 @ 0x0
492 ; ARM8-NEXT: .short 1 @ 0x1
493 ; ARM8-NEXT: .short 2 @ 0x2
494 ; ARM8-NEXT: .zero 2
495 ; ARM8-NEXT: .LCPI4_1:
496 ; ARM8-NEXT: .short 683 @ 0x2ab
497 ; ARM8-NEXT: .short 1463 @ 0x5b7
498 ; ARM8-NEXT: .short 819 @ 0x333
499 ; ARM8-NEXT: .zero 2
500 ; ARM8-NEXT: .LCPI4_2:
501 ; ARM8-NEXT: .short 1 @ 0x1
502 ; ARM8-NEXT: .short 0 @ 0x0
503 ; ARM8-NEXT: .short 0 @ 0x0
504 ; ARM8-NEXT: .short 0 @ 0x0
505 ; ARM8-NEXT: .LCPI4_3:
506 ; ARM8-NEXT: .short 9 @ 0x9
507 ; ARM8-NEXT: .short 10 @ 0xa
508 ; ARM8-NEXT: .short 10 @ 0xa
509 ; ARM8-NEXT: .short 10 @ 0xa
510 ; ARM8-NEXT: .LCPI4_4:
511 ; ARM8-NEXT: .short 341 @ 0x155
512 ; ARM8-NEXT: .short 292 @ 0x124
513 ; ARM8-NEXT: .short 1 @ 0x1
514 ; ARM8-NEXT: .short 0 @ 0x0
515 ;
516 ; NEON7-LABEL: test_urem_vec:
517 ; NEON7: @ %bb.0:
518 ; NEON7-NEXT: vmov.16 d16[0], r0
519 ; NEON7-NEXT: vldr d17, .LCPI4_0
520 ; NEON7-NEXT: vmov.16 d16[1], r1
521 ; NEON7-NEXT: vldr d19, .LCPI4_3
522 ; NEON7-NEXT: vmov.16 d16[2], r2
523 ; NEON7-NEXT: vsub.i16 d16, d16, d17
524 ; NEON7-NEXT: vldr d17, .LCPI4_1
525 ; NEON7-NEXT: vmul.i16 d16, d16, d17
526 ; NEON7-NEXT: vldr d17, .LCPI4_2
527 ; NEON7-NEXT: vneg.s16 d17, d17
528 ; NEON7-NEXT: vshl.i16 d18, d16, #1
529 ; NEON7-NEXT: vbic.i16 d16, #0xf800
530 ; NEON7-NEXT: vshl.u16 d16, d16, d17
531 ; NEON7-NEXT: vshl.u16 d17, d18, d19
532 ; NEON7-NEXT: vorr d16, d16, d17
533 ; NEON7-NEXT: vldr d17, .LCPI4_4
534 ; NEON7-NEXT: vbic.i16 d16, #0xf800
535 ; NEON7-NEXT: vcgt.u16 d16, d16, d17
536 ; NEON7-NEXT: vmov.u16 r0, d16[0]
537 ; NEON7-NEXT: vmov.u16 r1, d16[1]
538 ; NEON7-NEXT: vmov.u16 r2, d16[2]
539 ; NEON7-NEXT: bx lr
540 ; NEON7-NEXT: .p2align 3
541 ; NEON7-NEXT: @ %bb.1:
542 ; NEON7-NEXT: .LCPI4_0:
543 ; NEON7-NEXT: .short 0 @ 0x0
544 ; NEON7-NEXT: .short 1 @ 0x1
545 ; NEON7-NEXT: .short 2 @ 0x2
546 ; NEON7-NEXT: .zero 2
547 ; NEON7-NEXT: .LCPI4_1:
548 ; NEON7-NEXT: .short 683 @ 0x2ab
549 ; NEON7-NEXT: .short 1463 @ 0x5b7
550 ; NEON7-NEXT: .short 819 @ 0x333
551 ; NEON7-NEXT: .zero 2
552 ; NEON7-NEXT: .LCPI4_2:
553 ; NEON7-NEXT: .short 1 @ 0x1
554 ; NEON7-NEXT: .short 0 @ 0x0
555 ; NEON7-NEXT: .short 0 @ 0x0
556 ; NEON7-NEXT: .short 0 @ 0x0
557 ; NEON7-NEXT: .LCPI4_3:
558 ; NEON7-NEXT: .short 9 @ 0x9
559 ; NEON7-NEXT: .short 10 @ 0xa
560 ; NEON7-NEXT: .short 10 @ 0xa
561 ; NEON7-NEXT: .short 10 @ 0xa
562 ; NEON7-NEXT: .LCPI4_4:
563 ; NEON7-NEXT: .short 341 @ 0x155
564 ; NEON7-NEXT: .short 292 @ 0x124
565 ; NEON7-NEXT: .short 1 @ 0x1
566 ; NEON7-NEXT: .short 0 @ 0x0
567 ;
568 ; NEON8-LABEL: test_urem_vec:
569 ; NEON8: @ %bb.0:
570 ; NEON8-NEXT: vmov.16 d16[0], r0
571 ; NEON8-NEXT: vldr d17, .LCPI4_0
572 ; NEON8-NEXT: vmov.16 d16[1], r1
573 ; NEON8-NEXT: vldr d19, .LCPI4_3
574 ; NEON8-NEXT: vmov.16 d16[2], r2
575 ; NEON8-NEXT: vsub.i16 d16, d16, d17
576 ; NEON8-NEXT: vldr d17, .LCPI4_1
577 ; NEON8-NEXT: vmul.i16 d16, d16, d17
578 ; NEON8-NEXT: vldr d17, .LCPI4_2
579 ; NEON8-NEXT: vneg.s16 d17, d17
580 ; NEON8-NEXT: vshl.i16 d18, d16, #1
581 ; NEON8-NEXT: vbic.i16 d16, #0xf800
582 ; NEON8-NEXT: vshl.u16 d16, d16, d17
583 ; NEON8-NEXT: vshl.u16 d17, d18, d19
584 ; NEON8-NEXT: vorr d16, d16, d17
585 ; NEON8-NEXT: vldr d17, .LCPI4_4
586 ; NEON8-NEXT: vbic.i16 d16, #0xf800
587 ; NEON8-NEXT: vcgt.u16 d16, d16, d17
588 ; NEON8-NEXT: vmov.u16 r0, d16[0]
589 ; NEON8-NEXT: vmov.u16 r1, d16[1]
590 ; NEON8-NEXT: vmov.u16 r2, d16[2]
591 ; NEON8-NEXT: bx lr
592 ; NEON8-NEXT: .p2align 3
593 ; NEON8-NEXT: @ %bb.1:
594 ; NEON8-NEXT: .LCPI4_0:
595 ; NEON8-NEXT: .short 0 @ 0x0
596 ; NEON8-NEXT: .short 1 @ 0x1
597 ; NEON8-NEXT: .short 2 @ 0x2
598 ; NEON8-NEXT: .zero 2
599 ; NEON8-NEXT: .LCPI4_1:
600 ; NEON8-NEXT: .short 683 @ 0x2ab
601 ; NEON8-NEXT: .short 1463 @ 0x5b7
602 ; NEON8-NEXT: .short 819 @ 0x333
603 ; NEON8-NEXT: .zero 2
604 ; NEON8-NEXT: .LCPI4_2:
605 ; NEON8-NEXT: .short 1 @ 0x1
606 ; NEON8-NEXT: .short 0 @ 0x0
607 ; NEON8-NEXT: .short 0 @ 0x0
608 ; NEON8-NEXT: .short 0 @ 0x0
609 ; NEON8-NEXT: .LCPI4_3:
610 ; NEON8-NEXT: .short 9 @ 0x9
611 ; NEON8-NEXT: .short 10 @ 0xa
612 ; NEON8-NEXT: .short 10 @ 0xa
613 ; NEON8-NEXT: .short 10 @ 0xa
614 ; NEON8-NEXT: .LCPI4_4:
615 ; NEON8-NEXT: .short 341 @ 0x155
616 ; NEON8-NEXT: .short 292 @ 0x124
617 ; NEON8-NEXT: .short 1 @ 0x1
618 ; NEON8-NEXT: .short 0 @ 0x0
619 %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
620 %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
621 ret <3 x i1> %cmp
622 }
624 define i1 @test_urem_larger(i63 %X) nounwind {
625 ; ARM5-LABEL: test_urem_larger:
626 ; ARM5: @ %bb.0:
627 ; ARM5-NEXT: push {r4, lr}
628 ; ARM5-NEXT: ldr r12, .LCPI5_0
629 ; ARM5-NEXT: ldr r2, .LCPI5_1
630 ; ARM5-NEXT: umull r3, lr, r0, r12
631 ; ARM5-NEXT: mla r4, r0, r2, lr
632 ; ARM5-NEXT: mla r0, r1, r12, r4
633 ; ARM5-NEXT: bic r0, r0, #-2147483648
634 ; ARM5-NEXT: lsrs r0, r0, #1
635 ; ARM5-NEXT: rrx r1, r3
636 ; ARM5-NEXT: orr r0, r0, r3, lsl #30
637 ; ARM5-NEXT: ldr r3, .LCPI5_2
638 ; ARM5-NEXT: bic r2, r0, #-2147483648
639 ; ARM5-NEXT: mov r0, #0
640 ; ARM5-NEXT: subs r1, r1, r3
641 ; ARM5-NEXT: sbcs r1, r2, #1
642 ; ARM5-NEXT: movlo r0, #1
643 ; ARM5-NEXT: pop {r4, pc}
644 ; ARM5-NEXT: .p2align 2
645 ; ARM5-NEXT: @ %bb.1:
646 ; ARM5-NEXT: .LCPI5_0:
647 ; ARM5-NEXT: .long 3456474841 @ 0xce059ed9
648 ; ARM5-NEXT: .LCPI5_1:
649 ; ARM5-NEXT: .long 790204738 @ 0x2f199142
650 ; ARM5-NEXT: .LCPI5_2:
651 ; ARM5-NEXT: .long 3175964122 @ 0xbd4d5dda
652 ;
653 ; ARM6-LABEL: test_urem_larger:
654 ; ARM6: @ %bb.0:
655 ; ARM6-NEXT: push {r11, lr}
656 ; ARM6-NEXT: ldr r12, .LCPI5_0
657 ; ARM6-NEXT: ldr r2, .LCPI5_1
658 ; ARM6-NEXT: umull r3, lr, r0, r12
659 ; ARM6-NEXT: mla r0, r0, r2, lr
660 ; ARM6-NEXT: mla r0, r1, r12, r0
661 ; ARM6-NEXT: bic r0, r0, #-2147483648
662 ; ARM6-NEXT: lsrs r0, r0, #1
663 ; ARM6-NEXT: rrx r1, r3
664 ; ARM6-NEXT: orr r0, r0, r3, lsl #30
665 ; ARM6-NEXT: ldr r3, .LCPI5_2
666 ; ARM6-NEXT: bic r2, r0, #-2147483648
667 ; ARM6-NEXT: mov r0, #0
668 ; ARM6-NEXT: subs r1, r1, r3
669 ; ARM6-NEXT: sbcs r1, r2, #1
670 ; ARM6-NEXT: movlo r0, #1
671 ; ARM6-NEXT: pop {r11, pc}
672 ; ARM6-NEXT: .p2align 2
673 ; ARM6-NEXT: @ %bb.1:
674 ; ARM6-NEXT: .LCPI5_0:
675 ; ARM6-NEXT: .long 3456474841 @ 0xce059ed9
676 ; ARM6-NEXT: .LCPI5_1:
677 ; ARM6-NEXT: .long 790204738 @ 0x2f199142
678 ; ARM6-NEXT: .LCPI5_2:
679 ; ARM6-NEXT: .long 3175964122 @ 0xbd4d5dda
680 ;
681 ; ARM7-LABEL: test_urem_larger:
682 ; ARM7: @ %bb.0:
683 ; ARM7-NEXT: push {r11, lr}
684 ; ARM7-NEXT: movw r12, #40665
685 ; ARM7-NEXT: movw r2, #37186
686 ; ARM7-NEXT: movt r12, #52741
687 ; ARM7-NEXT: movt r2, #12057
688 ; ARM7-NEXT: umull r3, lr, r0, r12
689 ; ARM7-NEXT: mla r0, r0, r2, lr
690 ; ARM7-NEXT: mla r0, r1, r12, r0
691 ; ARM7-NEXT: bic r0, r0, #-2147483648
692 ; ARM7-NEXT: lsrs r0, r0, #1
693 ; ARM7-NEXT: rrx r1, r3
694 ; ARM7-NEXT: orr r0, r0, r3, lsl #30
695 ; ARM7-NEXT: movw r3, #24026
696 ; ARM7-NEXT: bic r2, r0, #-2147483648
697 ; ARM7-NEXT: movt r3, #48461
698 ; ARM7-NEXT: subs r1, r1, r3
699 ; ARM7-NEXT: mov r0, #0
700 ; ARM7-NEXT: sbcs r1, r2, #1
701 ; ARM7-NEXT: movwlo r0, #1
702 ; ARM7-NEXT: pop {r11, pc}
703 ;
704 ; ARM8-LABEL: test_urem_larger:
705 ; ARM8: @ %bb.0:
706 ; ARM8-NEXT: push {r11, lr}
707 ; ARM8-NEXT: movw r12, #40665
708 ; ARM8-NEXT: movw r2, #37186
709 ; ARM8-NEXT: movt r12, #52741
710 ; ARM8-NEXT: movt r2, #12057
711 ; ARM8-NEXT: umull r3, lr, r0, r12
712 ; ARM8-NEXT: mla r0, r0, r2, lr
713 ; ARM8-NEXT: mla r0, r1, r12, r0
714 ; ARM8-NEXT: bic r0, r0, #-2147483648
715 ; ARM8-NEXT: lsrs r0, r0, #1
716 ; ARM8-NEXT: rrx r1, r3
717 ; ARM8-NEXT: orr r0, r0, r3, lsl #30
718 ; ARM8-NEXT: movw r3, #24026
719 ; ARM8-NEXT: bic r2, r0, #-2147483648
720 ; ARM8-NEXT: movt r3, #48461
721 ; ARM8-NEXT: subs r1, r1, r3
722 ; ARM8-NEXT: mov r0, #0
723 ; ARM8-NEXT: sbcs r1, r2, #1
724 ; ARM8-NEXT: movwlo r0, #1
725 ; ARM8-NEXT: pop {r11, pc}
726 ;
727 ; NEON7-LABEL: test_urem_larger:
728 ; NEON7: @ %bb.0:
729 ; NEON7-NEXT: push {r11, lr}
730 ; NEON7-NEXT: movw r12, #40665
731 ; NEON7-NEXT: movw r2, #37186
732 ; NEON7-NEXT: movt r12, #52741
733 ; NEON7-NEXT: movt r2, #12057
734 ; NEON7-NEXT: umull r3, lr, r0, r12
735 ; NEON7-NEXT: mla r0, r0, r2, lr
736 ; NEON7-NEXT: mla r0, r1, r12, r0
737 ; NEON7-NEXT: bic r0, r0, #-2147483648
738 ; NEON7-NEXT: lsrs r0, r0, #1
739 ; NEON7-NEXT: rrx r1, r3
740 ; NEON7-NEXT: orr r0, r0, r3, lsl #30
741 ; NEON7-NEXT: movw r3, #24026
742 ; NEON7-NEXT: bic r2, r0, #-2147483648
743 ; NEON7-NEXT: movt r3, #48461
744 ; NEON7-NEXT: subs r1, r1, r3
745 ; NEON7-NEXT: mov r0, #0
746 ; NEON7-NEXT: sbcs r1, r2, #1
747 ; NEON7-NEXT: movwlo r0, #1
748 ; NEON7-NEXT: pop {r11, pc}
749 ;
750 ; NEON8-LABEL: test_urem_larger:
751 ; NEON8: @ %bb.0:
752 ; NEON8-NEXT: push {r11, lr}
753 ; NEON8-NEXT: movw r12, #40665
754 ; NEON8-NEXT: movw r2, #37186
755 ; NEON8-NEXT: movt r12, #52741
756 ; NEON8-NEXT: movt r2, #12057
757 ; NEON8-NEXT: umull r3, lr, r0, r12
758 ; NEON8-NEXT: mla r0, r0, r2, lr
759 ; NEON8-NEXT: mla r0, r1, r12, r0
760 ; NEON8-NEXT: bic r0, r0, #-2147483648
761 ; NEON8-NEXT: lsrs r0, r0, #1
762 ; NEON8-NEXT: rrx r1, r3
763 ; NEON8-NEXT: orr r0, r0, r3, lsl #30
764 ; NEON8-NEXT: movw r3, #24026
765 ; NEON8-NEXT: bic r2, r0, #-2147483648
766 ; NEON8-NEXT: movt r3, #48461
767 ; NEON8-NEXT: subs r1, r1, r3
768 ; NEON8-NEXT: mov r0, #0
769 ; NEON8-NEXT: sbcs r1, r2, #1
770 ; NEON8-NEXT: movwlo r0, #1
771 ; NEON8-NEXT: pop {r11, pc}
772 %urem = urem i63 %X, 1234567890
773 %cmp = icmp eq i63 %urem, 0
774 ret i1 %cmp
775 }