| blob | 40b2fc2e08f1b3a9c53d481805e62f00dcd1285f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
3 ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-OPT %s
4 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
5 ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-O0 %s
6 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \
7 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-OPT
8 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \
9 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-O0
11 ; The following testcases take one halfword element from the second vector and
12 ; inserts it at various locations in the first vector
13 define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) {
14 ; CHECK-64-LABEL: shuffle_vector_halfword_0_8:
15 ; CHECK-64: # %bb.0: # %entry
16 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 10
17 ; CHECK-64-NEXT: vinserth 2, 3, 0
18 ; CHECK-64-NEXT: blr
19 ;
20 ; CHECK-32-LABEL: shuffle_vector_halfword_0_8:
21 ; CHECK-32: # %bb.0: # %entry
22 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 10
23 ; CHECK-32-NEXT: vinserth 2, 3, 0
24 ; CHECK-32-NEXT: blr
25 entry:
26 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
27 ret <8 x i16> %vecins
28 }
30 define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) {
31 ; CHECK-64-LABEL: shuffle_vector_halfword_1_15:
32 ; CHECK-64: # %bb.0: # %entry
33 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 8
34 ; CHECK-64-NEXT: vinserth 2, 3, 2
35 ; CHECK-64-NEXT: blr
36 ;
37 ; CHECK-32-LABEL: shuffle_vector_halfword_1_15:
38 ; CHECK-32: # %bb.0: # %entry
39 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 8
40 ; CHECK-32-NEXT: vinserth 2, 3, 2
41 ; CHECK-32-NEXT: blr
42 entry:
43 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
44 ret <8 x i16> %vecins
45 }
47 define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) {
48 ; CHECK-64-LABEL: shuffle_vector_halfword_2_9:
49 ; CHECK-64: # %bb.0: # %entry
50 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 12
51 ; CHECK-64-NEXT: vinserth 2, 3, 4
52 ; CHECK-64-NEXT: blr
53 ;
54 ; CHECK-32-LABEL: shuffle_vector_halfword_2_9:
55 ; CHECK-32: # %bb.0: # %entry
56 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 12
57 ; CHECK-32-NEXT: vinserth 2, 3, 4
58 ; CHECK-32-NEXT: blr
59 entry:
60 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>
61 ret <8 x i16> %vecins
62 }
64 define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) {
65 ; CHECK-64-LABEL: shuffle_vector_halfword_3_13:
66 ; CHECK-64: # %bb.0: # %entry
67 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 4
68 ; CHECK-64-NEXT: vinserth 2, 3, 6
69 ; CHECK-64-NEXT: blr
70 ;
71 ; CHECK-32-LABEL: shuffle_vector_halfword_3_13:
72 ; CHECK-32: # %bb.0: # %entry
73 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 4
74 ; CHECK-32-NEXT: vinserth 2, 3, 6
75 ; CHECK-32-NEXT: blr
76 entry:
77 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
78 ret <8 x i16> %vecins
79 }
81 define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) {
82 ; CHECK-64-LABEL: shuffle_vector_halfword_4_10:
83 ; CHECK-64: # %bb.0: # %entry
84 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 14
85 ; CHECK-64-NEXT: vinserth 2, 3, 8
86 ; CHECK-64-NEXT: blr
87 ;
88 ; CHECK-32-LABEL: shuffle_vector_halfword_4_10:
89 ; CHECK-32: # %bb.0: # %entry
90 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 14
91 ; CHECK-32-NEXT: vinserth 2, 3, 8
92 ; CHECK-32-NEXT: blr
93 entry:
94 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7>
95 ret <8 x i16> %vecins
96 }
98 define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) {
99 ; CHECK-64-LABEL: shuffle_vector_halfword_5_14:
100 ; CHECK-64: # %bb.0: # %entry
101 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 6
102 ; CHECK-64-NEXT: vinserth 2, 3, 10
103 ; CHECK-64-NEXT: blr
104 ;
105 ; CHECK-32-LABEL: shuffle_vector_halfword_5_14:
106 ; CHECK-32: # %bb.0: # %entry
107 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 6
108 ; CHECK-32-NEXT: vinserth 2, 3, 10
109 ; CHECK-32-NEXT: blr
110 entry:
111 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7>
112 ret <8 x i16> %vecins
113 }
115 define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) {
116 ; CHECK-64-LABEL: shuffle_vector_halfword_6_11:
117 ; CHECK-64: # %bb.0: # %entry
118 ; CHECK-64-NEXT: vinserth 2, 3, 12
119 ; CHECK-64-NEXT: blr
120 ;
121 ; CHECK-32-LABEL: shuffle_vector_halfword_6_11:
122 ; CHECK-32: # %bb.0: # %entry
123 ; CHECK-32-NEXT: vinserth 2, 3, 12
124 ; CHECK-32-NEXT: blr
125 entry:
126 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7>
127 ret <8 x i16> %vecins
128 }
130 define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) {
131 ; CHECK-64-LABEL: shuffle_vector_halfword_7_12:
132 ; CHECK-64: # %bb.0: # %entry
133 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 2
134 ; CHECK-64-NEXT: vinserth 2, 3, 14
135 ; CHECK-64-NEXT: blr
136 ;
137 ; CHECK-32-LABEL: shuffle_vector_halfword_7_12:
138 ; CHECK-32: # %bb.0: # %entry
139 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 2
140 ; CHECK-32-NEXT: vinserth 2, 3, 14
141 ; CHECK-32-NEXT: blr
142 entry:
143 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12>
144 ret <8 x i16> %vecins
145 }
147 define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {
148 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_8_1:
149 ; CHECK-64-OPT: # %bb.0: # %entry
150 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 12
151 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 0
152 ; CHECK-64-OPT-NEXT: vmr 2, 3
153 ; CHECK-64-OPT-NEXT: blr
154 ;
155 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_8_1:
156 ; CHECK-64-O0: # %bb.0: # %entry
157 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
158 ; CHECK-64-O0-NEXT: vmr 3, 2
159 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
160 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 12
161 ; CHECK-64-O0-NEXT: vinserth 2, 3, 0
162 ; CHECK-64-O0-NEXT: blr
163 ;
164 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_8_1:
165 ; CHECK-32-OPT: # %bb.0: # %entry
166 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 12
167 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 0
168 ; CHECK-32-OPT-NEXT: vmr 2, 3
169 ; CHECK-32-OPT-NEXT: blr
170 ;
171 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_8_1:
172 ; CHECK-32-O0: # %bb.0: # %entry
173 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
174 ; CHECK-32-O0-NEXT: vmr 3, 2
175 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
176 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 12
177 ; CHECK-32-O0-NEXT: vinserth 2, 3, 0
178 ; CHECK-32-O0-NEXT: blr
179 entry:
180 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
181 ret <8 x i16> %vecins
182 }
184 ; The following testcases take one halfword element from the first vector and
185 ; inserts it at various locations in the second vector
186 define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {
187 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_9_7:
188 ; CHECK-64-OPT: # %bb.0: # %entry
189 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 8
190 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 2
191 ; CHECK-64-OPT-NEXT: vmr 2, 3
192 ; CHECK-64-OPT-NEXT: blr
193 ;
194 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_9_7:
195 ; CHECK-64-O0: # %bb.0: # %entry
196 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
197 ; CHECK-64-O0-NEXT: vmr 3, 2
198 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
199 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 8
200 ; CHECK-64-O0-NEXT: vinserth 2, 3, 2
201 ; CHECK-64-O0-NEXT: blr
202 ;
203 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_9_7:
204 ; CHECK-32-OPT: # %bb.0: # %entry
205 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 8
206 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 2
207 ; CHECK-32-OPT-NEXT: vmr 2, 3
208 ; CHECK-32-OPT-NEXT: blr
209 ;
210 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_9_7:
211 ; CHECK-32-O0: # %bb.0: # %entry
212 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
213 ; CHECK-32-O0-NEXT: vmr 3, 2
214 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
215 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 8
216 ; CHECK-32-O0-NEXT: vinserth 2, 3, 2
217 ; CHECK-32-O0-NEXT: blr
218 entry:
219 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
220 ret <8 x i16> %vecins
221 }
223 define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) {
224 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_10_4:
225 ; CHECK-64-OPT: # %bb.0: # %entry
226 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 2
227 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 4
228 ; CHECK-64-OPT-NEXT: vmr 2, 3
229 ; CHECK-64-OPT-NEXT: blr
230 ;
231 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_10_4:
232 ; CHECK-64-O0: # %bb.0: # %entry
233 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
234 ; CHECK-64-O0-NEXT: vmr 3, 2
235 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
236 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 2
237 ; CHECK-64-O0-NEXT: vinserth 2, 3, 4
238 ; CHECK-64-O0-NEXT: blr
239 ;
240 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_10_4:
241 ; CHECK-32-OPT: # %bb.0: # %entry
242 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 2
243 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 4
244 ; CHECK-32-OPT-NEXT: vmr 2, 3
245 ; CHECK-32-OPT-NEXT: blr
246 ;
247 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_10_4:
248 ; CHECK-32-O0: # %bb.0: # %entry
249 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
250 ; CHECK-32-O0-NEXT: vmr 3, 2
251 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
252 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 2
253 ; CHECK-32-O0-NEXT: vinserth 2, 3, 4
254 ; CHECK-32-O0-NEXT: blr
255 entry:
256 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>
257 ret <8 x i16> %vecins
258 }
260 define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {
261 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_11_2:
262 ; CHECK-64-OPT: # %bb.0: # %entry
263 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 14
264 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 6
265 ; CHECK-64-OPT-NEXT: vmr 2, 3
266 ; CHECK-64-OPT-NEXT: blr
267 ;
268 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_11_2:
269 ; CHECK-64-O0: # %bb.0: # %entry
270 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
271 ; CHECK-64-O0-NEXT: vmr 3, 2
272 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
273 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 14
274 ; CHECK-64-O0-NEXT: vinserth 2, 3, 6
275 ; CHECK-64-O0-NEXT: blr
276 ;
277 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_11_2:
278 ; CHECK-32-OPT: # %bb.0: # %entry
279 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 14
280 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 6
281 ; CHECK-32-OPT-NEXT: vmr 2, 3
282 ; CHECK-32-OPT-NEXT: blr
283 ;
284 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_11_2:
285 ; CHECK-32-O0: # %bb.0: # %entry
286 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
287 ; CHECK-32-O0-NEXT: vmr 3, 2
288 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
289 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 14
290 ; CHECK-32-O0-NEXT: vinserth 2, 3, 6
291 ; CHECK-32-O0-NEXT: blr
292 entry:
293 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>
294 ret <8 x i16> %vecins
295 }
297 define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {
298 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_12_6:
299 ; CHECK-64-OPT: # %bb.0: # %entry
300 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 6
301 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 8
302 ; CHECK-64-OPT-NEXT: vmr 2, 3
303 ; CHECK-64-OPT-NEXT: blr
304 ;
305 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_12_6:
306 ; CHECK-64-O0: # %bb.0: # %entry
307 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
308 ; CHECK-64-O0-NEXT: vmr 3, 2
309 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
310 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 6
311 ; CHECK-64-O0-NEXT: vinserth 2, 3, 8
312 ; CHECK-64-O0-NEXT: blr
313 ;
314 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_12_6:
315 ; CHECK-32-OPT: # %bb.0: # %entry
316 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 6
317 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 8
318 ; CHECK-32-OPT-NEXT: vmr 2, 3
319 ; CHECK-32-OPT-NEXT: blr
320 ;
321 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_12_6:
322 ; CHECK-32-O0: # %bb.0: # %entry
323 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
324 ; CHECK-32-O0-NEXT: vmr 3, 2
325 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
326 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 6
327 ; CHECK-32-O0-NEXT: vinserth 2, 3, 8
328 ; CHECK-32-O0-NEXT: blr
329 entry:
330 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>
331 ret <8 x i16> %vecins
332 }
334 define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {
335 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_13_3:
336 ; CHECK-64-OPT: # %bb.0: # %entry
337 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 10
338 ; CHECK-64-OPT-NEXT: vmr 2, 3
339 ; CHECK-64-OPT-NEXT: blr
340 ;
341 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_13_3:
342 ; CHECK-64-O0: # %bb.0: # %entry
343 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
344 ; CHECK-64-O0-NEXT: vmr 3, 2
345 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
346 ; CHECK-64-O0-NEXT: vinserth 2, 3, 10
347 ; CHECK-64-O0-NEXT: blr
348 ;
349 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_13_3:
350 ; CHECK-32-OPT: # %bb.0: # %entry
351 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 10
352 ; CHECK-32-OPT-NEXT: vmr 2, 3
353 ; CHECK-32-OPT-NEXT: blr
354 ;
355 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_13_3:
356 ; CHECK-32-O0: # %bb.0: # %entry
357 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
358 ; CHECK-32-O0-NEXT: vmr 3, 2
359 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
360 ; CHECK-32-O0-NEXT: vinserth 2, 3, 10
361 ; CHECK-32-O0-NEXT: blr
362 entry:
363 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15>
364 ret <8 x i16> %vecins
365 }
367 define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {
368 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_14_5:
369 ; CHECK-64-OPT: # %bb.0: # %entry
370 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 4
371 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 12
372 ; CHECK-64-OPT-NEXT: vmr 2, 3
373 ; CHECK-64-OPT-NEXT: blr
374 ;
375 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_14_5:
376 ; CHECK-64-O0: # %bb.0: # %entry
377 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
378 ; CHECK-64-O0-NEXT: vmr 3, 2
379 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
380 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 4
381 ; CHECK-64-O0-NEXT: vinserth 2, 3, 12
382 ; CHECK-64-O0-NEXT: blr
383 ;
384 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_14_5:
385 ; CHECK-32-OPT: # %bb.0: # %entry
386 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 4
387 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 12
388 ; CHECK-32-OPT-NEXT: vmr 2, 3
389 ; CHECK-32-OPT-NEXT: blr
390 ;
391 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_14_5:
392 ; CHECK-32-O0: # %bb.0: # %entry
393 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
394 ; CHECK-32-O0-NEXT: vmr 3, 2
395 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
396 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 4
397 ; CHECK-32-O0-NEXT: vinserth 2, 3, 12
398 ; CHECK-32-O0-NEXT: blr
399 entry:
400 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>
401 ret <8 x i16> %vecins
402 }
404 define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {
405 ; CHECK-64-OPT-LABEL: shuffle_vector_halfword_15_0:
406 ; CHECK-64-OPT: # %bb.0: # %entry
407 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 10
408 ; CHECK-64-OPT-NEXT: vinserth 3, 2, 14
409 ; CHECK-64-OPT-NEXT: vmr 2, 3
410 ; CHECK-64-OPT-NEXT: blr
411 ;
412 ; CHECK-64-O0-LABEL: shuffle_vector_halfword_15_0:
413 ; CHECK-64-O0: # %bb.0: # %entry
414 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
415 ; CHECK-64-O0-NEXT: vmr 3, 2
416 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
417 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 10
418 ; CHECK-64-O0-NEXT: vinserth 2, 3, 14
419 ; CHECK-64-O0-NEXT: blr
420 ;
421 ; CHECK-32-OPT-LABEL: shuffle_vector_halfword_15_0:
422 ; CHECK-32-OPT: # %bb.0: # %entry
423 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 10
424 ; CHECK-32-OPT-NEXT: vinserth 3, 2, 14
425 ; CHECK-32-OPT-NEXT: vmr 2, 3
426 ; CHECK-32-OPT-NEXT: blr
427 ;
428 ; CHECK-32-O0-LABEL: shuffle_vector_halfword_15_0:
429 ; CHECK-32-O0: # %bb.0: # %entry
430 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
431 ; CHECK-32-O0-NEXT: vmr 3, 2
432 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
433 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 10
434 ; CHECK-32-O0-NEXT: vinserth 2, 3, 14
435 ; CHECK-32-O0-NEXT: blr
436 entry:
437 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
438 ret <8 x i16> %vecins
439 }
441 ; The following testcases use the same vector in both arguments of the
442 ; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one
443 ; we're attempting to insert, then we can use the vector insert instruction
444 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
445 ; CHECK: # %bb.0: # %entry
446 ; CHECK-NEXT: vinserth 2, 2, 14
447 ; CHECK-NEXT: blr
448 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
449 ; CHECK-BE: # %bb.0: # %entry
450 ; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha
451 ; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l
452 ; CHECK-BE-NEXT: lxvx 35, 0, 3
453 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
454 ; CHECK-BE-NEXT: blr
455 ; CHECK-64-LABEL: shuffle_vector_halfword_0_4:
456 ; CHECK-64: # %bb.0: # %entry
457 ; CHECK-64-NEXT: ld 3, L..C0(2)
458 ; CHECK-64-NEXT: lxv 35, 0(3)
459 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
460 ; CHECK-64-NEXT: blr
461 ;
462 ; CHECK-32-LABEL: shuffle_vector_halfword_0_4:
463 ; CHECK-32: # %bb.0: # %entry
464 ; CHECK-32-NEXT: lwz 3, L..C0(2)
465 ; CHECK-32-NEXT: lxv 35, 0(3)
466 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
467 ; CHECK-32-NEXT: blr
468 entry:
469 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
470 ret <8 x i16> %vecins
471 }
473 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
474 ; CHECK: # %bb.0: # %entry
475 ; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha
476 ; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
477 ; CHECK-NEXT: lxvx 35, 0, 3
478 ; CHECK-NEXT: vperm 2, 2, 2, 3
479 ; CHECK-NEXT: blr
480 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
481 ; CHECK-BE: # %bb.0: # %entry
482 ; CHECK-BE-NEXT: vinserth 2, 2, 2
483 ; CHECK-BE-NEXT: blr
484 ; CHECK-64-LABEL: shuffle_vector_halfword_1_3:
485 ; CHECK-64: # %bb.0: # %entry
486 ; CHECK-64-NEXT: vinserth 2, 2, 2
487 ; CHECK-64-NEXT: blr
488 ;
489 ; CHECK-32-LABEL: shuffle_vector_halfword_1_3:
490 ; CHECK-32: # %bb.0: # %entry
491 ; CHECK-32-NEXT: vinserth 2, 2, 2
492 ; CHECK-32-NEXT: blr
493 entry:
494 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
495 ret <8 x i16> %vecins
496 }
498 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
499 ; CHECK: # %bb.0: # %entry
500 ; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha
501 ; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l
502 ; CHECK-NEXT: lxvx 35, 0, 3
503 ; CHECK-NEXT: vperm 2, 2, 2, 3
504 ; CHECK-NEXT: blr
505 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
506 ; CHECK-BE: # %bb.0: # %entry
507 ; CHECK-BE-NEXT: vinserth 2, 2, 4
508 ; CHECK-BE-NEXT: blr
509 ; CHECK-64-LABEL: shuffle_vector_halfword_2_3:
510 ; CHECK-64: # %bb.0: # %entry
511 ; CHECK-64-NEXT: vinserth 2, 2, 4
512 ; CHECK-64-NEXT: blr
513 ;
514 ; CHECK-32-LABEL: shuffle_vector_halfword_2_3:
515 ; CHECK-32: # %bb.0: # %entry
516 ; CHECK-32-NEXT: vinserth 2, 2, 4
517 ; CHECK-32-NEXT: blr
518 entry:
519 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
520 ret <8 x i16> %vecins
521 }
523 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
524 ; CHECK: # %bb.0: # %entry
525 ; CHECK-NEXT: vinserth 2, 2, 8
526 ; CHECK-NEXT: blr
527 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
528 ; CHECK-BE: # %bb.0: # %entry
529 ; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha
530 ; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l
531 ; CHECK-BE-NEXT: lxvx 35, 0, 3
532 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
533 ; CHECK-BE-NEXT: blr
534 ; CHECK-64-LABEL: shuffle_vector_halfword_3_4:
535 ; CHECK-64: # %bb.0: # %entry
536 ; CHECK-64-NEXT: ld 3, L..C1(2)
537 ; CHECK-64-NEXT: lxv 35, 0(3)
538 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
539 ; CHECK-64-NEXT: blr
540 ;
541 ; CHECK-32-LABEL: shuffle_vector_halfword_3_4:
542 ; CHECK-32: # %bb.0: # %entry
543 ; CHECK-32-NEXT: lwz 3, L..C1(2)
544 ; CHECK-32-NEXT: lxv 35, 0(3)
545 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
546 ; CHECK-32-NEXT: blr
547 entry:
548 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
549 ret <8 x i16> %vecins
550 }
552 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
553 ; CHECK: # %bb.0: # %entry
554 ; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha
555 ; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l
556 ; CHECK-NEXT: lxvx 35, 0, 3
557 ; CHECK-NEXT: vperm 2, 2, 2, 3
558 ; CHECK-NEXT: blr
559 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
560 ; CHECK-BE: # %bb.0: # %entry
561 ; CHECK-BE-NEXT: vinserth 2, 2, 8
562 ; CHECK-BE-NEXT: blr
563 ; CHECK-64-LABEL: shuffle_vector_halfword_4_3:
564 ; CHECK-64: # %bb.0: # %entry
565 ; CHECK-64-NEXT: vinserth 2, 2, 8
566 ; CHECK-64-NEXT: blr
567 ;
568 ; CHECK-32-LABEL: shuffle_vector_halfword_4_3:
569 ; CHECK-32: # %bb.0: # %entry
570 ; CHECK-32-NEXT: vinserth 2, 2, 8
571 ; CHECK-32-NEXT: blr
572 entry:
573 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
574 ret <8 x i16> %vecins
575 }
577 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
578 ; CHECK: # %bb.0: # %entry
579 ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha
580 ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
581 ; CHECK-NEXT: lxvx 35, 0, 3
582 ; CHECK-NEXT: vperm 2, 2, 2, 3
583 ; CHECK-NEXT: blr
584 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
585 ; CHECK-BE: # %bb.0: # %entry
586 ; CHECK-BE-NEXT: vinserth 2, 2, 10
587 ; CHECK-BE-NEXT: blr
588 ; CHECK-64-LABEL: shuffle_vector_halfword_5_3:
589 ; CHECK-64: # %bb.0: # %entry
590 ; CHECK-64-NEXT: vinserth 2, 2, 10
591 ; CHECK-64-NEXT: blr
592 ;
593 ; CHECK-32-LABEL: shuffle_vector_halfword_5_3:
594 ; CHECK-32: # %bb.0: # %entry
595 ; CHECK-32-NEXT: vinserth 2, 2, 10
596 ; CHECK-32-NEXT: blr
597 entry:
598 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
599 ret <8 x i16> %vecins
600 }
602 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
603 ; CHECK: # %bb.0: # %entry
604 ; CHECK-NEXT: vinserth 2, 2, 2
605 ; CHECK-NEXT: blr
606 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
607 ; CHECK-BE: # %bb.0: # %entry
608 ; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha
609 ; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l
610 ; CHECK-BE-NEXT: lxvx 35, 0, 3
611 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
612 ; CHECK-BE-NEXT: blr
613 ; CHECK-64-LABEL: shuffle_vector_halfword_6_4:
614 ; CHECK-64: # %bb.0: # %entry
615 ; CHECK-64-NEXT: ld 3, L..C2(2)
616 ; CHECK-64-NEXT: lxv 35, 0(3)
617 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
618 ; CHECK-64-NEXT: blr
619 ;
620 ; CHECK-32-LABEL: shuffle_vector_halfword_6_4:
621 ; CHECK-32: # %bb.0: # %entry
622 ; CHECK-32-NEXT: lwz 3, L..C2(2)
623 ; CHECK-32-NEXT: lxv 35, 0(3)
624 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
625 ; CHECK-32-NEXT: blr
626 entry:
627 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
628 ret <8 x i16> %vecins
629 }
631 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
632 ; CHECK: # %bb.0: # %entry
633 ; CHECK-NEXT: vinserth 2, 2, 0
634 ; CHECK-NEXT: blr
635 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
636 ; CHECK-BE: # %bb.0: # %entry
637 ; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha
638 ; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l
639 ; CHECK-BE-NEXT: lxvx 35, 0, 3
640 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
641 ; CHECK-BE-NEXT: blr
642 ; CHECK-64-LABEL: shuffle_vector_halfword_7_4:
643 ; CHECK-64: # %bb.0: # %entry
644 ; CHECK-64-NEXT: ld 3, L..C3(2)
645 ; CHECK-64-NEXT: lxv 35, 0(3)
646 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
647 ; CHECK-64-NEXT: blr
648 ;
649 ; CHECK-32-LABEL: shuffle_vector_halfword_7_4:
650 ; CHECK-32: # %bb.0: # %entry
651 ; CHECK-32-NEXT: lwz 3, L..C3(2)
652 ; CHECK-32-NEXT: lxv 35, 0(3)
653 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
654 ; CHECK-32-NEXT: blr
655 entry:
656 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
657 ret <8 x i16> %vecins
658 }
660 ; The following testcases take one byte element from the second vector and
661 ; inserts it at various locations in the first vector
662 define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {
663 ; CHECK: # %bb.0: # %entry
664 ; CHECK-NEXT: vsldoi 3, 3, 3, 8
665 ; CHECK-NEXT: vinsertb 2, 3, 15
666 ; CHECK-NEXT: blr
667 ; CHECK-BE-LABEL: shuffle_vector_byte_0_16:
668 ; CHECK-BE: # %bb.0: # %entry
669 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 9
670 ; CHECK-BE-NEXT: vinsertb 2, 3, 0
671 ; CHECK-BE-NEXT: blr
672 ; CHECK-64-LABEL: shuffle_vector_byte_0_16:
673 ; CHECK-64: # %bb.0: # %entry
674 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 9
675 ; CHECK-64-NEXT: vinsertb 2, 3, 0
676 ; CHECK-64-NEXT: blr
677 ;
678 ; CHECK-32-LABEL: shuffle_vector_byte_0_16:
679 ; CHECK-32: # %bb.0: # %entry
680 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 9
681 ; CHECK-32-NEXT: vinsertb 2, 3, 0
682 ; CHECK-32-NEXT: blr
683 entry:
684 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
685 ret <16 x i8> %vecins
686 }
688 define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {
689 ; CHECK: # %bb.0: # %entry
690 ; CHECK-NEXT: vsldoi 3, 3, 3, 15
691 ; CHECK-NEXT: vinsertb 2, 3, 14
692 ; CHECK-NEXT: blr
693 ; CHECK-BE-LABEL: shuffle_vector_byte_1_25:
694 ; CHECK-BE: # %bb.0: # %entry
695 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 2
696 ; CHECK-BE-NEXT: vinsertb 2, 3, 1
697 ; CHECK-BE-NEXT: blr
698 ; CHECK-64-LABEL: shuffle_vector_byte_1_25:
699 ; CHECK-64: # %bb.0: # %entry
700 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 2
701 ; CHECK-64-NEXT: vinsertb 2, 3, 1
702 ; CHECK-64-NEXT: blr
703 ;
704 ; CHECK-32-LABEL: shuffle_vector_byte_1_25:
705 ; CHECK-32: # %bb.0: # %entry
706 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 2
707 ; CHECK-32-NEXT: vinsertb 2, 3, 1
708 ; CHECK-32-NEXT: blr
709 entry:
710 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
711 ret <16 x i8> %vecins
712 }
714 define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {
715 ; CHECK: # %bb.0: # %entry
716 ; CHECK-NEXT: vsldoi 3, 3, 3, 6
717 ; CHECK-NEXT: vinsertb 2, 3, 13
718 ; CHECK-NEXT: blr
719 ; CHECK-BE-LABEL: shuffle_vector_byte_2_18:
720 ; CHECK-BE: # %bb.0: # %entry
721 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 11
722 ; CHECK-BE-NEXT: vinsertb 2, 3, 2
723 ; CHECK-BE-NEXT: blr
724 ; CHECK-64-LABEL: shuffle_vector_byte_2_18:
725 ; CHECK-64: # %bb.0: # %entry
726 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 11
727 ; CHECK-64-NEXT: vinsertb 2, 3, 2
728 ; CHECK-64-NEXT: blr
729 ;
730 ; CHECK-32-LABEL: shuffle_vector_byte_2_18:
731 ; CHECK-32: # %bb.0: # %entry
732 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 11
733 ; CHECK-32-NEXT: vinsertb 2, 3, 2
734 ; CHECK-32-NEXT: blr
735 entry:
736 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
737 ret <16 x i8> %vecins
738 }
740 define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {
741 ; CHECK: # %bb.0: # %entry
742 ; CHECK-NEXT: vsldoi 3, 3, 3, 13
743 ; CHECK-NEXT: vinsertb 2, 3, 12
744 ; CHECK-NEXT: blr
745 ; CHECK-BE-LABEL: shuffle_vector_byte_3_27:
746 ; CHECK-BE: # %bb.0: # %entry
747 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 4
748 ; CHECK-BE-NEXT: vinsertb 2, 3, 3
749 ; CHECK-BE-NEXT: blr
750 ; CHECK-64-LABEL: shuffle_vector_byte_3_27:
751 ; CHECK-64: # %bb.0: # %entry
752 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 4
753 ; CHECK-64-NEXT: vinsertb 2, 3, 3
754 ; CHECK-64-NEXT: blr
755 ;
756 ; CHECK-32-LABEL: shuffle_vector_byte_3_27:
757 ; CHECK-32: # %bb.0: # %entry
758 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 4
759 ; CHECK-32-NEXT: vinsertb 2, 3, 3
760 ; CHECK-32-NEXT: blr
761 entry:
762 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
763 ret <16 x i8> %vecins
764 }
766 define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {
767 ; CHECK: # %bb.0: # %entry
768 ; CHECK-NEXT: vsldoi 3, 3, 3, 4
769 ; CHECK-NEXT: vinsertb 2, 3, 11
770 ; CHECK-NEXT: blr
771 ; CHECK-BE-LABEL: shuffle_vector_byte_4_20:
772 ; CHECK-BE: # %bb.0: # %entry
773 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 13
774 ; CHECK-BE-NEXT: vinsertb 2, 3, 4
775 ; CHECK-BE-NEXT: blr
776 ; CHECK-64-LABEL: shuffle_vector_byte_4_20:
777 ; CHECK-64: # %bb.0: # %entry
778 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 13
779 ; CHECK-64-NEXT: vinsertb 2, 3, 4
780 ; CHECK-64-NEXT: blr
781 ;
782 ; CHECK-32-LABEL: shuffle_vector_byte_4_20:
783 ; CHECK-32: # %bb.0: # %entry
784 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 13
785 ; CHECK-32-NEXT: vinsertb 2, 3, 4
786 ; CHECK-32-NEXT: blr
787 entry:
788 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
789 ret <16 x i8> %vecins
790 }
792 define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {
793 ; CHECK: # %bb.0: # %entry
794 ; CHECK-NEXT: vsldoi 3, 3, 3, 11
795 ; CHECK-NEXT: vinsertb 2, 3, 10
796 ; CHECK-NEXT: blr
797 ; CHECK-BE-LABEL: shuffle_vector_byte_5_29:
798 ; CHECK-BE: # %bb.0: # %entry
799 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 6
800 ; CHECK-BE-NEXT: vinsertb 2, 3, 5
801 ; CHECK-BE-NEXT: blr
802 ; CHECK-64-LABEL: shuffle_vector_byte_5_29:
803 ; CHECK-64: # %bb.0: # %entry
804 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 6
805 ; CHECK-64-NEXT: vinsertb 2, 3, 5
806 ; CHECK-64-NEXT: blr
807 ;
808 ; CHECK-32-LABEL: shuffle_vector_byte_5_29:
809 ; CHECK-32: # %bb.0: # %entry
810 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 6
811 ; CHECK-32-NEXT: vinsertb 2, 3, 5
812 ; CHECK-32-NEXT: blr
813 entry:
814 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
815 ret <16 x i8> %vecins
816 }
818 define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {
819 ; CHECK: # %bb.0: # %entry
820 ; CHECK-NEXT: vsldoi 3, 3, 3, 2
821 ; CHECK-NEXT: vinsertb 2, 3, 9
822 ; CHECK-NEXT: blr
823 ; CHECK-BE-LABEL: shuffle_vector_byte_6_22:
824 ; CHECK-BE: # %bb.0: # %entry
825 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 15
826 ; CHECK-BE-NEXT: vinsertb 2, 3, 6
827 ; CHECK-BE-NEXT: blr
828 ; CHECK-64-LABEL: shuffle_vector_byte_6_22:
829 ; CHECK-64: # %bb.0: # %entry
830 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 15
831 ; CHECK-64-NEXT: vinsertb 2, 3, 6
832 ; CHECK-64-NEXT: blr
833 ;
834 ; CHECK-32-LABEL: shuffle_vector_byte_6_22:
835 ; CHECK-32: # %bb.0: # %entry
836 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 15
837 ; CHECK-32-NEXT: vinsertb 2, 3, 6
838 ; CHECK-32-NEXT: blr
839 entry:
840 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
841 ret <16 x i8> %vecins
842 }
844 define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {
845 ; CHECK: # %bb.0: # %entry
846 ; CHECK-NEXT: vsldoi 3, 3, 3, 9
847 ; CHECK-NEXT: vinsertb 2, 3, 8
848 ; CHECK-NEXT: blr
849 ; CHECK-BE-LABEL: shuffle_vector_byte_7_31:
850 ; CHECK-BE: # %bb.0: # %entry
851 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 8
852 ; CHECK-BE-NEXT: vinsertb 2, 3, 7
853 ; CHECK-BE-NEXT: blr
854 ; CHECK-64-LABEL: shuffle_vector_byte_7_31:
855 ; CHECK-64: # %bb.0: # %entry
856 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 8
857 ; CHECK-64-NEXT: vinsertb 2, 3, 7
858 ; CHECK-64-NEXT: blr
859 ;
860 ; CHECK-32-LABEL: shuffle_vector_byte_7_31:
861 ; CHECK-32: # %bb.0: # %entry
862 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 8
863 ; CHECK-32-NEXT: vinsertb 2, 3, 7
864 ; CHECK-32-NEXT: blr
865 entry:
866 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
867 ret <16 x i8> %vecins
868 }
870 define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {
871 ; CHECK: # %bb.0: # %entry
872 ; CHECK-NEXT: vinsertb 2, 3, 7
873 ; CHECK-NEXT: blr
874 ; CHECK-BE-LABEL: shuffle_vector_byte_8_24:
875 ; CHECK-BE: # %bb.0: # %entry
876 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 1
877 ; CHECK-BE-NEXT: vinsertb 2, 3, 8
878 ; CHECK-BE-NEXT: blr
879 ; CHECK-64-LABEL: shuffle_vector_byte_8_24:
880 ; CHECK-64: # %bb.0: # %entry
881 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 1
882 ; CHECK-64-NEXT: vinsertb 2, 3, 8
883 ; CHECK-64-NEXT: blr
884 ;
885 ; CHECK-32-LABEL: shuffle_vector_byte_8_24:
886 ; CHECK-32: # %bb.0: # %entry
887 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 1
888 ; CHECK-32-NEXT: vinsertb 2, 3, 8
889 ; CHECK-32-NEXT: blr
890 entry:
891 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
892 ret <16 x i8> %vecins
893 }
895 define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {
896 ; CHECK: # %bb.0: # %entry
897 ; CHECK-NEXT: vsldoi 3, 3, 3, 7
898 ; CHECK-NEXT: vinsertb 2, 3, 6
899 ; CHECK-NEXT: blr
900 ; CHECK-BE-LABEL: shuffle_vector_byte_9_17:
901 ; CHECK-BE: # %bb.0: # %entry
902 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 10
903 ; CHECK-BE-NEXT: vinsertb 2, 3, 9
904 ; CHECK-BE-NEXT: blr
905 ; CHECK-64-LABEL: shuffle_vector_byte_9_17:
906 ; CHECK-64: # %bb.0: # %entry
907 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 10
908 ; CHECK-64-NEXT: vinsertb 2, 3, 9
909 ; CHECK-64-NEXT: blr
910 ;
911 ; CHECK-32-LABEL: shuffle_vector_byte_9_17:
912 ; CHECK-32: # %bb.0: # %entry
913 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 10
914 ; CHECK-32-NEXT: vinsertb 2, 3, 9
915 ; CHECK-32-NEXT: blr
916 entry:
917 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
918 ret <16 x i8> %vecins
919 }
921 define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {
922 ; CHECK: # %bb.0: # %entry
923 ; CHECK-NEXT: vsldoi 3, 3, 3, 14
924 ; CHECK-NEXT: vinsertb 2, 3, 5
925 ; CHECK-NEXT: blr
926 ; CHECK-BE-LABEL: shuffle_vector_byte_10_26:
927 ; CHECK-BE: # %bb.0: # %entry
928 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 3
929 ; CHECK-BE-NEXT: vinsertb 2, 3, 10
930 ; CHECK-BE-NEXT: blr
931 ; CHECK-64-LABEL: shuffle_vector_byte_10_26:
932 ; CHECK-64: # %bb.0: # %entry
933 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 3
934 ; CHECK-64-NEXT: vinsertb 2, 3, 10
935 ; CHECK-64-NEXT: blr
936 ;
937 ; CHECK-32-LABEL: shuffle_vector_byte_10_26:
938 ; CHECK-32: # %bb.0: # %entry
939 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 3
940 ; CHECK-32-NEXT: vinsertb 2, 3, 10
941 ; CHECK-32-NEXT: blr
942 entry:
943 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>
944 ret <16 x i8> %vecins
945 }
947 define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {
948 ; CHECK: # %bb.0: # %entry
949 ; CHECK-NEXT: vsldoi 3, 3, 3, 5
950 ; CHECK-NEXT: vinsertb 2, 3, 4
951 ; CHECK-NEXT: blr
952 ; CHECK-BE-LABEL: shuffle_vector_byte_11_19:
953 ; CHECK-BE: # %bb.0: # %entry
954 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 12
955 ; CHECK-BE-NEXT: vinsertb 2, 3, 11
956 ; CHECK-BE-NEXT: blr
957 ; CHECK-64-LABEL: shuffle_vector_byte_11_19:
958 ; CHECK-64: # %bb.0: # %entry
959 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 12
960 ; CHECK-64-NEXT: vinsertb 2, 3, 11
961 ; CHECK-64-NEXT: blr
962 ;
963 ; CHECK-32-LABEL: shuffle_vector_byte_11_19:
964 ; CHECK-32: # %bb.0: # %entry
965 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 12
966 ; CHECK-32-NEXT: vinsertb 2, 3, 11
967 ; CHECK-32-NEXT: blr
968 entry:
969 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15>
970 ret <16 x i8> %vecins
971 }
973 define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {
974 ; CHECK: # %bb.0: # %entry
975 ; CHECK-NEXT: vsldoi 3, 3, 3, 12
976 ; CHECK-NEXT: vinsertb 2, 3, 3
977 ; CHECK-NEXT: blr
978 ; CHECK-BE-LABEL: shuffle_vector_byte_12_28:
979 ; CHECK-BE: # %bb.0: # %entry
980 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 5
981 ; CHECK-BE-NEXT: vinsertb 2, 3, 12
982 ; CHECK-BE-NEXT: blr
983 ; CHECK-64-LABEL: shuffle_vector_byte_12_28:
984 ; CHECK-64: # %bb.0: # %entry
985 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 5
986 ; CHECK-64-NEXT: vinsertb 2, 3, 12
987 ; CHECK-64-NEXT: blr
988 ;
989 ; CHECK-32-LABEL: shuffle_vector_byte_12_28:
990 ; CHECK-32: # %bb.0: # %entry
991 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 5
992 ; CHECK-32-NEXT: vinsertb 2, 3, 12
993 ; CHECK-32-NEXT: blr
994 entry:
995 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15>
996 ret <16 x i8> %vecins
997 }
999 define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {
1000 ; CHECK: # %bb.0: # %entry
1001 ; CHECK-NEXT: vsldoi 3, 3, 3, 3
1002 ; CHECK-NEXT: vinsertb 2, 3, 2
1003 ; CHECK-NEXT: blr
1004 ; CHECK-BE-LABEL: shuffle_vector_byte_13_21:
1005 ; CHECK-BE: # %bb.0: # %entry
1006 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 14
1007 ; CHECK-BE-NEXT: vinsertb 2, 3, 13
1008 ; CHECK-BE-NEXT: blr
1009 ; CHECK-64-LABEL: shuffle_vector_byte_13_21:
1010 ; CHECK-64: # %bb.0: # %entry
1011 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 14
1012 ; CHECK-64-NEXT: vinsertb 2, 3, 13
1013 ; CHECK-64-NEXT: blr
1014 ;
1015 ; CHECK-32-LABEL: shuffle_vector_byte_13_21:
1016 ; CHECK-32: # %bb.0: # %entry
1017 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 14
1018 ; CHECK-32-NEXT: vinsertb 2, 3, 13
1019 ; CHECK-32-NEXT: blr
1020 entry:
1021 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15>
1022 ret <16 x i8> %vecins
1023 }
1025 define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {
1026 ; CHECK: # %bb.0: # %entry
1027 ; CHECK-NEXT: vsldoi 3, 3, 3, 10
1028 ; CHECK-NEXT: vinsertb 2, 3, 1
1029 ; CHECK-NEXT: blr
1030 ; CHECK-BE-LABEL: shuffle_vector_byte_14_30:
1031 ; CHECK-BE: # %bb.0: # %entry
1032 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 7
1033 ; CHECK-BE-NEXT: vinsertb 2, 3, 14
1034 ; CHECK-BE-NEXT: blr
1035 ; CHECK-64-LABEL: shuffle_vector_byte_14_30:
1036 ; CHECK-64: # %bb.0: # %entry
1037 ; CHECK-64-NEXT: vsldoi 3, 3, 3, 7
1038 ; CHECK-64-NEXT: vinsertb 2, 3, 14
1039 ; CHECK-64-NEXT: blr
1040 ;
1041 ; CHECK-32-LABEL: shuffle_vector_byte_14_30:
1042 ; CHECK-32: # %bb.0: # %entry
1043 ; CHECK-32-NEXT: vsldoi 3, 3, 3, 7
1044 ; CHECK-32-NEXT: vinsertb 2, 3, 14
1045 ; CHECK-32-NEXT: blr
1046 entry:
1047 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>
1048 ret <16 x i8> %vecins
1049 }
1051 define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {
1052 ; CHECK: # %bb.0: # %entry
1053 ; CHECK-NEXT: vsldoi 3, 3, 3, 1
1054 ; CHECK-NEXT: vinsertb 2, 3, 0
1055 ; CHECK-NEXT: blr
1056 ; CHECK-BE-LABEL: shuffle_vector_byte_15_23:
1057 ; CHECK-BE: # %bb.0: # %entry
1058 ; CHECK-BE-NEXT: vinsertb 2, 3, 15
1059 ; CHECK-BE-NEXT: blr
1060 ; CHECK-64-LABEL: shuffle_vector_byte_15_23:
1061 ; CHECK-64: # %bb.0: # %entry
1062 ; CHECK-64-NEXT: vinsertb 2, 3, 15
1063 ; CHECK-64-NEXT: blr
1064 ;
1065 ; CHECK-32-LABEL: shuffle_vector_byte_15_23:
1066 ; CHECK-32: # %bb.0: # %entry
1067 ; CHECK-32-NEXT: vinsertb 2, 3, 15
1068 ; CHECK-32-NEXT: blr
1069 entry:
1070 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23>
1071 ret <16 x i8> %vecins
1072 }
1074 ; The following testcases take one byte element from the first vector and
1075 ; inserts it at various locations in the second vector
1076 define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) {
1077 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_16_8:
1078 ; CHECK-64-OPT: # %bb.0: # %entry
1079 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 1
1080 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 0
1081 ; CHECK-64-OPT-NEXT: vmr 2, 3
1082 ; CHECK-64-OPT-NEXT: blr
1083 ;
1084 ; CHECK-64-O0-LABEL: shuffle_vector_byte_16_8:
1085 ; CHECK-64-O0: # %bb.0: # %entry
1086 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1087 ; CHECK-64-O0-NEXT: vmr 3, 2
1088 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1089 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 1
1090 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 0
1091 ; CHECK-64-O0-NEXT: blr
1092 ;
1093 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_16_8:
1094 ; CHECK-32-OPT: # %bb.0: # %entry
1095 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 1
1096 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 0
1097 ; CHECK-32-OPT-NEXT: vmr 2, 3
1098 ; CHECK-32-OPT-NEXT: blr
1099 ;
1100 ; CHECK-32-O0-LABEL: shuffle_vector_byte_16_8:
1101 ; CHECK-32-O0: # %bb.0: # %entry
1102 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1103 ; CHECK-32-O0-NEXT: vmr 3, 2
1104 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1105 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 1
1106 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 0
1107 ; CHECK-32-O0-NEXT: blr
1108 entry:
1109 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1110 ret <16 x i8> %vecins
1111 }
1113 define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) {
1114 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_17_1:
1115 ; CHECK-64-OPT: # %bb.0: # %entry
1116 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 10
1117 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 1
1118 ; CHECK-64-OPT-NEXT: vmr 2, 3
1119 ; CHECK-64-OPT-NEXT: blr
1120 ;
1121 ; CHECK-64-O0-LABEL: shuffle_vector_byte_17_1:
1122 ; CHECK-64-O0: # %bb.0: # %entry
1123 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1124 ; CHECK-64-O0-NEXT: vmr 3, 2
1125 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1126 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 10
1127 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 1
1128 ; CHECK-64-O0-NEXT: blr
1129 ;
1130 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_17_1:
1131 ; CHECK-32-OPT: # %bb.0: # %entry
1132 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 10
1133 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 1
1134 ; CHECK-32-OPT-NEXT: vmr 2, 3
1135 ; CHECK-32-OPT-NEXT: blr
1136 ;
1137 ; CHECK-32-O0-LABEL: shuffle_vector_byte_17_1:
1138 ; CHECK-32-O0: # %bb.0: # %entry
1139 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1140 ; CHECK-32-O0-NEXT: vmr 3, 2
1141 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1142 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 10
1143 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 1
1144 ; CHECK-32-O0-NEXT: blr
1145 entry:
1146 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1147 ret <16 x i8> %vecins
1148 }
1150 define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) {
1151 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_18_10:
1152 ; CHECK-64-OPT: # %bb.0: # %entry
1153 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 3
1154 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 2
1155 ; CHECK-64-OPT-NEXT: vmr 2, 3
1156 ; CHECK-64-OPT-NEXT: blr
1157 ;
1158 ; CHECK-64-O0-LABEL: shuffle_vector_byte_18_10:
1159 ; CHECK-64-O0: # %bb.0: # %entry
1160 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1161 ; CHECK-64-O0-NEXT: vmr 3, 2
1162 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1163 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 3
1164 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 2
1165 ; CHECK-64-O0-NEXT: blr
1166 ;
1167 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_18_10:
1168 ; CHECK-32-OPT: # %bb.0: # %entry
1169 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 3
1170 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 2
1171 ; CHECK-32-OPT-NEXT: vmr 2, 3
1172 ; CHECK-32-OPT-NEXT: blr
1173 ;
1174 ; CHECK-32-O0-LABEL: shuffle_vector_byte_18_10:
1175 ; CHECK-32-O0: # %bb.0: # %entry
1176 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1177 ; CHECK-32-O0-NEXT: vmr 3, 2
1178 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1179 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 3
1180 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 2
1181 ; CHECK-32-O0-NEXT: blr
1182 entry:
1183 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1184 ret <16 x i8> %vecins
1185 }
1187 define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) {
1188 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_19_3:
1189 ; CHECK-64-OPT: # %bb.0: # %entry
1190 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 12
1191 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 3
1192 ; CHECK-64-OPT-NEXT: vmr 2, 3
1193 ; CHECK-64-OPT-NEXT: blr
1194 ;
1195 ; CHECK-64-O0-LABEL: shuffle_vector_byte_19_3:
1196 ; CHECK-64-O0: # %bb.0: # %entry
1197 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1198 ; CHECK-64-O0-NEXT: vmr 3, 2
1199 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1200 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 12
1201 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 3
1202 ; CHECK-64-O0-NEXT: blr
1203 ;
1204 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_19_3:
1205 ; CHECK-32-OPT: # %bb.0: # %entry
1206 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 12
1207 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 3
1208 ; CHECK-32-OPT-NEXT: vmr 2, 3
1209 ; CHECK-32-OPT-NEXT: blr
1210 ;
1211 ; CHECK-32-O0-LABEL: shuffle_vector_byte_19_3:
1212 ; CHECK-32-O0: # %bb.0: # %entry
1213 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1214 ; CHECK-32-O0-NEXT: vmr 3, 2
1215 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1216 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 12
1217 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 3
1218 ; CHECK-32-O0-NEXT: blr
1219 entry:
1220 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1221 ret <16 x i8> %vecins
1222 }
1224 define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) {
1225 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_20_12:
1226 ; CHECK-64-OPT: # %bb.0: # %entry
1227 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 5
1228 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 4
1229 ; CHECK-64-OPT-NEXT: vmr 2, 3
1230 ; CHECK-64-OPT-NEXT: blr
1231 ;
1232 ; CHECK-64-O0-LABEL: shuffle_vector_byte_20_12:
1233 ; CHECK-64-O0: # %bb.0: # %entry
1234 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1235 ; CHECK-64-O0-NEXT: vmr 3, 2
1236 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1237 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 5
1238 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 4
1239 ; CHECK-64-O0-NEXT: blr
1240 ;
1241 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_20_12:
1242 ; CHECK-32-OPT: # %bb.0: # %entry
1243 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 5
1244 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 4
1245 ; CHECK-32-OPT-NEXT: vmr 2, 3
1246 ; CHECK-32-OPT-NEXT: blr
1247 ;
1248 ; CHECK-32-O0-LABEL: shuffle_vector_byte_20_12:
1249 ; CHECK-32-O0: # %bb.0: # %entry
1250 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1251 ; CHECK-32-O0-NEXT: vmr 3, 2
1252 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1253 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 5
1254 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 4
1255 ; CHECK-32-O0-NEXT: blr
1256 entry:
1257 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1258 ret <16 x i8> %vecins
1259 }
1261 define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) {
1262 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_21_5:
1263 ; CHECK-64-OPT: # %bb.0: # %entry
1264 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 14
1265 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 5
1266 ; CHECK-64-OPT-NEXT: vmr 2, 3
1267 ; CHECK-64-OPT-NEXT: blr
1268 ;
1269 ; CHECK-64-O0-LABEL: shuffle_vector_byte_21_5:
1270 ; CHECK-64-O0: # %bb.0: # %entry
1271 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1272 ; CHECK-64-O0-NEXT: vmr 3, 2
1273 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1274 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 14
1275 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 5
1276 ; CHECK-64-O0-NEXT: blr
1277 ;
1278 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_21_5:
1279 ; CHECK-32-OPT: # %bb.0: # %entry
1280 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 14
1281 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 5
1282 ; CHECK-32-OPT-NEXT: vmr 2, 3
1283 ; CHECK-32-OPT-NEXT: blr
1284 ;
1285 ; CHECK-32-O0-LABEL: shuffle_vector_byte_21_5:
1286 ; CHECK-32-O0: # %bb.0: # %entry
1287 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1288 ; CHECK-32-O0-NEXT: vmr 3, 2
1289 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1290 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 14
1291 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 5
1292 ; CHECK-32-O0-NEXT: blr
1293 entry:
1294 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1295 ret <16 x i8> %vecins
1296 }
1298 define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) {
1299 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_22_14:
1300 ; CHECK-64-OPT: # %bb.0: # %entry
1301 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 7
1302 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 6
1303 ; CHECK-64-OPT-NEXT: vmr 2, 3
1304 ; CHECK-64-OPT-NEXT: blr
1305 ;
1306 ; CHECK-64-O0-LABEL: shuffle_vector_byte_22_14:
1307 ; CHECK-64-O0: # %bb.0: # %entry
1308 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1309 ; CHECK-64-O0-NEXT: vmr 3, 2
1310 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1311 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 7
1312 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 6
1313 ; CHECK-64-O0-NEXT: blr
1314 ;
1315 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_22_14:
1316 ; CHECK-32-OPT: # %bb.0: # %entry
1317 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 7
1318 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 6
1319 ; CHECK-32-OPT-NEXT: vmr 2, 3
1320 ; CHECK-32-OPT-NEXT: blr
1321 ;
1322 ; CHECK-32-O0-LABEL: shuffle_vector_byte_22_14:
1323 ; CHECK-32-O0: # %bb.0: # %entry
1324 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1325 ; CHECK-32-O0-NEXT: vmr 3, 2
1326 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1327 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 7
1328 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 6
1329 ; CHECK-32-O0-NEXT: blr
1330 entry:
1331 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1332 ret <16 x i8> %vecins
1333 }
1335 define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) {
1336 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_23_7:
1337 ; CHECK-64-OPT: # %bb.0: # %entry
1338 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 7
1339 ; CHECK-64-OPT-NEXT: vmr 2, 3
1340 ; CHECK-64-OPT-NEXT: blr
1341 ;
1342 ; CHECK-64-O0-LABEL: shuffle_vector_byte_23_7:
1343 ; CHECK-64-O0: # %bb.0: # %entry
1344 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1345 ; CHECK-64-O0-NEXT: vmr 3, 2
1346 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1347 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 7
1348 ; CHECK-64-O0-NEXT: blr
1349 ;
1350 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_23_7:
1351 ; CHECK-32-OPT: # %bb.0: # %entry
1352 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 7
1353 ; CHECK-32-OPT-NEXT: vmr 2, 3
1354 ; CHECK-32-OPT-NEXT: blr
1355 ;
1356 ; CHECK-32-O0-LABEL: shuffle_vector_byte_23_7:
1357 ; CHECK-32-O0: # %bb.0: # %entry
1358 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1359 ; CHECK-32-O0-NEXT: vmr 3, 2
1360 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1361 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 7
1362 ; CHECK-32-O0-NEXT: blr
1363 entry:
1364 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1365 ret <16 x i8> %vecins
1366 }
1368 define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) {
1369 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_24_0:
1370 ; CHECK-64-OPT: # %bb.0: # %entry
1371 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 9
1372 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 8
1373 ; CHECK-64-OPT-NEXT: vmr 2, 3
1374 ; CHECK-64-OPT-NEXT: blr
1375 ;
1376 ; CHECK-64-O0-LABEL: shuffle_vector_byte_24_0:
1377 ; CHECK-64-O0: # %bb.0: # %entry
1378 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1379 ; CHECK-64-O0-NEXT: vmr 3, 2
1380 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1381 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 9
1382 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 8
1383 ; CHECK-64-O0-NEXT: blr
1384 ;
1385 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_24_0:
1386 ; CHECK-32-OPT: # %bb.0: # %entry
1387 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 9
1388 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 8
1389 ; CHECK-32-OPT-NEXT: vmr 2, 3
1390 ; CHECK-32-OPT-NEXT: blr
1391 ;
1392 ; CHECK-32-O0-LABEL: shuffle_vector_byte_24_0:
1393 ; CHECK-32-O0: # %bb.0: # %entry
1394 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1395 ; CHECK-32-O0-NEXT: vmr 3, 2
1396 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1397 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 9
1398 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 8
1399 ; CHECK-32-O0-NEXT: blr
1400 entry:
1401 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1402 ret <16 x i8> %vecins
1403 }
1405 define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) {
1406 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_25_9:
1407 ; CHECK-64-OPT: # %bb.0: # %entry
1408 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 2
1409 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 9
1410 ; CHECK-64-OPT-NEXT: vmr 2, 3
1411 ; CHECK-64-OPT-NEXT: blr
1412 ;
1413 ; CHECK-64-O0-LABEL: shuffle_vector_byte_25_9:
1414 ; CHECK-64-O0: # %bb.0: # %entry
1415 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1416 ; CHECK-64-O0-NEXT: vmr 3, 2
1417 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1418 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 2
1419 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 9
1420 ; CHECK-64-O0-NEXT: blr
1421 ;
1422 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_25_9:
1423 ; CHECK-32-OPT: # %bb.0: # %entry
1424 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 2
1425 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 9
1426 ; CHECK-32-OPT-NEXT: vmr 2, 3
1427 ; CHECK-32-OPT-NEXT: blr
1428 ;
1429 ; CHECK-32-O0-LABEL: shuffle_vector_byte_25_9:
1430 ; CHECK-32-O0: # %bb.0: # %entry
1431 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1432 ; CHECK-32-O0-NEXT: vmr 3, 2
1433 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1434 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 2
1435 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 9
1436 ; CHECK-32-O0-NEXT: blr
1437 entry:
1438 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1439 ret <16 x i8> %vecins
1440 }
1442 define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) {
1443 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_26_2:
1444 ; CHECK-64-OPT: # %bb.0: # %entry
1445 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 11
1446 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 10
1447 ; CHECK-64-OPT-NEXT: vmr 2, 3
1448 ; CHECK-64-OPT-NEXT: blr
1449 ;
1450 ; CHECK-64-O0-LABEL: shuffle_vector_byte_26_2:
1451 ; CHECK-64-O0: # %bb.0: # %entry
1452 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1453 ; CHECK-64-O0-NEXT: vmr 3, 2
1454 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1455 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 11
1456 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 10
1457 ; CHECK-64-O0-NEXT: blr
1458 ;
1459 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_26_2:
1460 ; CHECK-32-OPT: # %bb.0: # %entry
1461 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 11
1462 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 10
1463 ; CHECK-32-OPT-NEXT: vmr 2, 3
1464 ; CHECK-32-OPT-NEXT: blr
1465 ;
1466 ; CHECK-32-O0-LABEL: shuffle_vector_byte_26_2:
1467 ; CHECK-32-O0: # %bb.0: # %entry
1468 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1469 ; CHECK-32-O0-NEXT: vmr 3, 2
1470 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1471 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 11
1472 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 10
1473 ; CHECK-32-O0-NEXT: blr
1474 entry:
1475 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31>
1476 ret <16 x i8> %vecins
1477 }
1479 define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) {
1480 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_27_11:
1481 ; CHECK-64-OPT: # %bb.0: # %entry
1482 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 4
1483 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 11
1484 ; CHECK-64-OPT-NEXT: vmr 2, 3
1485 ; CHECK-64-OPT-NEXT: blr
1486 ;
1487 ; CHECK-64-O0-LABEL: shuffle_vector_byte_27_11:
1488 ; CHECK-64-O0: # %bb.0: # %entry
1489 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1490 ; CHECK-64-O0-NEXT: vmr 3, 2
1491 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1492 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 4
1493 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 11
1494 ; CHECK-64-O0-NEXT: blr
1495 ;
1496 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_27_11:
1497 ; CHECK-32-OPT: # %bb.0: # %entry
1498 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 4
1499 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 11
1500 ; CHECK-32-OPT-NEXT: vmr 2, 3
1501 ; CHECK-32-OPT-NEXT: blr
1502 ;
1503 ; CHECK-32-O0-LABEL: shuffle_vector_byte_27_11:
1504 ; CHECK-32-O0: # %bb.0: # %entry
1505 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1506 ; CHECK-32-O0-NEXT: vmr 3, 2
1507 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1508 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 4
1509 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 11
1510 ; CHECK-32-O0-NEXT: blr
1511 entry:
1512 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31>
1513 ret <16 x i8> %vecins
1514 }
1516 define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) {
1517 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_28_4:
1518 ; CHECK-64-OPT: # %bb.0: # %entry
1519 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 13
1520 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 12
1521 ; CHECK-64-OPT-NEXT: vmr 2, 3
1522 ; CHECK-64-OPT-NEXT: blr
1523 ;
1524 ; CHECK-64-O0-LABEL: shuffle_vector_byte_28_4:
1525 ; CHECK-64-O0: # %bb.0: # %entry
1526 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1527 ; CHECK-64-O0-NEXT: vmr 3, 2
1528 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1529 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 13
1530 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 12
1531 ; CHECK-64-O0-NEXT: blr
1532 ;
1533 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_28_4:
1534 ; CHECK-32-OPT: # %bb.0: # %entry
1535 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 13
1536 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 12
1537 ; CHECK-32-OPT-NEXT: vmr 2, 3
1538 ; CHECK-32-OPT-NEXT: blr
1539 ;
1540 ; CHECK-32-O0-LABEL: shuffle_vector_byte_28_4:
1541 ; CHECK-32-O0: # %bb.0: # %entry
1542 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1543 ; CHECK-32-O0-NEXT: vmr 3, 2
1544 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1545 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 13
1546 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 12
1547 ; CHECK-32-O0-NEXT: blr
1548 entry:
1549 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31>
1550 ret <16 x i8> %vecins
1551 }
1553 define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) {
1554 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_29_13:
1555 ; CHECK-64-OPT: # %bb.0: # %entry
1556 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 6
1557 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 13
1558 ; CHECK-64-OPT-NEXT: vmr 2, 3
1559 ; CHECK-64-OPT-NEXT: blr
1560 ;
1561 ; CHECK-64-O0-LABEL: shuffle_vector_byte_29_13:
1562 ; CHECK-64-O0: # %bb.0: # %entry
1563 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1564 ; CHECK-64-O0-NEXT: vmr 3, 2
1565 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1566 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 6
1567 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 13
1568 ; CHECK-64-O0-NEXT: blr
1569 ;
1570 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_29_13:
1571 ; CHECK-32-OPT: # %bb.0: # %entry
1572 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 6
1573 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 13
1574 ; CHECK-32-OPT-NEXT: vmr 2, 3
1575 ; CHECK-32-OPT-NEXT: blr
1576 ;
1577 ; CHECK-32-O0-LABEL: shuffle_vector_byte_29_13:
1578 ; CHECK-32-O0: # %bb.0: # %entry
1579 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1580 ; CHECK-32-O0-NEXT: vmr 3, 2
1581 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1582 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 6
1583 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 13
1584 ; CHECK-32-O0-NEXT: blr
1585 entry:
1586 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31>
1587 ret <16 x i8> %vecins
1588 }
1590 define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) {
1591 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_30_6:
1592 ; CHECK-64-OPT: # %bb.0: # %entry
1593 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 15
1594 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 14
1595 ; CHECK-64-OPT-NEXT: vmr 2, 3
1596 ; CHECK-64-OPT-NEXT: blr
1597 ;
1598 ; CHECK-64-O0-LABEL: shuffle_vector_byte_30_6:
1599 ; CHECK-64-O0: # %bb.0: # %entry
1600 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1601 ; CHECK-64-O0-NEXT: vmr 3, 2
1602 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1603 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 15
1604 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 14
1605 ; CHECK-64-O0-NEXT: blr
1606 ;
1607 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_30_6:
1608 ; CHECK-32-OPT: # %bb.0: # %entry
1609 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 15
1610 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 14
1611 ; CHECK-32-OPT-NEXT: vmr 2, 3
1612 ; CHECK-32-OPT-NEXT: blr
1613 ;
1614 ; CHECK-32-O0-LABEL: shuffle_vector_byte_30_6:
1615 ; CHECK-32-O0: # %bb.0: # %entry
1616 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1617 ; CHECK-32-O0-NEXT: vmr 3, 2
1618 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1619 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 15
1620 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 14
1621 ; CHECK-32-O0-NEXT: blr
1622 entry:
1623 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31>
1624 ret <16 x i8> %vecins
1625 }
1627 define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) {
1628 ; CHECK-64-OPT-LABEL: shuffle_vector_byte_31_15:
1629 ; CHECK-64-OPT: # %bb.0: # %entry
1630 ; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 8
1631 ; CHECK-64-OPT-NEXT: vinsertb 3, 2, 15
1632 ; CHECK-64-OPT-NEXT: vmr 2, 3
1633 ; CHECK-64-OPT-NEXT: blr
1634 ;
1635 ; CHECK-64-O0-LABEL: shuffle_vector_byte_31_15:
1636 ; CHECK-64-O0: # %bb.0: # %entry
1637 ; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1638 ; CHECK-64-O0-NEXT: vmr 3, 2
1639 ; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1640 ; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 8
1641 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 15
1642 ; CHECK-64-O0-NEXT: blr
1643 ;
1644 ; CHECK-32-OPT-LABEL: shuffle_vector_byte_31_15:
1645 ; CHECK-32-OPT: # %bb.0: # %entry
1646 ; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 8
1647 ; CHECK-32-OPT-NEXT: vinsertb 3, 2, 15
1648 ; CHECK-32-OPT-NEXT: vmr 2, 3
1649 ; CHECK-32-OPT-NEXT: blr
1650 ;
1651 ; CHECK-32-O0-LABEL: shuffle_vector_byte_31_15:
1652 ; CHECK-32-O0: # %bb.0: # %entry
1653 ; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1654 ; CHECK-32-O0-NEXT: vmr 3, 2
1655 ; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1656 ; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 8
1657 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 15
1658 ; CHECK-32-O0-NEXT: blr
1659 entry:
1660 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>
1661 ret <16 x i8> %vecins
1662 }
1664 ; The following testcases use the same vector in both arguments of the
1665 ; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one
1666 ; we're attempting to insert, then we can use the vector insert instruction
1667 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
1668 ; CHECK: # %bb.0: # %entry
1669 ; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha
1670 ; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l
1671 ; CHECK-NEXT: lxvx 35, 0, 3
1672 ; CHECK-NEXT: vperm 2, 2, 2, 3
1673 ; CHECK-NEXT: blr
1674 ; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
1675 ; CHECK-BE: # %bb.0: # %entry
1676 ; CHECK-BE-NEXT: vinsertb 2, 2, 0
1677 ; CHECK-BE-NEXT: blr
1678 ; CHECK-64-LABEL: shuffle_vector_byte_0_7:
1679 ; CHECK-64: # %bb.0: # %entry
1680 ; CHECK-64-NEXT: vinsertb 2, 2, 0
1681 ; CHECK-64-NEXT: blr
1682 ;
1683 ; CHECK-32-LABEL: shuffle_vector_byte_0_7:
1684 ; CHECK-32: # %bb.0: # %entry
1685 ; CHECK-32-NEXT: vinsertb 2, 2, 0
1686 ; CHECK-32-NEXT: blr
1687 entry:
1688 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1689 ret <16 x i8> %vecins
1690 }
1692 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
1693 ; CHECK: # %bb.0: # %entry
1694 ; CHECK-NEXT: vinsertb 2, 2, 14
1695 ; CHECK-NEXT: blr
1696 ; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
1697 ; CHECK-BE: # %bb.0: # %entry
1698 ; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha
1699 ; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l
1700 ; CHECK-BE-NEXT: lxvx 35, 0, 3
1701 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
1702 ; CHECK-BE-NEXT: blr
1703 ; CHECK-64-LABEL: shuffle_vector_byte_1_8:
1704 ; CHECK-64: # %bb.0: # %entry
1705 ; CHECK-64-NEXT: ld 3, L..C4(2)
1706 ; CHECK-64-NEXT: lxv 35, 0(3)
1707 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
1708 ; CHECK-64-NEXT: blr
1709 ;
1710 ; CHECK-32-LABEL: shuffle_vector_byte_1_8:
1711 ; CHECK-32: # %bb.0: # %entry
1712 ; CHECK-32-NEXT: lwz 3, L..C4(2)
1713 ; CHECK-32-NEXT: lxv 35, 0(3)
1714 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
1715 ; CHECK-32-NEXT: blr
1716 entry:
1717 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1718 ret <16 x i8> %vecins
1719 }
1721 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
1722 ; CHECK: # %bb.0: # %entry
1723 ; CHECK-NEXT: vinsertb 2, 2, 13
1724 ; CHECK-NEXT: blr
1725 ; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
1726 ; CHECK-BE: # %bb.0: # %entry
1727 ; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha
1728 ; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l
1729 ; CHECK-BE-NEXT: lxvx 35, 0, 3
1730 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
1731 ; CHECK-BE-NEXT: blr
1732 ; CHECK-64-LABEL: shuffle_vector_byte_2_8:
1733 ; CHECK-64: # %bb.0: # %entry
1734 ; CHECK-64-NEXT: ld 3, L..C5(2)
1735 ; CHECK-64-NEXT: lxv 35, 0(3)
1736 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
1737 ; CHECK-64-NEXT: blr
1738 ;
1739 ; CHECK-32-LABEL: shuffle_vector_byte_2_8:
1740 ; CHECK-32: # %bb.0: # %entry
1741 ; CHECK-32-NEXT: lwz 3, L..C5(2)
1742 ; CHECK-32-NEXT: lxv 35, 0(3)
1743 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
1744 ; CHECK-32-NEXT: blr
1745 entry:
1746 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1747 ret <16 x i8> %vecins
1748 }
1750 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
1751 ; CHECK: # %bb.0: # %entry
1752 ; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha
1753 ; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l
1754 ; CHECK-NEXT: lxvx 35, 0, 3
1755 ; CHECK-NEXT: vperm 2, 2, 2, 3
1756 ; CHECK-NEXT: blr
1757 ; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
1758 ; CHECK-BE: # %bb.0: # %entry
1759 ; CHECK-BE-NEXT: vinsertb 2, 2, 3
1760 ; CHECK-BE-NEXT: blr
1761 ; CHECK-64-LABEL: shuffle_vector_byte_3_7:
1762 ; CHECK-64: # %bb.0: # %entry
1763 ; CHECK-64-NEXT: vinsertb 2, 2, 3
1764 ; CHECK-64-NEXT: blr
1765 ;
1766 ; CHECK-32-LABEL: shuffle_vector_byte_3_7:
1767 ; CHECK-32: # %bb.0: # %entry
1768 ; CHECK-32-NEXT: vinsertb 2, 2, 3
1769 ; CHECK-32-NEXT: blr
1770 entry:
1771 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1772 ret <16 x i8> %vecins
1773 }
1775 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
1776 ; CHECK: # %bb.0: # %entry
1777 ; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha
1778 ; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l
1779 ; CHECK-NEXT: lxvx 35, 0, 3
1780 ; CHECK-NEXT: vperm 2, 2, 2, 3
1781 ; CHECK-NEXT: blr
1782 ; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
1783 ; CHECK-BE: # %bb.0: # %entry
1784 ; CHECK-BE-NEXT: vinsertb 2, 2, 4
1785 ; CHECK-BE-NEXT: blr
1786 ; CHECK-64-LABEL: shuffle_vector_byte_4_7:
1787 ; CHECK-64: # %bb.0: # %entry
1788 ; CHECK-64-NEXT: vinsertb 2, 2, 4
1789 ; CHECK-64-NEXT: blr
1790 ;
1791 ; CHECK-32-LABEL: shuffle_vector_byte_4_7:
1792 ; CHECK-32: # %bb.0: # %entry
1793 ; CHECK-32-NEXT: vinsertb 2, 2, 4
1794 ; CHECK-32-NEXT: blr
1795 entry:
1796 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1797 ret <16 x i8> %vecins
1798 }
1800 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
1801 ; CHECK: # %bb.0: # %entry
1802 ; CHECK-NEXT: vinsertb 2, 2, 10
1803 ; CHECK-NEXT: blr
1804 ; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
1805 ; CHECK-BE: # %bb.0: # %entry
1806 ; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha
1807 ; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l
1808 ; CHECK-BE-NEXT: lxvx 35, 0, 3
1809 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
1810 ; CHECK-BE-NEXT: blr
1811 ; CHECK-64-LABEL: shuffle_vector_byte_5_8:
1812 ; CHECK-64: # %bb.0: # %entry
1813 ; CHECK-64-NEXT: ld 3, L..C6(2)
1814 ; CHECK-64-NEXT: lxv 35, 0(3)
1815 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
1816 ; CHECK-64-NEXT: blr
1817 ;
1818 ; CHECK-32-LABEL: shuffle_vector_byte_5_8:
1819 ; CHECK-32: # %bb.0: # %entry
1820 ; CHECK-32-NEXT: lwz 3, L..C6(2)
1821 ; CHECK-32-NEXT: lxv 35, 0(3)
1822 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
1823 ; CHECK-32-NEXT: blr
1824 entry:
1825 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1826 ret <16 x i8> %vecins
1827 }
1829 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
1830 ; CHECK: # %bb.0: # %entry
1831 ; CHECK-NEXT: vinsertb 2, 2, 9
1832 ; CHECK-NEXT: blr
1833 ; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
1834 ; CHECK-BE: # %bb.0: # %entry
1835 ; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha
1836 ; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l
1837 ; CHECK-BE-NEXT: lxvx 35, 0, 3
1838 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
1839 ; CHECK-BE-NEXT: blr
1840 ; CHECK-64-LABEL: shuffle_vector_byte_6_8:
1841 ; CHECK-64: # %bb.0: # %entry
1842 ; CHECK-64-NEXT: ld 3, L..C7(2)
1843 ; CHECK-64-NEXT: lxv 35, 0(3)
1844 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
1845 ; CHECK-64-NEXT: blr
1846 ;
1847 ; CHECK-32-LABEL: shuffle_vector_byte_6_8:
1848 ; CHECK-32: # %bb.0: # %entry
1849 ; CHECK-32-NEXT: lwz 3, L..C7(2)
1850 ; CHECK-32-NEXT: lxv 35, 0(3)
1851 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
1852 ; CHECK-32-NEXT: blr
1853 entry:
1854 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1855 ret <16 x i8> %vecins
1856 }
1858 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
1859 ; CHECK: # %bb.0: # %entry
1860 ; CHECK-NEXT: vinsertb 2, 2, 8
1861 ; CHECK-NEXT: blr
1862 ; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
1863 ; CHECK-BE: # %bb.0: # %entry
1864 ; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha
1865 ; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l
1866 ; CHECK-BE-NEXT: lxvx 35, 0, 3
1867 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
1868 ; CHECK-BE-NEXT: blr
1869 ; CHECK-64-LABEL: shuffle_vector_byte_7_8:
1870 ; CHECK-64: # %bb.0: # %entry
1871 ; CHECK-64-NEXT: ld 3, L..C8(2)
1872 ; CHECK-64-NEXT: lxv 35, 0(3)
1873 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
1874 ; CHECK-64-NEXT: blr
1875 ;
1876 ; CHECK-32-LABEL: shuffle_vector_byte_7_8:
1877 ; CHECK-32: # %bb.0: # %entry
1878 ; CHECK-32-NEXT: lwz 3, L..C8(2)
1879 ; CHECK-32-NEXT: lxv 35, 0(3)
1880 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
1881 ; CHECK-32-NEXT: blr
1882 entry:
1883 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1884 ret <16 x i8> %vecins
1885 }
1887 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
1888 ; CHECK: # %bb.0: # %entry
1889 ; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha
1890 ; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l
1891 ; CHECK-NEXT: lxvx 35, 0, 3
1892 ; CHECK-NEXT: vperm 2, 2, 2, 3
1893 ; CHECK-NEXT: blr
1894 ; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
1895 ; CHECK-BE: # %bb.0: # %entry
1896 ; CHECK-BE-NEXT: vinsertb 2, 2, 8
1897 ; CHECK-BE-NEXT: blr
1898 ; CHECK-64-LABEL: shuffle_vector_byte_8_7:
1899 ; CHECK-64: # %bb.0: # %entry
1900 ; CHECK-64-NEXT: vinsertb 2, 2, 8
1901 ; CHECK-64-NEXT: blr
1902 ;
1903 ; CHECK-32-LABEL: shuffle_vector_byte_8_7:
1904 ; CHECK-32: # %bb.0: # %entry
1905 ; CHECK-32-NEXT: vinsertb 2, 2, 8
1906 ; CHECK-32-NEXT: blr
1907 entry:
1908 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1909 ret <16 x i8> %vecins
1910 }
1912 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
1913 ; CHECK: # %bb.0: # %entry
1914 ; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha
1915 ; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l
1916 ; CHECK-NEXT: lxvx 35, 0, 3
1917 ; CHECK-NEXT: vperm 2, 2, 2, 3
1918 ; CHECK-NEXT: blr
1919 ; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
1920 ; CHECK-BE: # %bb.0: # %entry
1921 ; CHECK-BE-NEXT: vinsertb 2, 2, 9
1922 ; CHECK-BE-NEXT: blr
1923 ; CHECK-64-LABEL: shuffle_vector_byte_9_7:
1924 ; CHECK-64: # %bb.0: # %entry
1925 ; CHECK-64-NEXT: vinsertb 2, 2, 9
1926 ; CHECK-64-NEXT: blr
1927 ;
1928 ; CHECK-32-LABEL: shuffle_vector_byte_9_7:
1929 ; CHECK-32: # %bb.0: # %entry
1930 ; CHECK-32-NEXT: vinsertb 2, 2, 9
1931 ; CHECK-32-NEXT: blr
1932 entry:
1933 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1934 ret <16 x i8> %vecins
1935 }
1937 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
1938 ; CHECK: # %bb.0: # %entry
1939 ; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha
1940 ; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l
1941 ; CHECK-NEXT: lxvx 35, 0, 3
1942 ; CHECK-NEXT: vperm 2, 2, 2, 3
1943 ; CHECK-NEXT: blr
1944 ; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
1945 ; CHECK-BE: # %bb.0: # %entry
1946 ; CHECK-BE-NEXT: vinsertb 2, 2, 10
1947 ; CHECK-BE-NEXT: blr
1948 ; CHECK-64-LABEL: shuffle_vector_byte_10_7:
1949 ; CHECK-64: # %bb.0: # %entry
1950 ; CHECK-64-NEXT: vinsertb 2, 2, 10
1951 ; CHECK-64-NEXT: blr
1952 ;
1953 ; CHECK-32-LABEL: shuffle_vector_byte_10_7:
1954 ; CHECK-32: # %bb.0: # %entry
1955 ; CHECK-32-NEXT: vinsertb 2, 2, 10
1956 ; CHECK-32-NEXT: blr
1957 entry:
1958 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
1959 ret <16 x i8> %vecins
1960 }
1962 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
1963 ; CHECK: # %bb.0: # %entry
1964 ; CHECK-NEXT: vinsertb 2, 2, 4
1965 ; CHECK-NEXT: blr
1966 ; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
1967 ; CHECK-BE: # %bb.0: # %entry
1968 ; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha
1969 ; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l
1970 ; CHECK-BE-NEXT: lxvx 35, 0, 3
1971 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
1972 ; CHECK-BE-NEXT: blr
1973 ; CHECK-64-LABEL: shuffle_vector_byte_11_8:
1974 ; CHECK-64: # %bb.0: # %entry
1975 ; CHECK-64-NEXT: ld 3, L..C9(2)
1976 ; CHECK-64-NEXT: lxv 35, 0(3)
1977 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
1978 ; CHECK-64-NEXT: blr
1979 ;
1980 ; CHECK-32-LABEL: shuffle_vector_byte_11_8:
1981 ; CHECK-32: # %bb.0: # %entry
1982 ; CHECK-32-NEXT: lwz 3, L..C9(2)
1983 ; CHECK-32-NEXT: lxv 35, 0(3)
1984 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
1985 ; CHECK-32-NEXT: blr
1986 entry:
1987 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
1988 ret <16 x i8> %vecins
1989 }
1991 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
1992 ; CHECK: # %bb.0: # %entry
1993 ; CHECK-NEXT: vinsertb 2, 2, 3
1994 ; CHECK-NEXT: blr
1995 ; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
1996 ; CHECK-BE: # %bb.0: # %entry
1997 ; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha
1998 ; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l
1999 ; CHECK-BE-NEXT: lxvx 35, 0, 3
2000 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
2001 ; CHECK-BE-NEXT: blr
2002 ; CHECK-64-LABEL: shuffle_vector_byte_12_8:
2003 ; CHECK-64: # %bb.0: # %entry
2004 ; CHECK-64-NEXT: ld 3, L..C10(2)
2005 ; CHECK-64-NEXT: lxv 35, 0(3)
2006 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
2007 ; CHECK-64-NEXT: blr
2008 ;
2009 ; CHECK-32-LABEL: shuffle_vector_byte_12_8:
2010 ; CHECK-32: # %bb.0: # %entry
2011 ; CHECK-32-NEXT: lwz 3, L..C10(2)
2012 ; CHECK-32-NEXT: lxv 35, 0(3)
2013 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
2014 ; CHECK-32-NEXT: blr
2015 entry:
2016 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
2017 ret <16 x i8> %vecins
2018 }
2020 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
2021 ; CHECK: # %bb.0: # %entry
2022 ; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha
2023 ; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l
2024 ; CHECK-NEXT: lxvx 35, 0, 3
2025 ; CHECK-NEXT: vperm 2, 2, 2, 3
2026 ; CHECK-NEXT: blr
2027 ; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
2028 ; CHECK-BE: # %bb.0: # %entry
2029 ; CHECK-BE-NEXT: vinsertb 2, 2, 13
2030 ; CHECK-BE-NEXT: blr
2031 ; CHECK-64-LABEL: shuffle_vector_byte_13_7:
2032 ; CHECK-64: # %bb.0: # %entry
2033 ; CHECK-64-NEXT: vinsertb 2, 2, 13
2034 ; CHECK-64-NEXT: blr
2035 ;
2036 ; CHECK-32-LABEL: shuffle_vector_byte_13_7:
2037 ; CHECK-32: # %bb.0: # %entry
2038 ; CHECK-32-NEXT: vinsertb 2, 2, 13
2039 ; CHECK-32-NEXT: blr
2040 entry:
2041 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
2042 ret <16 x i8> %vecins
2043 }
2045 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
2046 ; CHECK: # %bb.0: # %entry
2047 ; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha
2048 ; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l
2049 ; CHECK-NEXT: lxvx 35, 0, 3
2050 ; CHECK-NEXT: vperm 2, 2, 2, 3
2051 ; CHECK-NEXT: blr
2052 ; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
2053 ; CHECK-BE: # %bb.0: # %entry
2054 ; CHECK-BE-NEXT: vinsertb 2, 2, 14
2055 ; CHECK-BE-NEXT: blr
2056 ; CHECK-64-LABEL: shuffle_vector_byte_14_7:
2057 ; CHECK-64: # %bb.0: # %entry
2058 ; CHECK-64-NEXT: vinsertb 2, 2, 14
2059 ; CHECK-64-NEXT: blr
2060 ;
2061 ; CHECK-32-LABEL: shuffle_vector_byte_14_7:
2062 ; CHECK-32: # %bb.0: # %entry
2063 ; CHECK-32-NEXT: vinsertb 2, 2, 14
2064 ; CHECK-32-NEXT: blr
2065 entry:
2066 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
2067 ret <16 x i8> %vecins
2068 }
2070 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
2071 ; CHECK: # %bb.0: # %entry
2072 ; CHECK-NEXT: vinsertb 2, 2, 0
2073 ; CHECK-NEXT: blr
2074 ; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
2075 ; CHECK-BE: # %bb.0: # %entry
2076 ; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha
2077 ; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l
2078 ; CHECK-BE-NEXT: lxvx 35, 0, 3
2079 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
2080 ; CHECK-BE-NEXT: blr
2081 ; CHECK-64-LABEL: shuffle_vector_byte_15_8:
2082 ; CHECK-64: # %bb.0: # %entry
2083 ; CHECK-64-NEXT: ld 3, L..C11(2)
2084 ; CHECK-64-NEXT: lxv 35, 0(3)
2085 ; CHECK-64-NEXT: vperm 2, 2, 2, 3
2086 ; CHECK-64-NEXT: blr
2087 ;
2088 ; CHECK-32-LABEL: shuffle_vector_byte_15_8:
2089 ; CHECK-32: # %bb.0: # %entry
2090 ; CHECK-32-NEXT: lwz 3, L..C11(2)
2091 ; CHECK-32-NEXT: lxv 35, 0(3)
2092 ; CHECK-32-NEXT: vperm 2, 2, 2, 3
2093 ; CHECK-32-NEXT: blr
2094 entry:
2095 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
2096 ret <16 x i8> %vecins
2097 }
2099 ; The following tests try to insert one halfword element into the vector. We
2100 ; should always be using the 'vinserth' instruction.
2101 define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) {
2102 ; CHECK-64-OPT-LABEL: insert_halfword_0:
2103 ; CHECK-64-OPT: # %bb.0: # %entry
2104 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2105 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 0
2106 ; CHECK-64-OPT-NEXT: blr
2107 ;
2108 ; CHECK-64-O0-LABEL: insert_halfword_0:
2109 ; CHECK-64-O0: # %bb.0: # %entry
2110 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2111 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2112 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2113 ; CHECK-64-O0-NEXT: vinserth 2, 3, 0
2114 ; CHECK-64-O0-NEXT: blr
2115 ;
2116 ; CHECK-32-OPT-LABEL: insert_halfword_0:
2117 ; CHECK-32-OPT: # %bb.0: # %entry
2118 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2119 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 0
2120 ; CHECK-32-OPT-NEXT: blr
2121 ;
2122 ; CHECK-32-O0-LABEL: insert_halfword_0:
2123 ; CHECK-32-O0: # %bb.0: # %entry
2124 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2125 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2126 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2127 ; CHECK-32-O0-NEXT: vinserth 2, 3, 0
2128 ; CHECK-32-O0-NEXT: blr
2129 entry:
2130 %vecins = insertelement <8 x i16> %a, i16 %b, i32 0
2131 ret <8 x i16> %vecins
2132 }
2134 define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) {
2135 ; CHECK-64-OPT-LABEL: insert_halfword_1:
2136 ; CHECK-64-OPT: # %bb.0: # %entry
2137 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2138 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 2
2139 ; CHECK-64-OPT-NEXT: blr
2140 ;
2141 ; CHECK-64-O0-LABEL: insert_halfword_1:
2142 ; CHECK-64-O0: # %bb.0: # %entry
2143 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2144 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2145 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2146 ; CHECK-64-O0-NEXT: vinserth 2, 3, 2
2147 ; CHECK-64-O0-NEXT: blr
2148 ;
2149 ; CHECK-32-OPT-LABEL: insert_halfword_1:
2150 ; CHECK-32-OPT: # %bb.0: # %entry
2151 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2152 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 2
2153 ; CHECK-32-OPT-NEXT: blr
2154 ;
2155 ; CHECK-32-O0-LABEL: insert_halfword_1:
2156 ; CHECK-32-O0: # %bb.0: # %entry
2157 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2158 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2159 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2160 ; CHECK-32-O0-NEXT: vinserth 2, 3, 2
2161 ; CHECK-32-O0-NEXT: blr
2162 entry:
2163 %vecins = insertelement <8 x i16> %a, i16 %b, i32 1
2164 ret <8 x i16> %vecins
2165 }
2167 define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) {
2168 ; CHECK-64-OPT-LABEL: insert_halfword_2:
2169 ; CHECK-64-OPT: # %bb.0: # %entry
2170 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2171 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 4
2172 ; CHECK-64-OPT-NEXT: blr
2173 ;
2174 ; CHECK-64-O0-LABEL: insert_halfword_2:
2175 ; CHECK-64-O0: # %bb.0: # %entry
2176 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2177 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2178 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2179 ; CHECK-64-O0-NEXT: vinserth 2, 3, 4
2180 ; CHECK-64-O0-NEXT: blr
2181 ;
2182 ; CHECK-32-OPT-LABEL: insert_halfword_2:
2183 ; CHECK-32-OPT: # %bb.0: # %entry
2184 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2185 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 4
2186 ; CHECK-32-OPT-NEXT: blr
2187 ;
2188 ; CHECK-32-O0-LABEL: insert_halfword_2:
2189 ; CHECK-32-O0: # %bb.0: # %entry
2190 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2191 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2192 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2193 ; CHECK-32-O0-NEXT: vinserth 2, 3, 4
2194 ; CHECK-32-O0-NEXT: blr
2195 entry:
2196 %vecins = insertelement <8 x i16> %a, i16 %b, i32 2
2197 ret <8 x i16> %vecins
2198 }
2200 define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) {
2201 ; CHECK-64-OPT-LABEL: insert_halfword_3:
2202 ; CHECK-64-OPT: # %bb.0: # %entry
2203 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2204 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 6
2205 ; CHECK-64-OPT-NEXT: blr
2206 ;
2207 ; CHECK-64-O0-LABEL: insert_halfword_3:
2208 ; CHECK-64-O0: # %bb.0: # %entry
2209 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2210 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2211 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2212 ; CHECK-64-O0-NEXT: vinserth 2, 3, 6
2213 ; CHECK-64-O0-NEXT: blr
2214 ;
2215 ; CHECK-32-OPT-LABEL: insert_halfword_3:
2216 ; CHECK-32-OPT: # %bb.0: # %entry
2217 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2218 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 6
2219 ; CHECK-32-OPT-NEXT: blr
2220 ;
2221 ; CHECK-32-O0-LABEL: insert_halfword_3:
2222 ; CHECK-32-O0: # %bb.0: # %entry
2223 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2224 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2225 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2226 ; CHECK-32-O0-NEXT: vinserth 2, 3, 6
2227 ; CHECK-32-O0-NEXT: blr
2228 entry:
2229 %vecins = insertelement <8 x i16> %a, i16 %b, i32 3
2230 ret <8 x i16> %vecins
2231 }
2233 define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) {
2234 ; CHECK-64-OPT-LABEL: insert_halfword_4:
2235 ; CHECK-64-OPT: # %bb.0: # %entry
2236 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2237 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 8
2238 ; CHECK-64-OPT-NEXT: blr
2239 ;
2240 ; CHECK-64-O0-LABEL: insert_halfword_4:
2241 ; CHECK-64-O0: # %bb.0: # %entry
2242 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2243 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2244 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2245 ; CHECK-64-O0-NEXT: vinserth 2, 3, 8
2246 ; CHECK-64-O0-NEXT: blr
2247 ;
2248 ; CHECK-32-OPT-LABEL: insert_halfword_4:
2249 ; CHECK-32-OPT: # %bb.0: # %entry
2250 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2251 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 8
2252 ; CHECK-32-OPT-NEXT: blr
2253 ;
2254 ; CHECK-32-O0-LABEL: insert_halfword_4:
2255 ; CHECK-32-O0: # %bb.0: # %entry
2256 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2257 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2258 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2259 ; CHECK-32-O0-NEXT: vinserth 2, 3, 8
2260 ; CHECK-32-O0-NEXT: blr
2261 entry:
2262 %vecins = insertelement <8 x i16> %a, i16 %b, i32 4
2263 ret <8 x i16> %vecins
2264 }
2266 define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) {
2267 ; CHECK-64-OPT-LABEL: insert_halfword_5:
2268 ; CHECK-64-OPT: # %bb.0: # %entry
2269 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2270 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 10
2271 ; CHECK-64-OPT-NEXT: blr
2272 ;
2273 ; CHECK-64-O0-LABEL: insert_halfword_5:
2274 ; CHECK-64-O0: # %bb.0: # %entry
2275 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2276 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2277 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2278 ; CHECK-64-O0-NEXT: vinserth 2, 3, 10
2279 ; CHECK-64-O0-NEXT: blr
2280 ;
2281 ; CHECK-32-OPT-LABEL: insert_halfword_5:
2282 ; CHECK-32-OPT: # %bb.0: # %entry
2283 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2284 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 10
2285 ; CHECK-32-OPT-NEXT: blr
2286 ;
2287 ; CHECK-32-O0-LABEL: insert_halfword_5:
2288 ; CHECK-32-O0: # %bb.0: # %entry
2289 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2290 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2291 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2292 ; CHECK-32-O0-NEXT: vinserth 2, 3, 10
2293 ; CHECK-32-O0-NEXT: blr
2294 entry:
2295 %vecins = insertelement <8 x i16> %a, i16 %b, i32 5
2296 ret <8 x i16> %vecins
2297 }
2299 define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) {
2300 ; CHECK-64-OPT-LABEL: insert_halfword_6:
2301 ; CHECK-64-OPT: # %bb.0: # %entry
2302 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2303 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 12
2304 ; CHECK-64-OPT-NEXT: blr
2305 ;
2306 ; CHECK-64-O0-LABEL: insert_halfword_6:
2307 ; CHECK-64-O0: # %bb.0: # %entry
2308 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2309 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2310 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2311 ; CHECK-64-O0-NEXT: vinserth 2, 3, 12
2312 ; CHECK-64-O0-NEXT: blr
2313 ;
2314 ; CHECK-32-OPT-LABEL: insert_halfword_6:
2315 ; CHECK-32-OPT: # %bb.0: # %entry
2316 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2317 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 12
2318 ; CHECK-32-OPT-NEXT: blr
2319 ;
2320 ; CHECK-32-O0-LABEL: insert_halfword_6:
2321 ; CHECK-32-O0: # %bb.0: # %entry
2322 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2323 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2324 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2325 ; CHECK-32-O0-NEXT: vinserth 2, 3, 12
2326 ; CHECK-32-O0-NEXT: blr
2327 entry:
2328 %vecins = insertelement <8 x i16> %a, i16 %b, i32 6
2329 ret <8 x i16> %vecins
2330 }
2332 define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) {
2333 ; CHECK-64-OPT-LABEL: insert_halfword_7:
2334 ; CHECK-64-OPT: # %bb.0: # %entry
2335 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2336 ; CHECK-64-OPT-NEXT: vinserth 2, 3, 14
2337 ; CHECK-64-OPT-NEXT: blr
2338 ;
2339 ; CHECK-64-O0-LABEL: insert_halfword_7:
2340 ; CHECK-64-O0: # %bb.0: # %entry
2341 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2342 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2343 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2344 ; CHECK-64-O0-NEXT: vinserth 2, 3, 14
2345 ; CHECK-64-O0-NEXT: blr
2346 ;
2347 ; CHECK-32-OPT-LABEL: insert_halfword_7:
2348 ; CHECK-32-OPT: # %bb.0: # %entry
2349 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2350 ; CHECK-32-OPT-NEXT: vinserth 2, 3, 14
2351 ; CHECK-32-OPT-NEXT: blr
2352 ;
2353 ; CHECK-32-O0-LABEL: insert_halfword_7:
2354 ; CHECK-32-O0: # %bb.0: # %entry
2355 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2356 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2357 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2358 ; CHECK-32-O0-NEXT: vinserth 2, 3, 14
2359 ; CHECK-32-O0-NEXT: blr
2360 entry:
2361 %vecins = insertelement <8 x i16> %a, i16 %b, i32 7
2362 ret <8 x i16> %vecins
2363 }
2365 ; The following tests try to insert one byte element into the vector. We
2366 ; should always be using the 'vinsertb' instruction.
2367 define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) {
2368 ; CHECK-64-OPT-LABEL: insert_byte_0:
2369 ; CHECK-64-OPT: # %bb.0: # %entry
2370 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2371 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 0
2372 ; CHECK-64-OPT-NEXT: blr
2373 ;
2374 ; CHECK-64-O0-LABEL: insert_byte_0:
2375 ; CHECK-64-O0: # %bb.0: # %entry
2376 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2377 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2378 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2379 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 0
2380 ; CHECK-64-O0-NEXT: blr
2381 ;
2382 ; CHECK-32-OPT-LABEL: insert_byte_0:
2383 ; CHECK-32-OPT: # %bb.0: # %entry
2384 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2385 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 0
2386 ; CHECK-32-OPT-NEXT: blr
2387 ;
2388 ; CHECK-32-O0-LABEL: insert_byte_0:
2389 ; CHECK-32-O0: # %bb.0: # %entry
2390 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2391 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2392 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2393 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 0
2394 ; CHECK-32-O0-NEXT: blr
2395 entry:
2396 %vecins = insertelement <16 x i8> %a, i8 %b, i32 0
2397 ret <16 x i8> %vecins
2398 }
2400 define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) {
2401 ; CHECK-64-OPT-LABEL: insert_byte_1:
2402 ; CHECK-64-OPT: # %bb.0: # %entry
2403 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2404 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 1
2405 ; CHECK-64-OPT-NEXT: blr
2406 ;
2407 ; CHECK-64-O0-LABEL: insert_byte_1:
2408 ; CHECK-64-O0: # %bb.0: # %entry
2409 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2410 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2411 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2412 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 1
2413 ; CHECK-64-O0-NEXT: blr
2414 ;
2415 ; CHECK-32-OPT-LABEL: insert_byte_1:
2416 ; CHECK-32-OPT: # %bb.0: # %entry
2417 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2418 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 1
2419 ; CHECK-32-OPT-NEXT: blr
2420 ;
2421 ; CHECK-32-O0-LABEL: insert_byte_1:
2422 ; CHECK-32-O0: # %bb.0: # %entry
2423 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2424 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2425 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2426 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 1
2427 ; CHECK-32-O0-NEXT: blr
2428 entry:
2429 %vecins = insertelement <16 x i8> %a, i8 %b, i32 1
2430 ret <16 x i8> %vecins
2431 }
2433 define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) {
2434 ; CHECK-64-OPT-LABEL: insert_byte_2:
2435 ; CHECK-64-OPT: # %bb.0: # %entry
2436 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2437 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 2
2438 ; CHECK-64-OPT-NEXT: blr
2439 ;
2440 ; CHECK-64-O0-LABEL: insert_byte_2:
2441 ; CHECK-64-O0: # %bb.0: # %entry
2442 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2443 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2444 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2445 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 2
2446 ; CHECK-64-O0-NEXT: blr
2447 ;
2448 ; CHECK-32-OPT-LABEL: insert_byte_2:
2449 ; CHECK-32-OPT: # %bb.0: # %entry
2450 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2451 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 2
2452 ; CHECK-32-OPT-NEXT: blr
2453 ;
2454 ; CHECK-32-O0-LABEL: insert_byte_2:
2455 ; CHECK-32-O0: # %bb.0: # %entry
2456 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2457 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2458 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2459 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 2
2460 ; CHECK-32-O0-NEXT: blr
2461 entry:
2462 %vecins = insertelement <16 x i8> %a, i8 %b, i32 2
2463 ret <16 x i8> %vecins
2464 }
2466 define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) {
2467 ; CHECK-64-OPT-LABEL: insert_byte_3:
2468 ; CHECK-64-OPT: # %bb.0: # %entry
2469 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2470 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 3
2471 ; CHECK-64-OPT-NEXT: blr
2472 ;
2473 ; CHECK-64-O0-LABEL: insert_byte_3:
2474 ; CHECK-64-O0: # %bb.0: # %entry
2475 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2476 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2477 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2478 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 3
2479 ; CHECK-64-O0-NEXT: blr
2480 ;
2481 ; CHECK-32-OPT-LABEL: insert_byte_3:
2482 ; CHECK-32-OPT: # %bb.0: # %entry
2483 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2484 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 3
2485 ; CHECK-32-OPT-NEXT: blr
2486 ;
2487 ; CHECK-32-O0-LABEL: insert_byte_3:
2488 ; CHECK-32-O0: # %bb.0: # %entry
2489 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2490 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2491 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2492 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 3
2493 ; CHECK-32-O0-NEXT: blr
2494 entry:
2495 %vecins = insertelement <16 x i8> %a, i8 %b, i32 3
2496 ret <16 x i8> %vecins
2497 }
2499 define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) {
2500 ; CHECK-64-OPT-LABEL: insert_byte_4:
2501 ; CHECK-64-OPT: # %bb.0: # %entry
2502 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2503 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 4
2504 ; CHECK-64-OPT-NEXT: blr
2505 ;
2506 ; CHECK-64-O0-LABEL: insert_byte_4:
2507 ; CHECK-64-O0: # %bb.0: # %entry
2508 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2509 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2510 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2511 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 4
2512 ; CHECK-64-O0-NEXT: blr
2513 ;
2514 ; CHECK-32-OPT-LABEL: insert_byte_4:
2515 ; CHECK-32-OPT: # %bb.0: # %entry
2516 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2517 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 4
2518 ; CHECK-32-OPT-NEXT: blr
2519 ;
2520 ; CHECK-32-O0-LABEL: insert_byte_4:
2521 ; CHECK-32-O0: # %bb.0: # %entry
2522 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2523 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2524 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2525 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 4
2526 ; CHECK-32-O0-NEXT: blr
2527 entry:
2528 %vecins = insertelement <16 x i8> %a, i8 %b, i32 4
2529 ret <16 x i8> %vecins
2530 }
2532 define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) {
2533 ; CHECK-64-OPT-LABEL: insert_byte_5:
2534 ; CHECK-64-OPT: # %bb.0: # %entry
2535 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2536 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 5
2537 ; CHECK-64-OPT-NEXT: blr
2538 ;
2539 ; CHECK-64-O0-LABEL: insert_byte_5:
2540 ; CHECK-64-O0: # %bb.0: # %entry
2541 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2542 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2543 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2544 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 5
2545 ; CHECK-64-O0-NEXT: blr
2546 ;
2547 ; CHECK-32-OPT-LABEL: insert_byte_5:
2548 ; CHECK-32-OPT: # %bb.0: # %entry
2549 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2550 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 5
2551 ; CHECK-32-OPT-NEXT: blr
2552 ;
2553 ; CHECK-32-O0-LABEL: insert_byte_5:
2554 ; CHECK-32-O0: # %bb.0: # %entry
2555 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2556 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2557 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2558 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 5
2559 ; CHECK-32-O0-NEXT: blr
2560 entry:
2561 %vecins = insertelement <16 x i8> %a, i8 %b, i32 5
2562 ret <16 x i8> %vecins
2563 }
2565 define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) {
2566 ; CHECK-64-OPT-LABEL: insert_byte_6:
2567 ; CHECK-64-OPT: # %bb.0: # %entry
2568 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2569 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 6
2570 ; CHECK-64-OPT-NEXT: blr
2571 ;
2572 ; CHECK-64-O0-LABEL: insert_byte_6:
2573 ; CHECK-64-O0: # %bb.0: # %entry
2574 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2575 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2576 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2577 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 6
2578 ; CHECK-64-O0-NEXT: blr
2579 ;
2580 ; CHECK-32-OPT-LABEL: insert_byte_6:
2581 ; CHECK-32-OPT: # %bb.0: # %entry
2582 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2583 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 6
2584 ; CHECK-32-OPT-NEXT: blr
2585 ;
2586 ; CHECK-32-O0-LABEL: insert_byte_6:
2587 ; CHECK-32-O0: # %bb.0: # %entry
2588 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2589 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2590 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2591 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 6
2592 ; CHECK-32-O0-NEXT: blr
2593 entry:
2594 %vecins = insertelement <16 x i8> %a, i8 %b, i32 6
2595 ret <16 x i8> %vecins
2596 }
2598 define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) {
2599 ; CHECK-64-OPT-LABEL: insert_byte_7:
2600 ; CHECK-64-OPT: # %bb.0: # %entry
2601 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2602 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 7
2603 ; CHECK-64-OPT-NEXT: blr
2604 ;
2605 ; CHECK-64-O0-LABEL: insert_byte_7:
2606 ; CHECK-64-O0: # %bb.0: # %entry
2607 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2608 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2609 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2610 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 7
2611 ; CHECK-64-O0-NEXT: blr
2612 ;
2613 ; CHECK-32-OPT-LABEL: insert_byte_7:
2614 ; CHECK-32-OPT: # %bb.0: # %entry
2615 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2616 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 7
2617 ; CHECK-32-OPT-NEXT: blr
2618 ;
2619 ; CHECK-32-O0-LABEL: insert_byte_7:
2620 ; CHECK-32-O0: # %bb.0: # %entry
2621 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2622 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2623 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2624 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 7
2625 ; CHECK-32-O0-NEXT: blr
2626 entry:
2627 %vecins = insertelement <16 x i8> %a, i8 %b, i32 7
2628 ret <16 x i8> %vecins
2629 }
2631 define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) {
2632 ; CHECK-64-OPT-LABEL: insert_byte_8:
2633 ; CHECK-64-OPT: # %bb.0: # %entry
2634 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2635 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 8
2636 ; CHECK-64-OPT-NEXT: blr
2637 ;
2638 ; CHECK-64-O0-LABEL: insert_byte_8:
2639 ; CHECK-64-O0: # %bb.0: # %entry
2640 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2641 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2642 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2643 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 8
2644 ; CHECK-64-O0-NEXT: blr
2645 ;
2646 ; CHECK-32-OPT-LABEL: insert_byte_8:
2647 ; CHECK-32-OPT: # %bb.0: # %entry
2648 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2649 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 8
2650 ; CHECK-32-OPT-NEXT: blr
2651 ;
2652 ; CHECK-32-O0-LABEL: insert_byte_8:
2653 ; CHECK-32-O0: # %bb.0: # %entry
2654 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2655 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2656 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2657 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 8
2658 ; CHECK-32-O0-NEXT: blr
2659 entry:
2660 %vecins = insertelement <16 x i8> %a, i8 %b, i32 8
2661 ret <16 x i8> %vecins
2662 }
2664 define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) {
2665 ; CHECK-64-OPT-LABEL: insert_byte_9:
2666 ; CHECK-64-OPT: # %bb.0: # %entry
2667 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2668 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 9
2669 ; CHECK-64-OPT-NEXT: blr
2670 ;
2671 ; CHECK-64-O0-LABEL: insert_byte_9:
2672 ; CHECK-64-O0: # %bb.0: # %entry
2673 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2674 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2675 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2676 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 9
2677 ; CHECK-64-O0-NEXT: blr
2678 ;
2679 ; CHECK-32-OPT-LABEL: insert_byte_9:
2680 ; CHECK-32-OPT: # %bb.0: # %entry
2681 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2682 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 9
2683 ; CHECK-32-OPT-NEXT: blr
2684 ;
2685 ; CHECK-32-O0-LABEL: insert_byte_9:
2686 ; CHECK-32-O0: # %bb.0: # %entry
2687 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2688 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2689 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2690 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 9
2691 ; CHECK-32-O0-NEXT: blr
2692 entry:
2693 %vecins = insertelement <16 x i8> %a, i8 %b, i32 9
2694 ret <16 x i8> %vecins
2695 }
2697 define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) {
2698 ; CHECK-64-OPT-LABEL: insert_byte_10:
2699 ; CHECK-64-OPT: # %bb.0: # %entry
2700 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2701 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 10
2702 ; CHECK-64-OPT-NEXT: blr
2703 ;
2704 ; CHECK-64-O0-LABEL: insert_byte_10:
2705 ; CHECK-64-O0: # %bb.0: # %entry
2706 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2707 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2708 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2709 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 10
2710 ; CHECK-64-O0-NEXT: blr
2711 ;
2712 ; CHECK-32-OPT-LABEL: insert_byte_10:
2713 ; CHECK-32-OPT: # %bb.0: # %entry
2714 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2715 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 10
2716 ; CHECK-32-OPT-NEXT: blr
2717 ;
2718 ; CHECK-32-O0-LABEL: insert_byte_10:
2719 ; CHECK-32-O0: # %bb.0: # %entry
2720 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2721 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2722 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2723 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 10
2724 ; CHECK-32-O0-NEXT: blr
2725 entry:
2726 %vecins = insertelement <16 x i8> %a, i8 %b, i32 10
2727 ret <16 x i8> %vecins
2728 }
2730 define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) {
2731 ; CHECK-64-OPT-LABEL: insert_byte_11:
2732 ; CHECK-64-OPT: # %bb.0: # %entry
2733 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2734 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 11
2735 ; CHECK-64-OPT-NEXT: blr
2736 ;
2737 ; CHECK-64-O0-LABEL: insert_byte_11:
2738 ; CHECK-64-O0: # %bb.0: # %entry
2739 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2740 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2741 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2742 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 11
2743 ; CHECK-64-O0-NEXT: blr
2744 ;
2745 ; CHECK-32-OPT-LABEL: insert_byte_11:
2746 ; CHECK-32-OPT: # %bb.0: # %entry
2747 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2748 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 11
2749 ; CHECK-32-OPT-NEXT: blr
2750 ;
2751 ; CHECK-32-O0-LABEL: insert_byte_11:
2752 ; CHECK-32-O0: # %bb.0: # %entry
2753 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2754 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2755 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2756 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 11
2757 ; CHECK-32-O0-NEXT: blr
2758 entry:
2759 %vecins = insertelement <16 x i8> %a, i8 %b, i32 11
2760 ret <16 x i8> %vecins
2761 }
2763 define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) {
2764 ; CHECK-64-OPT-LABEL: insert_byte_12:
2765 ; CHECK-64-OPT: # %bb.0: # %entry
2766 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2767 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 12
2768 ; CHECK-64-OPT-NEXT: blr
2769 ;
2770 ; CHECK-64-O0-LABEL: insert_byte_12:
2771 ; CHECK-64-O0: # %bb.0: # %entry
2772 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2773 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2774 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2775 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 12
2776 ; CHECK-64-O0-NEXT: blr
2777 ;
2778 ; CHECK-32-OPT-LABEL: insert_byte_12:
2779 ; CHECK-32-OPT: # %bb.0: # %entry
2780 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2781 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 12
2782 ; CHECK-32-OPT-NEXT: blr
2783 ;
2784 ; CHECK-32-O0-LABEL: insert_byte_12:
2785 ; CHECK-32-O0: # %bb.0: # %entry
2786 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2787 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2788 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2789 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 12
2790 ; CHECK-32-O0-NEXT: blr
2791 entry:
2792 %vecins = insertelement <16 x i8> %a, i8 %b, i32 12
2793 ret <16 x i8> %vecins
2794 }
2796 define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) {
2797 ; CHECK-64-OPT-LABEL: insert_byte_13:
2798 ; CHECK-64-OPT: # %bb.0: # %entry
2799 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2800 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 13
2801 ; CHECK-64-OPT-NEXT: blr
2802 ;
2803 ; CHECK-64-O0-LABEL: insert_byte_13:
2804 ; CHECK-64-O0: # %bb.0: # %entry
2805 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2806 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2807 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2808 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 13
2809 ; CHECK-64-O0-NEXT: blr
2810 ;
2811 ; CHECK-32-OPT-LABEL: insert_byte_13:
2812 ; CHECK-32-OPT: # %bb.0: # %entry
2813 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2814 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 13
2815 ; CHECK-32-OPT-NEXT: blr
2816 ;
2817 ; CHECK-32-O0-LABEL: insert_byte_13:
2818 ; CHECK-32-O0: # %bb.0: # %entry
2819 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2820 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2821 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2822 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 13
2823 ; CHECK-32-O0-NEXT: blr
2824 entry:
2825 %vecins = insertelement <16 x i8> %a, i8 %b, i32 13
2826 ret <16 x i8> %vecins
2827 }
2829 define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) {
2830 ; CHECK-64-OPT-LABEL: insert_byte_14:
2831 ; CHECK-64-OPT: # %bb.0: # %entry
2832 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2833 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 14
2834 ; CHECK-64-OPT-NEXT: blr
2835 ;
2836 ; CHECK-64-O0-LABEL: insert_byte_14:
2837 ; CHECK-64-O0: # %bb.0: # %entry
2838 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2839 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2840 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2841 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 14
2842 ; CHECK-64-O0-NEXT: blr
2843 ;
2844 ; CHECK-32-OPT-LABEL: insert_byte_14:
2845 ; CHECK-32-OPT: # %bb.0: # %entry
2846 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2847 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 14
2848 ; CHECK-32-OPT-NEXT: blr
2849 ;
2850 ; CHECK-32-O0-LABEL: insert_byte_14:
2851 ; CHECK-32-O0: # %bb.0: # %entry
2852 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2853 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2854 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2855 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 14
2856 ; CHECK-32-O0-NEXT: blr
2857 entry:
2858 %vecins = insertelement <16 x i8> %a, i8 %b, i32 14
2859 ret <16 x i8> %vecins
2860 }
2862 define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) {
2863 ; CHECK-64-OPT-LABEL: insert_byte_15:
2864 ; CHECK-64-OPT: # %bb.0: # %entry
2865 ; CHECK-64-OPT-NEXT: mtvsrwz 35, 3
2866 ; CHECK-64-OPT-NEXT: vinsertb 2, 3, 15
2867 ; CHECK-64-OPT-NEXT: blr
2868 ;
2869 ; CHECK-64-O0-LABEL: insert_byte_15:
2870 ; CHECK-64-O0: # %bb.0: # %entry
2871 ; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
2872 ; CHECK-64-O0-NEXT: mtfprwz 0, 3
2873 ; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0
2874 ; CHECK-64-O0-NEXT: vinsertb 2, 3, 15
2875 ; CHECK-64-O0-NEXT: blr
2876 ;
2877 ; CHECK-32-OPT-LABEL: insert_byte_15:
2878 ; CHECK-32-OPT: # %bb.0: # %entry
2879 ; CHECK-32-OPT-NEXT: mtvsrwz 35, 3
2880 ; CHECK-32-OPT-NEXT: vinsertb 2, 3, 15
2881 ; CHECK-32-OPT-NEXT: blr
2882 ;
2883 ; CHECK-32-O0-LABEL: insert_byte_15:
2884 ; CHECK-32-O0: # %bb.0: # %entry
2885 ; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3
2886 ; CHECK-32-O0-NEXT: mtfprwz 0, 3
2887 ; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0
2888 ; CHECK-32-O0-NEXT: vinsertb 2, 3, 15
2889 ; CHECK-32-O0-NEXT: blr
2890 entry:
2891 %vecins = insertelement <16 x i8> %a, i8 %b, i32 15
2892 ret <16 x i8> %vecins
2893 }