| blob | 22a0505dad34cbb26e7b120647b13fb796336f7e |
1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
2 ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \
3 ; RUN: --check-prefix=SMALL32
4 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
5 ; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \
6 ; RUN: | FileCheck %s --check-prefix=LARGE32
7 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
8 ; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
9 ; RUN: --check-prefix=SMALL64
10 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
11 ; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
12 ; RUN: | FileCheck %s --check-prefix=LARGE64
14 @TGInit = thread_local global double 1.000000e+00, align 8
15 @TWInit = weak thread_local global double 1.000000e+00, align 8
16 @GInit = global double 1.000000e+00, align 8
17 @TGUninit = thread_local global double 0.000000e+00, align 8
18 @TIInit = internal thread_local global double 1.000000e+00, align 8
20 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
21 define void @storesTGUninit(double %Val) #0 {
22 ; SMALL32-LABEL: storesTGUninit:
23 ; SMALL32: # %bb.0: # %entry
24 ; SMALL32-NEXT: mflr 0
25 ; SMALL32-NEXT: stw 0, 8(1)
26 ; SMALL32-NEXT: stwu 1, -32(1)
27 ; SMALL32-NEXT: lwz 3, L..C0(2)
28 ; SMALL32-NEXT: lwz 4, L..C1(2)
29 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
30 ; SMALL32-NEXT: stfd 1, 0(3)
31 ; SMALL32-NEXT: addi 1, 1, 32
32 ; SMALL32-NEXT: lwz 0, 8(1)
33 ; SMALL32-NEXT: mtlr 0
34 ; SMALL32-NEXT: blr
35 ;
36 ; LARGE32-LABEL: storesTGUninit:
37 ; LARGE32: # %bb.0: # %entry
38 ; LARGE32-NEXT: mflr 0
39 ; LARGE32-NEXT: stw 0, 8(1)
40 ; LARGE32-NEXT: stwu 1, -32(1)
41 ; LARGE32-NEXT: addis 3, L..C0@u(2)
42 ; LARGE32-NEXT: addis 4, L..C1@u(2)
43 ; LARGE32-NEXT: lwz 3, L..C0@l(3)
44 ; LARGE32-NEXT: lwz 4, L..C1@l(4)
45 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
46 ; LARGE32-NEXT: stfd 1, 0(3)
47 ; LARGE32-NEXT: addi 1, 1, 32
48 ; LARGE32-NEXT: lwz 0, 8(1)
49 ; LARGE32-NEXT: mtlr 0
50 ; LARGE32-NEXT: blr
51 ;
52 ; SMALL64-LABEL: storesTGUninit:
53 ; SMALL64: # %bb.0: # %entry
54 ; SMALL64-NEXT: mflr 0
55 ; SMALL64-NEXT: std 0, 16(1)
56 ; SMALL64-NEXT: stdu 1, -48(1)
57 ; SMALL64-NEXT: ld 3, L..C0(2)
58 ; SMALL64-NEXT: ld 4, L..C1(2)
59 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
60 ; SMALL64-NEXT: stfd 1, 0(3)
61 ; SMALL64-NEXT: addi 1, 1, 48
62 ; SMALL64-NEXT: ld 0, 16(1)
63 ; SMALL64-NEXT: mtlr 0
64 ; SMALL64-NEXT: blr
65 ;
66 ; LARGE64-LABEL: storesTGUninit:
67 ; LARGE64: # %bb.0: # %entry
68 ; LARGE64-NEXT: mflr 0
69 ; LARGE64-NEXT: std 0, 16(1)
70 ; LARGE64-NEXT: stdu 1, -48(1)
71 ; LARGE64-NEXT: addis 3, L..C0@u(2)
72 ; LARGE64-NEXT: addis 4, L..C1@u(2)
73 ; LARGE64-NEXT: ld 3, L..C0@l(3)
74 ; LARGE64-NEXT: ld 4, L..C1@l(4)
75 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
76 ; LARGE64-NEXT: stfd 1, 0(3)
77 ; LARGE64-NEXT: addi 1, 1, 48
78 ; LARGE64-NEXT: ld 0, 16(1)
79 ; LARGE64-NEXT: mtlr 0
80 ; LARGE64-NEXT: blr
81 entry:
82 store double %Val, double* @TGUninit, align 8
83 ret void
84 }
86 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
87 define void @storesTGInit(double %Val) #0 {
88 ; SMALL32-LABEL: storesTGInit:
89 ; SMALL32: # %bb.0: # %entry
90 ; SMALL32-NEXT: mflr 0
91 ; SMALL32-NEXT: stw 0, 8(1)
92 ; SMALL32-NEXT: stwu 1, -32(1)
93 ; SMALL32-NEXT: lwz 3, L..C2(2)
94 ; SMALL32-NEXT: lwz 4, L..C3(2)
95 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
96 ; SMALL32-NEXT: stfd 1, 0(3)
97 ; SMALL32-NEXT: addi 1, 1, 32
98 ; SMALL32-NEXT: lwz 0, 8(1)
99 ; SMALL32-NEXT: mtlr 0
100 ; SMALL32-NEXT: blr
101 ;
102 ; LARGE32-LABEL: storesTGInit:
103 ; LARGE32: # %bb.0: # %entry
104 ; LARGE32-NEXT: mflr 0
105 ; LARGE32-NEXT: stw 0, 8(1)
106 ; LARGE32-NEXT: stwu 1, -32(1)
107 ; LARGE32-NEXT: addis 3, L..C2@u(2)
108 ; LARGE32-NEXT: addis 4, L..C3@u(2)
109 ; LARGE32-NEXT: lwz 3, L..C2@l(3)
110 ; LARGE32-NEXT: lwz 4, L..C3@l(4)
111 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
112 ; LARGE32-NEXT: stfd 1, 0(3)
113 ; LARGE32-NEXT: addi 1, 1, 32
114 ; LARGE32-NEXT: lwz 0, 8(1)
115 ; LARGE32-NEXT: mtlr 0
116 ; LARGE32-NEXT: blr
117 ;
118 ; SMALL64-LABEL: storesTGInit:
119 ; SMALL64: # %bb.0: # %entry
120 ; SMALL64-NEXT: mflr 0
121 ; SMALL64-NEXT: std 0, 16(1)
122 ; SMALL64-NEXT: stdu 1, -48(1)
123 ; SMALL64-NEXT: ld 3, L..C2(2)
124 ; SMALL64-NEXT: ld 4, L..C3(2)
125 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
126 ; SMALL64-NEXT: stfd 1, 0(3)
127 ; SMALL64-NEXT: addi 1, 1, 48
128 ; SMALL64-NEXT: ld 0, 16(1)
129 ; SMALL64-NEXT: mtlr 0
130 ; SMALL64-NEXT: blr
131 ;
132 ; LARGE64-LABEL: storesTGInit:
133 ; LARGE64: # %bb.0: # %entry
134 ; LARGE64-NEXT: mflr 0
135 ; LARGE64-NEXT: std 0, 16(1)
136 ; LARGE64-NEXT: stdu 1, -48(1)
137 ; LARGE64-NEXT: addis 3, L..C2@u(2)
138 ; LARGE64-NEXT: addis 4, L..C3@u(2)
139 ; LARGE64-NEXT: ld 3, L..C2@l(3)
140 ; LARGE64-NEXT: ld 4, L..C3@l(4)
141 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
142 ; LARGE64-NEXT: stfd 1, 0(3)
143 ; LARGE64-NEXT: addi 1, 1, 48
144 ; LARGE64-NEXT: ld 0, 16(1)
145 ; LARGE64-NEXT: mtlr 0
146 ; LARGE64-NEXT: blr
147 entry:
148 store double %Val, double* @TGInit, align 8
149 ret void
150 }
152 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
153 define void @storesTIInit(double %Val) #0 {
154 ; SMALL32-LABEL: storesTIInit:
155 ; SMALL32: # %bb.0: # %entry
156 ; SMALL32-NEXT: mflr 0
157 ; SMALL32-NEXT: stw 0, 8(1)
158 ; SMALL32-NEXT: stwu 1, -32(1)
159 ; SMALL32-NEXT: lwz 3, L..C4(2)
160 ; SMALL32-NEXT: lwz 4, L..C5(2)
161 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
162 ; SMALL32-NEXT: stfd 1, 0(3)
163 ; SMALL32-NEXT: addi 1, 1, 32
164 ; SMALL32-NEXT: lwz 0, 8(1)
165 ; SMALL32-NEXT: mtlr 0
166 ; SMALL32-NEXT: blr
167 ;
168 ; LARGE32-LABEL: storesTIInit:
169 ; LARGE32: # %bb.0: # %entry
170 ; LARGE32-NEXT: mflr 0
171 ; LARGE32-NEXT: stw 0, 8(1)
172 ; LARGE32-NEXT: stwu 1, -32(1)
173 ; LARGE32-NEXT: addis 3, L..C4@u(2)
174 ; LARGE32-NEXT: addis 4, L..C5@u(2)
175 ; LARGE32-NEXT: lwz 3, L..C4@l(3)
176 ; LARGE32-NEXT: lwz 4, L..C5@l(4)
177 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
178 ; LARGE32-NEXT: stfd 1, 0(3)
179 ; LARGE32-NEXT: addi 1, 1, 32
180 ; LARGE32-NEXT: lwz 0, 8(1)
181 ; LARGE32-NEXT: mtlr 0
182 ; LARGE32-NEXT: blr
183 ;
184 ; SMALL64-LABEL: storesTIInit:
185 ; SMALL64: # %bb.0: # %entry
186 ; SMALL64-NEXT: mflr 0
187 ; SMALL64-NEXT: std 0, 16(1)
188 ; SMALL64-NEXT: stdu 1, -48(1)
189 ; SMALL64-NEXT: ld 3, L..C4(2)
190 ; SMALL64-NEXT: ld 4, L..C5(2)
191 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
192 ; SMALL64-NEXT: stfd 1, 0(3)
193 ; SMALL64-NEXT: addi 1, 1, 48
194 ; SMALL64-NEXT: ld 0, 16(1)
195 ; SMALL64-NEXT: mtlr 0
196 ; SMALL64-NEXT: blr
197 ;
198 ; LARGE64-LABEL: storesTIInit:
199 ; LARGE64: # %bb.0: # %entry
200 ; LARGE64-NEXT: mflr 0
201 ; LARGE64-NEXT: std 0, 16(1)
202 ; LARGE64-NEXT: stdu 1, -48(1)
203 ; LARGE64-NEXT: addis 3, L..C4@u(2)
204 ; LARGE64-NEXT: addis 4, L..C5@u(2)
205 ; LARGE64-NEXT: ld 3, L..C4@l(3)
206 ; LARGE64-NEXT: ld 4, L..C5@l(4)
207 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
208 ; LARGE64-NEXT: stfd 1, 0(3)
209 ; LARGE64-NEXT: addi 1, 1, 48
210 ; LARGE64-NEXT: ld 0, 16(1)
211 ; LARGE64-NEXT: mtlr 0
212 ; LARGE64-NEXT: blr
213 entry:
214 store double %Val, double* @TIInit, align 8
215 ret void
216 }
218 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
219 define void @storesTWInit(double %Val) #0 {
220 ; SMALL32-LABEL: storesTWInit:
221 ; SMALL32: # %bb.0: # %entry
222 ; SMALL32-NEXT: mflr 0
223 ; SMALL32-NEXT: stw 0, 8(1)
224 ; SMALL32-NEXT: stwu 1, -32(1)
225 ; SMALL32-NEXT: lwz 3, L..C6(2)
226 ; SMALL32-NEXT: lwz 4, L..C7(2)
227 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
228 ; SMALL32-NEXT: stfd 1, 0(3)
229 ; SMALL32-NEXT: addi 1, 1, 32
230 ; SMALL32-NEXT: lwz 0, 8(1)
231 ; SMALL32-NEXT: mtlr 0
232 ; SMALL32-NEXT: blr
233 ;
234 ; LARGE32-LABEL: storesTWInit:
235 ; LARGE32: # %bb.0: # %entry
236 ; LARGE32-NEXT: mflr 0
237 ; LARGE32-NEXT: stw 0, 8(1)
238 ; LARGE32-NEXT: stwu 1, -32(1)
239 ; LARGE32-NEXT: addis 3, L..C6@u(2)
240 ; LARGE32-NEXT: addis 4, L..C7@u(2)
241 ; LARGE32-NEXT: lwz 3, L..C6@l(3)
242 ; LARGE32-NEXT: lwz 4, L..C7@l(4)
243 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
244 ; LARGE32-NEXT: stfd 1, 0(3)
245 ; LARGE32-NEXT: addi 1, 1, 32
246 ; LARGE32-NEXT: lwz 0, 8(1)
247 ; LARGE32-NEXT: mtlr 0
248 ; LARGE32-NEXT: blr
249 ;
250 ; SMALL64-LABEL: storesTWInit:
251 ; SMALL64: # %bb.0: # %entry
252 ; SMALL64-NEXT: mflr 0
253 ; SMALL64-NEXT: std 0, 16(1)
254 ; SMALL64-NEXT: stdu 1, -48(1)
255 ; SMALL64-NEXT: ld 3, L..C6(2)
256 ; SMALL64-NEXT: ld 4, L..C7(2)
257 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
258 ; SMALL64-NEXT: stfd 1, 0(3)
259 ; SMALL64-NEXT: addi 1, 1, 48
260 ; SMALL64-NEXT: ld 0, 16(1)
261 ; SMALL64-NEXT: mtlr 0
262 ; SMALL64-NEXT: blr
263 ;
264 ; LARGE64-LABEL: storesTWInit:
265 ; LARGE64: # %bb.0: # %entry
266 ; LARGE64-NEXT: mflr 0
267 ; LARGE64-NEXT: std 0, 16(1)
268 ; LARGE64-NEXT: stdu 1, -48(1)
269 ; LARGE64-NEXT: addis 3, L..C6@u(2)
270 ; LARGE64-NEXT: addis 4, L..C7@u(2)
271 ; LARGE64-NEXT: ld 3, L..C6@l(3)
272 ; LARGE64-NEXT: ld 4, L..C7@l(4)
273 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
274 ; LARGE64-NEXT: stfd 1, 0(3)
275 ; LARGE64-NEXT: addi 1, 1, 48
276 ; LARGE64-NEXT: ld 0, 16(1)
277 ; LARGE64-NEXT: mtlr 0
278 ; LARGE64-NEXT: blr
279 entry:
280 store double %Val, double* @TWInit, align 8
281 ret void
282 }
284 ; Function Attrs: norecurse nounwind readonly willreturn
285 define double @loadsTGUninit() #1 {
286 ; SMALL32-LABEL: loadsTGUninit:
287 ; SMALL32: # %bb.0: # %entry
288 ; SMALL32-NEXT: mflr 0
289 ; SMALL32-NEXT: stw 0, 8(1)
290 ; SMALL32-NEXT: stwu 1, -32(1)
291 ; SMALL32-NEXT: lwz 3, L..C0(2)
292 ; SMALL32-NEXT: lwz 4, L..C1(2)
293 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
294 ; SMALL32-NEXT: lwz 4, L..C8(2)
295 ; SMALL32-NEXT: lfd 0, 0(3)
296 ; SMALL32-NEXT: lfd 1, 0(4)
297 ; SMALL32-NEXT: fadd 1, 0, 1
298 ; SMALL32-NEXT: addi 1, 1, 32
299 ; SMALL32-NEXT: lwz 0, 8(1)
300 ; SMALL32-NEXT: mtlr 0
301 ; SMALL32-NEXT: blr
302 ;
303 ; LARGE32-LABEL: loadsTGUninit:
304 ; LARGE32: # %bb.0: # %entry
305 ; LARGE32-NEXT: mflr 0
306 ; LARGE32-NEXT: stw 0, 8(1)
307 ; LARGE32-NEXT: stwu 1, -32(1)
308 ; LARGE32-NEXT: addis 3, L..C0@u(2)
309 ; LARGE32-NEXT: addis 4, L..C1@u(2)
310 ; LARGE32-NEXT: lwz 3, L..C0@l(3)
311 ; LARGE32-NEXT: lwz 4, L..C1@l(4)
312 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
313 ; LARGE32-NEXT: lfd 0, 0(3)
314 ; LARGE32-NEXT: addis 3, L..C8@u(2)
315 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
316 ; LARGE32-NEXT: lfd 1, 0(3)
317 ; LARGE32-NEXT: fadd 1, 0, 1
318 ; LARGE32-NEXT: addi 1, 1, 32
319 ; LARGE32-NEXT: lwz 0, 8(1)
320 ; LARGE32-NEXT: mtlr 0
321 ; LARGE32-NEXT: blr
322 ;
323 ; SMALL64-LABEL: loadsTGUninit:
324 ; SMALL64: # %bb.0: # %entry
325 ; SMALL64-NEXT: mflr 0
326 ; SMALL64-NEXT: std 0, 16(1)
327 ; SMALL64-NEXT: stdu 1, -48(1)
328 ; SMALL64-NEXT: ld 3, L..C0(2)
329 ; SMALL64-NEXT: ld 4, L..C1(2)
330 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
331 ; SMALL64-NEXT: ld 4, L..C8(2)
332 ; SMALL64-NEXT: lfd 0, 0(3)
333 ; SMALL64-NEXT: lfd 1, 0(4)
334 ; SMALL64-NEXT: fadd 1, 0, 1
335 ; SMALL64-NEXT: addi 1, 1, 48
336 ; SMALL64-NEXT: ld 0, 16(1)
337 ; SMALL64-NEXT: mtlr 0
338 ; SMALL64-NEXT: blr
339 ;
340 ; LARGE64-LABEL: loadsTGUninit:
341 ; LARGE64: # %bb.0: # %entry
342 ; LARGE64-NEXT: mflr 0
343 ; LARGE64-NEXT: std 0, 16(1)
344 ; LARGE64-NEXT: stdu 1, -48(1)
345 ; LARGE64-NEXT: addis 3, L..C0@u(2)
346 ; LARGE64-NEXT: addis 4, L..C1@u(2)
347 ; LARGE64-NEXT: ld 3, L..C0@l(3)
348 ; LARGE64-NEXT: ld 4, L..C1@l(4)
349 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
350 ; LARGE64-NEXT: addis 4, L..C8@u(2)
351 ; LARGE64-NEXT: lfd 0, 0(3)
352 ; LARGE64-NEXT: ld 3, L..C8@l(4)
353 ; LARGE64-NEXT: lfd 1, 0(3)
354 ; LARGE64-NEXT: fadd 1, 0, 1
355 ; LARGE64-NEXT: addi 1, 1, 48
356 ; LARGE64-NEXT: ld 0, 16(1)
357 ; LARGE64-NEXT: mtlr 0
358 ; LARGE64-NEXT: blr
359 entry:
360 %0 = load double, double* @TGUninit, align 8
361 %1 = load double, double* @GInit, align 8
362 %add = fadd double %0, %1
363 ret double %add
364 }
366 ; Function Attrs: norecurse nounwind readonly willreturn
367 define double @loadsTGInit() #1 {
368 ; SMALL32-LABEL: loadsTGInit:
369 ; SMALL32: # %bb.0: # %entry
370 ; SMALL32-NEXT: mflr 0
371 ; SMALL32-NEXT: stw 0, 8(1)
372 ; SMALL32-NEXT: stwu 1, -32(1)
373 ; SMALL32-NEXT: lwz 3, L..C2(2)
374 ; SMALL32-NEXT: lwz 4, L..C3(2)
375 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
376 ; SMALL32-NEXT: lwz 4, L..C8(2)
377 ; SMALL32-NEXT: lfd 0, 0(3)
378 ; SMALL32-NEXT: lfd 1, 0(4)
379 ; SMALL32-NEXT: fadd 1, 0, 1
380 ; SMALL32-NEXT: addi 1, 1, 32
381 ; SMALL32-NEXT: lwz 0, 8(1)
382 ; SMALL32-NEXT: mtlr 0
383 ; SMALL32-NEXT: blr
384 ;
385 ; LARGE32-LABEL: loadsTGInit:
386 ; LARGE32: # %bb.0: # %entry
387 ; LARGE32-NEXT: mflr 0
388 ; LARGE32-NEXT: stw 0, 8(1)
389 ; LARGE32-NEXT: stwu 1, -32(1)
390 ; LARGE32-NEXT: addis 3, L..C2@u(2)
391 ; LARGE32-NEXT: addis 4, L..C3@u(2)
392 ; LARGE32-NEXT: lwz 3, L..C2@l(3)
393 ; LARGE32-NEXT: lwz 4, L..C3@l(4)
394 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
395 ; LARGE32-NEXT: lfd 0, 0(3)
396 ; LARGE32-NEXT: addis 3, L..C8@u(2)
397 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
398 ; LARGE32-NEXT: lfd 1, 0(3)
399 ; LARGE32-NEXT: fadd 1, 0, 1
400 ; LARGE32-NEXT: addi 1, 1, 32
401 ; LARGE32-NEXT: lwz 0, 8(1)
402 ; LARGE32-NEXT: mtlr 0
403 ; LARGE32-NEXT: blr
404 ;
405 ; SMALL64-LABEL: loadsTGInit:
406 ; SMALL64: # %bb.0: # %entry
407 ; SMALL64-NEXT: mflr 0
408 ; SMALL64-NEXT: std 0, 16(1)
409 ; SMALL64-NEXT: stdu 1, -48(1)
410 ; SMALL64-NEXT: ld 3, L..C2(2)
411 ; SMALL64-NEXT: ld 4, L..C3(2)
412 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
413 ; SMALL64-NEXT: ld 4, L..C8(2)
414 ; SMALL64-NEXT: lfd 0, 0(3)
415 ; SMALL64-NEXT: lfd 1, 0(4)
416 ; SMALL64-NEXT: fadd 1, 0, 1
417 ; SMALL64-NEXT: addi 1, 1, 48
418 ; SMALL64-NEXT: ld 0, 16(1)
419 ; SMALL64-NEXT: mtlr 0
420 ; SMALL64-NEXT: blr
421 ;
422 ; LARGE64-LABEL: loadsTGInit:
423 ; LARGE64: # %bb.0: # %entry
424 ; LARGE64-NEXT: mflr 0
425 ; LARGE64-NEXT: std 0, 16(1)
426 ; LARGE64-NEXT: stdu 1, -48(1)
427 ; LARGE64-NEXT: addis 3, L..C2@u(2)
428 ; LARGE64-NEXT: addis 4, L..C3@u(2)
429 ; LARGE64-NEXT: ld 3, L..C2@l(3)
430 ; LARGE64-NEXT: ld 4, L..C3@l(4)
431 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
432 ; LARGE64-NEXT: addis 4, L..C8@u(2)
433 ; LARGE64-NEXT: lfd 0, 0(3)
434 ; LARGE64-NEXT: ld 3, L..C8@l(4)
435 ; LARGE64-NEXT: lfd 1, 0(3)
436 ; LARGE64-NEXT: fadd 1, 0, 1
437 ; LARGE64-NEXT: addi 1, 1, 48
438 ; LARGE64-NEXT: ld 0, 16(1)
439 ; LARGE64-NEXT: mtlr 0
440 ; LARGE64-NEXT: blr
441 entry:
442 %0 = load double, double* @TGInit, align 8
443 %1 = load double, double* @GInit, align 8
444 %add = fadd double %0, %1
445 ret double %add
446 }
448 ; Function Attrs: norecurse nounwind readonly willreturn
449 define double @loadsTIInit() #1 {
450 ; SMALL32-LABEL: loadsTIInit:
451 ; SMALL32: # %bb.0: # %entry
452 ; SMALL32-NEXT: mflr 0
453 ; SMALL32-NEXT: stw 0, 8(1)
454 ; SMALL32-NEXT: stwu 1, -32(1)
455 ; SMALL32-NEXT: lwz 3, L..C4(2)
456 ; SMALL32-NEXT: lwz 4, L..C5(2)
457 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
458 ; SMALL32-NEXT: lwz 4, L..C8(2)
459 ; SMALL32-NEXT: lfd 0, 0(3)
460 ; SMALL32-NEXT: lfd 1, 0(4)
461 ; SMALL32-NEXT: fadd 1, 0, 1
462 ; SMALL32-NEXT: addi 1, 1, 32
463 ; SMALL32-NEXT: lwz 0, 8(1)
464 ; SMALL32-NEXT: mtlr 0
465 ; SMALL32-NEXT: blr
466 ;
467 ; LARGE32-LABEL: loadsTIInit:
468 ; LARGE32: # %bb.0: # %entry
469 ; LARGE32-NEXT: mflr 0
470 ; LARGE32-NEXT: stw 0, 8(1)
471 ; LARGE32-NEXT: stwu 1, -32(1)
472 ; LARGE32-NEXT: addis 3, L..C4@u(2)
473 ; LARGE32-NEXT: addis 4, L..C5@u(2)
474 ; LARGE32-NEXT: lwz 3, L..C4@l(3)
475 ; LARGE32-NEXT: lwz 4, L..C5@l(4)
476 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
477 ; LARGE32-NEXT: lfd 0, 0(3)
478 ; LARGE32-NEXT: addis 3, L..C8@u(2)
479 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
480 ; LARGE32-NEXT: lfd 1, 0(3)
481 ; LARGE32-NEXT: fadd 1, 0, 1
482 ; LARGE32-NEXT: addi 1, 1, 32
483 ; LARGE32-NEXT: lwz 0, 8(1)
484 ; LARGE32-NEXT: mtlr 0
485 ; LARGE32-NEXT: blr
486 ;
487 ; SMALL64-LABEL: loadsTIInit:
488 ; SMALL64: # %bb.0: # %entry
489 ; SMALL64-NEXT: mflr 0
490 ; SMALL64-NEXT: std 0, 16(1)
491 ; SMALL64-NEXT: stdu 1, -48(1)
492 ; SMALL64-NEXT: ld 3, L..C4(2)
493 ; SMALL64-NEXT: ld 4, L..C5(2)
494 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
495 ; SMALL64-NEXT: ld 4, L..C8(2)
496 ; SMALL64-NEXT: lfd 0, 0(3)
497 ; SMALL64-NEXT: lfd 1, 0(4)
498 ; SMALL64-NEXT: fadd 1, 0, 1
499 ; SMALL64-NEXT: addi 1, 1, 48
500 ; SMALL64-NEXT: ld 0, 16(1)
501 ; SMALL64-NEXT: mtlr 0
502 ; SMALL64-NEXT: blr
503 ;
504 ; LARGE64-LABEL: loadsTIInit:
505 ; LARGE64: # %bb.0: # %entry
506 ; LARGE64-NEXT: mflr 0
507 ; LARGE64-NEXT: std 0, 16(1)
508 ; LARGE64-NEXT: stdu 1, -48(1)
509 ; LARGE64-NEXT: addis 3, L..C4@u(2)
510 ; LARGE64-NEXT: addis 4, L..C5@u(2)
511 ; LARGE64-NEXT: ld 3, L..C4@l(3)
512 ; LARGE64-NEXT: ld 4, L..C5@l(4)
513 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
514 ; LARGE64-NEXT: addis 4, L..C8@u(2)
515 ; LARGE64-NEXT: lfd 0, 0(3)
516 ; LARGE64-NEXT: ld 3, L..C8@l(4)
517 ; LARGE64-NEXT: lfd 1, 0(3)
518 ; LARGE64-NEXT: fadd 1, 0, 1
519 ; LARGE64-NEXT: addi 1, 1, 48
520 ; LARGE64-NEXT: ld 0, 16(1)
521 ; LARGE64-NEXT: mtlr 0
522 ; LARGE64-NEXT: blr
523 entry:
524 %0 = load double, double* @TIInit, align 8
525 %1 = load double, double* @GInit, align 8
526 %add = fadd double %0, %1
527 ret double %add
528 }
530 ; Function Attrs: norecurse nounwind readonly willreturn
531 define double @loadsTWInit() #1 {
532 ; SMALL32-LABEL: loadsTWInit:
533 ; SMALL32: # %bb.0: # %entry
534 ; SMALL32-NEXT: mflr 0
535 ; SMALL32-NEXT: stw 0, 8(1)
536 ; SMALL32-NEXT: stwu 1, -32(1)
537 ; SMALL32-NEXT: lwz 3, L..C6(2)
538 ; SMALL32-NEXT: lwz 4, L..C7(2)
539 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
540 ; SMALL32-NEXT: lwz 4, L..C8(2)
541 ; SMALL32-NEXT: lfd 0, 0(3)
542 ; SMALL32-NEXT: lfd 1, 0(4)
543 ; SMALL32-NEXT: fadd 1, 0, 1
544 ; SMALL32-NEXT: addi 1, 1, 32
545 ; SMALL32-NEXT: lwz 0, 8(1)
546 ; SMALL32-NEXT: mtlr 0
547 ; SMALL32-NEXT: blr
548 ;
549 ; LARGE32-LABEL: loadsTWInit:
550 ; LARGE32: # %bb.0: # %entry
551 ; LARGE32-NEXT: mflr 0
552 ; LARGE32-NEXT: stw 0, 8(1)
553 ; LARGE32-NEXT: stwu 1, -32(1)
554 ; LARGE32-NEXT: addis 3, L..C6@u(2)
555 ; LARGE32-NEXT: addis 4, L..C7@u(2)
556 ; LARGE32-NEXT: lwz 3, L..C6@l(3)
557 ; LARGE32-NEXT: lwz 4, L..C7@l(4)
558 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
559 ; LARGE32-NEXT: lfd 0, 0(3)
560 ; LARGE32-NEXT: addis 3, L..C8@u(2)
561 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
562 ; LARGE32-NEXT: lfd 1, 0(3)
563 ; LARGE32-NEXT: fadd 1, 0, 1
564 ; LARGE32-NEXT: addi 1, 1, 32
565 ; LARGE32-NEXT: lwz 0, 8(1)
566 ; LARGE32-NEXT: mtlr 0
567 ; LARGE32-NEXT: blr
568 ;
569 ; SMALL64-LABEL: loadsTWInit:
570 ; SMALL64: # %bb.0: # %entry
571 ; SMALL64-NEXT: mflr 0
572 ; SMALL64-NEXT: std 0, 16(1)
573 ; SMALL64-NEXT: stdu 1, -48(1)
574 ; SMALL64-NEXT: ld 3, L..C6(2)
575 ; SMALL64-NEXT: ld 4, L..C7(2)
576 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
577 ; SMALL64-NEXT: ld 4, L..C8(2)
578 ; SMALL64-NEXT: lfd 0, 0(3)
579 ; SMALL64-NEXT: lfd 1, 0(4)
580 ; SMALL64-NEXT: fadd 1, 0, 1
581 ; SMALL64-NEXT: addi 1, 1, 48
582 ; SMALL64-NEXT: ld 0, 16(1)
583 ; SMALL64-NEXT: mtlr 0
584 ; SMALL64-NEXT: blr
585 ;
586 ; LARGE64-LABEL: loadsTWInit:
587 ; LARGE64: # %bb.0: # %entry
588 ; LARGE64-NEXT: mflr 0
589 ; LARGE64-NEXT: std 0, 16(1)
590 ; LARGE64-NEXT: stdu 1, -48(1)
591 ; LARGE64-NEXT: addis 3, L..C6@u(2)
592 ; LARGE64-NEXT: addis 4, L..C7@u(2)
593 ; LARGE64-NEXT: ld 3, L..C6@l(3)
594 ; LARGE64-NEXT: ld 4, L..C7@l(4)
595 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
596 ; LARGE64-NEXT: addis 4, L..C8@u(2)
597 ; LARGE64-NEXT: lfd 0, 0(3)
598 ; LARGE64-NEXT: ld 3, L..C8@l(4)
599 ; LARGE64-NEXT: lfd 1, 0(3)
600 ; LARGE64-NEXT: fadd 1, 0, 1
601 ; LARGE64-NEXT: addi 1, 1, 48
602 ; LARGE64-NEXT: ld 0, 16(1)
603 ; LARGE64-NEXT: mtlr 0
604 ; LARGE64-NEXT: blr
605 entry:
606 %0 = load double, double* @TWInit, align 8
607 %1 = load double, double* @GInit, align 8
608 %add = fadd double %0, %1
609 ret double %add
610 }
612 ; External symbol reference checks for .__tls_get_addr
614 ; SMALL32: .extern .__tls_get_addr[PR]
615 ; SMALL64: .extern .__tls_get_addr[PR]
616 ; LARGE32: .extern .__tls_get_addr[PR]
617 ; LARGE64: .extern .__tls_get_addr[PR]
619 ; TOC entry checks
621 ; SMALL32-LABEL: .toc
622 ; SMALL32-LABEL: L..C0:
623 ; SMALL32-NEXT: .tc .TGUninit[TC],TGUninit[TL]@m
624 ; SMALL32-LABEL: L..C1:
625 ; SMALL32-NEXT: .tc TGUninit[TC],TGUninit[TL]@gd
626 ; SMALL32-LABEL: L..C2:
627 ; SMALL32-NEXT: .tc .TGInit[TC],TGInit[TL]@m
628 ; SMALL32-LABEL: L..C3:
629 ; SMALL32-NEXT: .tc TGInit[TC],TGInit[TL]@gd
630 ; SMALL32-LABEL: L..C4:
631 ; SMALL32-NEXT: .tc .TIInit[TC],TIInit[TL]@m
632 ; SMALL32-LABEL: L..C5:
633 ; SMALL32-NEXT: .tc TIInit[TC],TIInit[TL]@gd
634 ; SMALL32-LABEL: L..C6:
635 ; SMALL32-NEXT: .tc .TWInit[TC],TWInit[TL]@m
636 ; SMALL32-LABEL: L..C7:
637 ; SMALL32-NEXT: .tc TWInit[TC],TWInit[TL]@gd
638 ; SMALL32-LABEL: L..C8:
639 ; SMALL32-NEXT: .tc GInit[TC],GInit[RW]
641 ; LARGE32-LABEL: .toc
642 ; LARGE32-LABEL: L..C0:
643 ; LARGE32-NEXT: .tc .TGUninit[TE],TGUninit[TL]@m
644 ; LARGE32-LABEL: L..C1:
645 ; LARGE32-NEXT: .tc TGUninit[TE],TGUninit[TL]@gd
646 ; LARGE32-LABEL: L..C2:
647 ; LARGE32-NEXT: .tc .TGInit[TE],TGInit[TL]@m
648 ; LARGE32-LABEL: L..C3:
649 ; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@gd
650 ; LARGE32-LABEL: L..C4:
651 ; LARGE32-NEXT: .tc .TIInit[TE],TIInit[TL]@m
652 ; LARGE32-LABEL: L..C5:
653 ; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]@gd
654 ; LARGE32-LABEL: L..C6:
655 ; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m
656 ; LARGE32-LABEL: L..C7:
657 ; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL]@gd
658 ; LARGE32-LABEL: L..C8:
659 ; LARGE32-NEXT: .tc GInit[TE],GInit[RW]
661 ; SMALL64-LABEL: .toc
662 ; SMALL64-LABEL: L..C0:
663 ; SMALL64-NEXT: .tc .TGUninit[TC],TGUninit[TL]@m
664 ; SMALL64-LABEL: L..C1:
665 ; SMALL64-NEXT: .tc TGUninit[TC],TGUninit[TL]@gd
666 ; SMALL64-LABEL: L..C2:
667 ; SMALL64-NEXT: .tc .TGInit[TC],TGInit[TL]@m
668 ; SMALL64-LABEL: L..C3:
669 ; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]@gd
670 ; SMALL64-LABEL: L..C4:
671 ; SMALL64-NEXT: .tc .TIInit[TC],TIInit[TL]@m
672 ; SMALL64-LABEL: L..C5:
673 ; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]@gd
674 ; SMALL64-LABEL: L..C6:
675 ; SMALL64-NEXT: .tc .TWInit[TC],TWInit[TL]@m
676 ; SMALL64-LABEL: L..C7:
677 ; SMALL64-NEXT: .tc TWInit[TC],TWInit[TL]@gd
678 ; SMALL64-LABEL: L..C8:
679 ; SMALL64-NEXT: .tc GInit[TC],GInit[RW]
681 ; LARGE64-LABEL: .toc
682 ; LARGE64-LABEL: L..C0:
683 ; LARGE64-NEXT: .tc .TGUninit[TE],TGUninit[TL]@m
684 ; LARGE64-LABEL: L..C1:
685 ; LARGE64-NEXT: .tc TGUninit[TE],TGUninit[TL]@gd
686 ; LARGE64-LABEL: L..C2:
687 ; LARGE64-NEXT: .tc .TGInit[TE],TGInit[TL]@m
688 ; LARGE64-LABEL: L..C3:
689 ; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@gd
690 ; LARGE64-LABEL: L..C4:
691 ; LARGE64-NEXT: .tc .TIInit[TE],TIInit[TL]@m
692 ; LARGE64-LABEL: L..C5:
693 ; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]@gd
694 ; LARGE64-LABEL: L..C6:
695 ; LARGE64-NEXT: .tc .TWInit[TE],TWInit[TL]@m
696 ; LARGE64-LABEL: L..C7:
697 ; LARGE64-NEXT: .tc TWInit[TE],TWInit[TL]@gd
698 ; LARGE64-LABEL: L..C8:
699 ; LARGE64-NEXT: .tc GInit[TE],GInit[RW]
702 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
703 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }