| blob | 65e2b7ef5294523a4a6bbcf6fe9ff6fad59526b1 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
3 ; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-AIX
5 ; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
6 ; RUN: -verify-machineinstrs -O2 -mattr=vsx < %s | \
7 ; RUN: FileCheck %s
9 define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) {
10 ; CHECK-AIX-LABEL: test_aix_splatimm:
11 ; CHECK-AIX: # %bb.0: # %bb
12 ; CHECK-AIX-NEXT: bclr 12, 20, 0
13 ; CHECK-AIX-NEXT: # %bb.1: # %bb3
14 ; CHECK-AIX-NEXT: srwi 4, 4, 16
15 ; CHECK-AIX-NEXT: srwi 5, 5, 16
16 ; CHECK-AIX-NEXT: mullw 4, 5, 4
17 ; CHECK-AIX-NEXT: lwz 5, 0(3)
18 ; CHECK-AIX-NEXT: slwi 3, 3, 8
19 ; CHECK-AIX-NEXT: neg 3, 3
20 ; CHECK-AIX-NEXT: srwi 5, 5, 1
21 ; CHECK-AIX-NEXT: sth 3, -32(1)
22 ; CHECK-AIX-NEXT: addi 3, 1, -32
23 ; CHECK-AIX-NEXT: mullw 4, 4, 5
24 ; CHECK-AIX-NEXT: li 5, 0
25 ; CHECK-AIX-NEXT: sth 5, -48(1)
26 ; CHECK-AIX-NEXT: neg 4, 4
27 ; CHECK-AIX-NEXT: sth 4, -16(1)
28 ; CHECK-AIX-NEXT: addi 4, 1, -48
29 ; CHECK-AIX-NEXT: lxvw4x 34, 0, 4
30 ; CHECK-AIX-NEXT: lxvw4x 35, 0, 3
31 ; CHECK-AIX-NEXT: addi 3, 1, -16
32 ; CHECK-AIX-NEXT: vmrghh 3, 2, 3
33 ; CHECK-AIX-NEXT: vsplth 4, 2, 0
34 ; CHECK-AIX-NEXT: vmrghw 3, 3, 4
35 ; CHECK-AIX-NEXT: lxvw4x 36, 0, 3
36 ; CHECK-AIX-NEXT: vmrghh 2, 4, 2
37 ; CHECK-AIX-NEXT: xxswapd 0, 35
38 ; CHECK-AIX-NEXT: xxsldwi 34, 0, 34, 2
39 ; CHECK-AIX-NEXT: vsplth 3, 2, 1
40 ; CHECK-AIX-NEXT: vsplth 2, 2, 4
41 ; CHECK-AIX-NEXT: stxvw4x 35, 0, 5
42 ; CHECK-AIX-NEXT: stxvw4x 34, 0, 3
43 ;
44 ; CHECK-LABEL: test_aix_splatimm:
45 ; CHECK: # %bb.0: # %bb
46 ; CHECK-NEXT: bclr 12, 20, 0
47 ; CHECK-NEXT: # %bb.1: # %bb3
48 ; CHECK-NEXT: srwi 4, 4, 16
49 ; CHECK-NEXT: srwi 5, 5, 16
50 ; CHECK-NEXT: slwi 3, 3, 8
51 ; CHECK-NEXT: mullw 4, 5, 4
52 ; CHECK-NEXT: li 5, 0
53 ; CHECK-NEXT: neg 3, 3
54 ; CHECK-NEXT: mtvsrd 34, 5
55 ; CHECK-NEXT: lwz 5, 0(3)
56 ; CHECK-NEXT: mtvsrd 35, 3
57 ; CHECK-NEXT: srwi 3, 5, 1
58 ; CHECK-NEXT: vsplth 4, 2, 3
59 ; CHECK-NEXT: mullw 3, 4, 3
60 ; CHECK-NEXT: vmrghh 3, 3, 2
61 ; CHECK-NEXT: neg 3, 3
62 ; CHECK-NEXT: mtvsrd 37, 3
63 ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
64 ; CHECK-NEXT: vmrglw 3, 4, 3
65 ; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
66 ; CHECK-NEXT: vmrghh 2, 2, 5
67 ; CHECK-NEXT: lvx 4, 0, 3
68 ; CHECK-NEXT: li 3, 0
69 ; CHECK-NEXT: vperm 2, 2, 3, 4
70 ; CHECK-NEXT: vsplth 3, 2, 6
71 ; CHECK-NEXT: vsplth 2, 2, 3
72 ; CHECK-NEXT: stvx 3, 0, 3
73 ; CHECK-NEXT: stvx 2, 0, 3
74 bb:
75 br i1 undef, label %bb22, label %bb3
77 bb3: ; preds = %bb
78 %i = insertelement <8 x i16> undef, i16 0, i32 0
79 %i4 = trunc i32 %arg to i16
80 %i5 = mul i16 %i4, -256
81 %i6 = insertelement <8 x i16> %i, i16 %i5, i32 1
82 %i7 = ashr i32 %arg1, 16
83 %i8 = ashr i32 %arg2, 16
84 %i9 = mul nsw i32 %i8, %i7
85 %i10 = insertelement <8 x i16> %i6, i16 0, i32 2
86 %i11 = insertelement <8 x i16> %i10, i16 0, i32 3
87 %i12 = load i32, i32* undef, align 4
88 %i13 = ashr i32 %i12, 1
89 %i14 = mul i32 %i9, %i13
90 %i15 = trunc i32 %i14 to i16
91 %i16 = sub i16 0, %i15
92 %i17 = insertelement <8 x i16> %i11, i16 %i16, i32 4
93 %i18 = insertelement <8 x i16> %i17, i16 0, i32 5
94 %i19 = bitcast <8 x i16> %i18 to <16 x i8>
95 %i20 = shufflevector <16 x i8> %i19, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
96 store <16 x i8> %i20, <16 x i8>* null, align 16
97 %i21 = shufflevector <16 x i8> %i19, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9>
98 store <16 x i8> %i21, <16 x i8>* undef, align 16
99 unreachable
101 bb22: ; preds = %bb
102 ret void
103 }