| blob | 86923667d912f1b786f40f0601ad1003eee0fc29 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc-unknown-linux -mattr=spe | FileCheck %s -check-prefix=SPE
4 define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
5 ; SPE-LABEL: test_f32_oeq_s:
6 ; SPE: # %bb.0:
7 ; SPE-NEXT: efscmpeq cr0, r5, r6
8 ; SPE-NEXT: bclr 12, gt, 0
9 ; SPE-NEXT: # %bb.1:
10 ; SPE-NEXT: ori r3, r4, 0
11 ; SPE-NEXT: blr
12 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oeq", metadata !"fpexcept.strict") #0
13 %res = select i1 %cond, i32 %a, i32 %b
14 ret i32 %res
15 }
17 define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
18 ; SPE-LABEL: test_f32_ogt_s:
19 ; SPE: # %bb.0:
20 ; SPE-NEXT: efscmpgt cr0, r5, r6
21 ; SPE-NEXT: bclr 12, gt, 0
22 ; SPE-NEXT: # %bb.1:
23 ; SPE-NEXT: ori r3, r4, 0
24 ; SPE-NEXT: blr
25 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ogt", metadata !"fpexcept.strict") #0
26 %res = select i1 %cond, i32 %a, i32 %b
27 ret i32 %res
28 }
30 define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
31 ; SPE-LABEL: test_f32_oge_s:
32 ; SPE: # %bb.0:
33 ; SPE-NEXT: efscmplt cr0, r5, r6
34 ; SPE-NEXT: efscmplt cr1, r5, r6
35 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
36 ; SPE-NEXT: efscmpeq cr0, r6, r6
37 ; SPE-NEXT: efscmpeq cr1, r5, r5
38 ; SPE-NEXT: crand 4*cr5+gt, 4*cr1+gt, gt
39 ; SPE-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
40 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
41 ; SPE-NEXT: # %bb.1:
42 ; SPE-NEXT: ori r3, r4, 0
43 ; SPE-NEXT: blr
44 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oge", metadata !"fpexcept.strict") #0
45 %res = select i1 %cond, i32 %a, i32 %b
46 ret i32 %res
47 }
49 define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
50 ; SPE-LABEL: test_f32_olt_s:
51 ; SPE: # %bb.0:
52 ; SPE-NEXT: efscmplt cr0, r5, r6
53 ; SPE-NEXT: bclr 12, gt, 0
54 ; SPE-NEXT: # %bb.1:
55 ; SPE-NEXT: ori r3, r4, 0
56 ; SPE-NEXT: blr
57 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"olt", metadata !"fpexcept.strict") #0
58 %res = select i1 %cond, i32 %a, i32 %b
59 ret i32 %res
60 }
62 define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
63 ; SPE-LABEL: test_f32_ole_s:
64 ; SPE: # %bb.0:
65 ; SPE-NEXT: efscmpgt cr0, r5, r6
66 ; SPE-NEXT: efscmpgt cr1, r5, r6
67 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
68 ; SPE-NEXT: efscmpeq cr0, r6, r6
69 ; SPE-NEXT: efscmpeq cr1, r5, r5
70 ; SPE-NEXT: crand 4*cr5+gt, 4*cr1+gt, gt
71 ; SPE-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
72 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
73 ; SPE-NEXT: # %bb.1:
74 ; SPE-NEXT: ori r3, r4, 0
75 ; SPE-NEXT: blr
76 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ole", metadata !"fpexcept.strict") #0
77 %res = select i1 %cond, i32 %a, i32 %b
78 ret i32 %res
79 }
81 define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
82 ; SPE-LABEL: test_f32_one_s:
83 ; SPE: # %bb.0:
84 ; SPE-NEXT: efscmplt cr0, r5, r6
85 ; SPE-NEXT: efscmpgt cr1, r5, r6
86 ; SPE-NEXT: cror 4*cr5+lt, 4*cr1+gt, gt
87 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
88 ; SPE-NEXT: # %bb.1:
89 ; SPE-NEXT: ori r3, r4, 0
90 ; SPE-NEXT: blr
91 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"one", metadata !"fpexcept.strict") #0
92 %res = select i1 %cond, i32 %a, i32 %b
93 ret i32 %res
94 }
96 define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
97 ; SPE-LABEL: test_f32_ord_s:
98 ; SPE: # %bb.0:
99 ; SPE-NEXT: efscmpeq cr0, r6, r6
100 ; SPE-NEXT: efscmpeq cr1, r5, r5
101 ; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
102 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
103 ; SPE-NEXT: # %bb.1:
104 ; SPE-NEXT: ori r3, r4, 0
105 ; SPE-NEXT: blr
106 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ord", metadata !"fpexcept.strict") #0
107 %res = select i1 %cond, i32 %a, i32 %b
108 ret i32 %res
109 }
111 define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
112 ; SPE-LABEL: test_f32_ueq_s:
113 ; SPE: # %bb.0:
114 ; SPE-NEXT: efscmplt cr0, r5, r6
115 ; SPE-NEXT: efscmpgt cr1, r5, r6
116 ; SPE-NEXT: cror 4*cr5+lt, 4*cr1+gt, gt
117 ; SPE-NEXT: bc 12, 4*cr5+lt, .LBB7_1
118 ; SPE-NEXT: blr
119 ; SPE-NEXT: .LBB7_1:
120 ; SPE-NEXT: addi r3, r4, 0
121 ; SPE-NEXT: blr
122 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ueq", metadata !"fpexcept.strict") #0
123 %res = select i1 %cond, i32 %a, i32 %b
124 ret i32 %res
125 }
127 define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
128 ; SPE-LABEL: test_f32_ugt_s:
129 ; SPE: # %bb.0:
130 ; SPE-NEXT: efscmpeq cr0, r6, r6
131 ; SPE-NEXT: efscmpeq cr1, r6, r6
132 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
133 ; SPE-NEXT: efscmpeq cr0, r5, r5
134 ; SPE-NEXT: efscmpeq cr1, r5, r5
135 ; SPE-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
136 ; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
137 ; SPE-NEXT: efscmpgt cr0, r5, r6
138 ; SPE-NEXT: cror 4*cr5+lt, gt, 4*cr5+lt
139 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
140 ; SPE-NEXT: # %bb.1:
141 ; SPE-NEXT: ori r3, r4, 0
142 ; SPE-NEXT: blr
143 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ugt", metadata !"fpexcept.strict") #0
144 %res = select i1 %cond, i32 %a, i32 %b
145 ret i32 %res
146 }
148 define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
149 ; SPE-LABEL: test_f32_uge_s:
150 ; SPE: # %bb.0:
151 ; SPE-NEXT: efscmplt cr0, r5, r6
152 ; SPE-NEXT: efscmplt cr1, r5, r6
153 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
154 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
155 ; SPE-NEXT: # %bb.1:
156 ; SPE-NEXT: ori r3, r4, 0
157 ; SPE-NEXT: blr
158 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uge", metadata !"fpexcept.strict") #0
159 %res = select i1 %cond, i32 %a, i32 %b
160 ret i32 %res
161 }
163 define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
164 ; SPE-LABEL: test_f32_ult_s:
165 ; SPE: # %bb.0:
166 ; SPE-NEXT: efscmpeq cr0, r6, r6
167 ; SPE-NEXT: efscmpeq cr1, r6, r6
168 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
169 ; SPE-NEXT: efscmpeq cr0, r5, r5
170 ; SPE-NEXT: efscmpeq cr1, r5, r5
171 ; SPE-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
172 ; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
173 ; SPE-NEXT: efscmplt cr0, r5, r6
174 ; SPE-NEXT: cror 4*cr5+lt, gt, 4*cr5+lt
175 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
176 ; SPE-NEXT: # %bb.1:
177 ; SPE-NEXT: ori r3, r4, 0
178 ; SPE-NEXT: blr
179 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ult", metadata !"fpexcept.strict") #0
180 %res = select i1 %cond, i32 %a, i32 %b
181 ret i32 %res
182 }
184 define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
185 ; SPE-LABEL: test_f32_ule_s:
186 ; SPE: # %bb.0:
187 ; SPE-NEXT: efscmpgt cr0, r5, r6
188 ; SPE-NEXT: efscmpgt cr1, r5, r6
189 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
190 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
191 ; SPE-NEXT: # %bb.1:
192 ; SPE-NEXT: ori r3, r4, 0
193 ; SPE-NEXT: blr
194 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ule", metadata !"fpexcept.strict") #0
195 %res = select i1 %cond, i32 %a, i32 %b
196 ret i32 %res
197 }
199 define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
200 ; SPE-LABEL: test_f32_une_s:
201 ; SPE: # %bb.0:
202 ; SPE-NEXT: efscmpeq cr0, r5, r6
203 ; SPE-NEXT: efscmpeq cr1, r5, r6
204 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
205 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
206 ; SPE-NEXT: # %bb.1:
207 ; SPE-NEXT: ori r3, r4, 0
208 ; SPE-NEXT: blr
209 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"une", metadata !"fpexcept.strict") #0
210 %res = select i1 %cond, i32 %a, i32 %b
211 ret i32 %res
212 }
214 define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
215 ; SPE-LABEL: test_f32_uno_s:
216 ; SPE: # %bb.0:
217 ; SPE-NEXT: efscmpeq cr0, r6, r6
218 ; SPE-NEXT: efscmpeq cr1, r6, r6
219 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
220 ; SPE-NEXT: efscmpeq cr0, r5, r5
221 ; SPE-NEXT: efscmpeq cr1, r5, r5
222 ; SPE-NEXT: crnor 4*cr5+gt, gt, 4*cr1+gt
223 ; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
224 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
225 ; SPE-NEXT: # %bb.1:
226 ; SPE-NEXT: ori r3, r4, 0
227 ; SPE-NEXT: blr
228 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uno", metadata !"fpexcept.strict") #0
229 %res = select i1 %cond, i32 %a, i32 %b
230 ret i32 %res
231 }
233 define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
234 ; SPE-LABEL: test_f64_oeq_s:
235 ; SPE: # %bb.0:
236 ; SPE-NEXT: evmergelo r7, r7, r8
237 ; SPE-NEXT: evmergelo r5, r5, r6
238 ; SPE-NEXT: efdcmpeq cr0, r5, r7
239 ; SPE-NEXT: bclr 12, gt, 0
240 ; SPE-NEXT: # %bb.1:
241 ; SPE-NEXT: ori r3, r4, 0
242 ; SPE-NEXT: blr
243 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oeq", metadata !"fpexcept.strict") #0
244 %res = select i1 %cond, i32 %a, i32 %b
245 ret i32 %res
246 }
248 define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
249 ; SPE-LABEL: test_f64_ogt_s:
250 ; SPE: # %bb.0:
251 ; SPE-NEXT: evmergelo r7, r7, r8
252 ; SPE-NEXT: evmergelo r5, r5, r6
253 ; SPE-NEXT: efdcmpgt cr0, r5, r7
254 ; SPE-NEXT: bclr 12, gt, 0
255 ; SPE-NEXT: # %bb.1:
256 ; SPE-NEXT: ori r3, r4, 0
257 ; SPE-NEXT: blr
258 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ogt", metadata !"fpexcept.strict") #0
259 %res = select i1 %cond, i32 %a, i32 %b
260 ret i32 %res
261 }
263 define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
264 ; SPE-LABEL: test_f64_oge_s:
265 ; SPE: # %bb.0:
266 ; SPE-NEXT: evmergelo r7, r7, r8
267 ; SPE-NEXT: evmergelo r5, r5, r6
268 ; SPE-NEXT: efdcmplt cr0, r5, r7
269 ; SPE-NEXT: efdcmplt cr1, r5, r7
270 ; SPE-NEXT: efdcmpeq cr5, r7, r7
271 ; SPE-NEXT: efdcmpeq cr6, r5, r5
272 ; SPE-NEXT: crnor 4*cr7+lt, gt, 4*cr1+gt
273 ; SPE-NEXT: crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
274 ; SPE-NEXT: crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
275 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
276 ; SPE-NEXT: # %bb.1:
277 ; SPE-NEXT: ori r3, r4, 0
278 ; SPE-NEXT: blr
279 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oge", metadata !"fpexcept.strict") #0
280 %res = select i1 %cond, i32 %a, i32 %b
281 ret i32 %res
282 }
284 define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
285 ; SPE-LABEL: test_f64_olt_s:
286 ; SPE: # %bb.0:
287 ; SPE-NEXT: evmergelo r7, r7, r8
288 ; SPE-NEXT: evmergelo r5, r5, r6
289 ; SPE-NEXT: efdcmplt cr0, r5, r7
290 ; SPE-NEXT: bclr 12, gt, 0
291 ; SPE-NEXT: # %bb.1:
292 ; SPE-NEXT: ori r3, r4, 0
293 ; SPE-NEXT: blr
294 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"olt", metadata !"fpexcept.strict") #0
295 %res = select i1 %cond, i32 %a, i32 %b
296 ret i32 %res
297 }
299 define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
300 ; SPE-LABEL: test_f64_ole_s:
301 ; SPE: # %bb.0:
302 ; SPE-NEXT: evmergelo r7, r7, r8
303 ; SPE-NEXT: evmergelo r5, r5, r6
304 ; SPE-NEXT: efdcmpgt cr0, r5, r7
305 ; SPE-NEXT: efdcmpgt cr1, r5, r7
306 ; SPE-NEXT: efdcmpeq cr5, r7, r7
307 ; SPE-NEXT: efdcmpeq cr6, r5, r5
308 ; SPE-NEXT: crnor 4*cr7+lt, gt, 4*cr1+gt
309 ; SPE-NEXT: crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
310 ; SPE-NEXT: crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
311 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
312 ; SPE-NEXT: # %bb.1:
313 ; SPE-NEXT: ori r3, r4, 0
314 ; SPE-NEXT: blr
315 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ole", metadata !"fpexcept.strict") #0
316 %res = select i1 %cond, i32 %a, i32 %b
317 ret i32 %res
318 }
320 define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
321 ; SPE-LABEL: test_f64_one_s:
322 ; SPE: # %bb.0:
323 ; SPE-NEXT: evmergelo r7, r7, r8
324 ; SPE-NEXT: evmergelo r5, r5, r6
325 ; SPE-NEXT: efdcmplt cr0, r5, r7
326 ; SPE-NEXT: efdcmpgt cr1, r5, r7
327 ; SPE-NEXT: cror 4*cr5+lt, 4*cr1+gt, gt
328 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
329 ; SPE-NEXT: # %bb.1:
330 ; SPE-NEXT: ori r3, r4, 0
331 ; SPE-NEXT: blr
332 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"one", metadata !"fpexcept.strict") #0
333 %res = select i1 %cond, i32 %a, i32 %b
334 ret i32 %res
335 }
337 define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
338 ; SPE-LABEL: test_f64_ord_s:
339 ; SPE: # %bb.0:
340 ; SPE-NEXT: evmergelo r5, r5, r6
341 ; SPE-NEXT: evmergelo r6, r7, r8
342 ; SPE-NEXT: efdcmpeq cr0, r6, r6
343 ; SPE-NEXT: efdcmpeq cr1, r5, r5
344 ; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
345 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
346 ; SPE-NEXT: # %bb.1:
347 ; SPE-NEXT: ori r3, r4, 0
348 ; SPE-NEXT: blr
349 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ord", metadata !"fpexcept.strict") #0
350 %res = select i1 %cond, i32 %a, i32 %b
351 ret i32 %res
352 }
354 define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
355 ; SPE-LABEL: test_f64_ueq_s:
356 ; SPE: # %bb.0:
357 ; SPE-NEXT: evmergelo r7, r7, r8
358 ; SPE-NEXT: evmergelo r5, r5, r6
359 ; SPE-NEXT: efdcmplt cr0, r5, r7
360 ; SPE-NEXT: efdcmpgt cr1, r5, r7
361 ; SPE-NEXT: cror 4*cr5+lt, 4*cr1+gt, gt
362 ; SPE-NEXT: bc 12, 4*cr5+lt, .LBB21_1
363 ; SPE-NEXT: blr
364 ; SPE-NEXT: .LBB21_1:
365 ; SPE-NEXT: addi r3, r4, 0
366 ; SPE-NEXT: blr
367 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ueq", metadata !"fpexcept.strict") #0
368 %res = select i1 %cond, i32 %a, i32 %b
369 ret i32 %res
370 }
372 define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
373 ; SPE-LABEL: test_f64_ugt_s:
374 ; SPE: # %bb.0:
375 ; SPE-NEXT: evmergelo r5, r5, r6
376 ; SPE-NEXT: evmergelo r6, r7, r8
377 ; SPE-NEXT: efdcmpeq cr0, r6, r6
378 ; SPE-NEXT: efdcmpeq cr1, r6, r6
379 ; SPE-NEXT: efdcmpeq cr5, r5, r5
380 ; SPE-NEXT: efdcmpeq cr6, r5, r5
381 ; SPE-NEXT: efdcmpgt cr7, r5, r6
382 ; SPE-NEXT: crnor 4*cr1+lt, gt, 4*cr1+gt
383 ; SPE-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
384 ; SPE-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
385 ; SPE-NEXT: cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
386 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
387 ; SPE-NEXT: # %bb.1:
388 ; SPE-NEXT: ori r3, r4, 0
389 ; SPE-NEXT: blr
390 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ugt", metadata !"fpexcept.strict") #0
391 %res = select i1 %cond, i32 %a, i32 %b
392 ret i32 %res
393 }
395 define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
396 ; SPE-LABEL: test_f64_uge_s:
397 ; SPE: # %bb.0:
398 ; SPE-NEXT: evmergelo r7, r7, r8
399 ; SPE-NEXT: evmergelo r5, r5, r6
400 ; SPE-NEXT: efdcmplt cr0, r5, r7
401 ; SPE-NEXT: efdcmplt cr1, r5, r7
402 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
403 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
404 ; SPE-NEXT: # %bb.1:
405 ; SPE-NEXT: ori r3, r4, 0
406 ; SPE-NEXT: blr
407 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uge", metadata !"fpexcept.strict") #0
408 %res = select i1 %cond, i32 %a, i32 %b
409 ret i32 %res
410 }
412 define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
413 ; SPE-LABEL: test_f64_ult_s:
414 ; SPE: # %bb.0:
415 ; SPE-NEXT: evmergelo r5, r5, r6
416 ; SPE-NEXT: evmergelo r6, r7, r8
417 ; SPE-NEXT: efdcmpeq cr0, r6, r6
418 ; SPE-NEXT: efdcmpeq cr1, r6, r6
419 ; SPE-NEXT: efdcmpeq cr5, r5, r5
420 ; SPE-NEXT: efdcmpeq cr6, r5, r5
421 ; SPE-NEXT: efdcmplt cr7, r5, r6
422 ; SPE-NEXT: crnor 4*cr1+lt, gt, 4*cr1+gt
423 ; SPE-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
424 ; SPE-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
425 ; SPE-NEXT: cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
426 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
427 ; SPE-NEXT: # %bb.1:
428 ; SPE-NEXT: ori r3, r4, 0
429 ; SPE-NEXT: blr
430 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ult", metadata !"fpexcept.strict") #0
431 %res = select i1 %cond, i32 %a, i32 %b
432 ret i32 %res
433 }
435 define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
436 ; SPE-LABEL: test_f64_ule_s:
437 ; SPE: # %bb.0:
438 ; SPE-NEXT: evmergelo r7, r7, r8
439 ; SPE-NEXT: evmergelo r5, r5, r6
440 ; SPE-NEXT: efdcmpgt cr0, r5, r7
441 ; SPE-NEXT: efdcmpgt cr1, r5, r7
442 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
443 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
444 ; SPE-NEXT: # %bb.1:
445 ; SPE-NEXT: ori r3, r4, 0
446 ; SPE-NEXT: blr
447 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ule", metadata !"fpexcept.strict") #0
448 %res = select i1 %cond, i32 %a, i32 %b
449 ret i32 %res
450 }
452 define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
453 ; SPE-LABEL: test_f64_une_s:
454 ; SPE: # %bb.0:
455 ; SPE-NEXT: evmergelo r7, r7, r8
456 ; SPE-NEXT: evmergelo r5, r5, r6
457 ; SPE-NEXT: efdcmpeq cr0, r5, r7
458 ; SPE-NEXT: efdcmpeq cr1, r5, r7
459 ; SPE-NEXT: crnor 4*cr5+lt, gt, 4*cr1+gt
460 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
461 ; SPE-NEXT: # %bb.1:
462 ; SPE-NEXT: ori r3, r4, 0
463 ; SPE-NEXT: blr
464 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"une", metadata !"fpexcept.strict") #0
465 %res = select i1 %cond, i32 %a, i32 %b
466 ret i32 %res
467 }
469 define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
470 ; SPE-LABEL: test_f64_uno_s:
471 ; SPE: # %bb.0:
472 ; SPE-NEXT: evmergelo r5, r5, r6
473 ; SPE-NEXT: evmergelo r6, r7, r8
474 ; SPE-NEXT: efdcmpeq cr0, r6, r6
475 ; SPE-NEXT: efdcmpeq cr1, r6, r6
476 ; SPE-NEXT: efdcmpeq cr5, r5, r5
477 ; SPE-NEXT: efdcmpeq cr6, r5, r5
478 ; SPE-NEXT: crnor 4*cr7+lt, gt, 4*cr1+gt
479 ; SPE-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
480 ; SPE-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr7+lt
481 ; SPE-NEXT: bclr 12, 4*cr5+lt, 0
482 ; SPE-NEXT: # %bb.1:
483 ; SPE-NEXT: ori r3, r4, 0
484 ; SPE-NEXT: blr
485 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uno", metadata !"fpexcept.strict") #0
486 %res = select i1 %cond, i32 %a, i32 %b
487 ret i32 %res
488 }
490 attributes #0 = { strictfp nounwind }
492 declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)
493 declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)