| blob | cb7bf512481681957beaeef962bbd67b18c721cb |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s
9 ; This test case tests spilling the CR EQ bit on Power10. On Power10, this is
10 ; achieved by setb %reg, %CRREG (eq bit) -> stw %reg, $FI instead of:
11 ; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.
13 ; Without fine-grained control over clobbering individual CR bits,
14 ; it is difficult to produce a concise test case that will ensure a specific
15 ; bit of any CR field is spilled. We need to test the spilling of a CR bit
16 ; other than the LT bit. Hence this test case is rather complex.
18 %0 = type { i32, %1*, %0*, [1 x i8], i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
19 %1 = type { %1*, %0*, i32 }
20 %2 = type { [200 x i8], [200 x i8], %3*, %3*, %4*, %4*, %4*, %4*, %4*, i64 }
21 %3 = type { i64, i32, %3*, %3*, %3*, %3*, %4*, %4*, %4*, %4*, i64, i32, i32 }
22 %4 = type { i32, i64, %3*, %3*, i16, %4*, %4*, i64, i64 }
24 define dso_local double @P10_Spill_CR_EQ(%2* %arg) local_unnamed_addr #0 {
25 ; CHECK-LABEL: P10_Spill_CR_EQ:
26 ; CHECK: # %bb.0: # %bb
27 ; CHECK-NEXT: mfcr r12
28 ; CHECK-NEXT: stw r12, 8(r1)
29 ; CHECK-NEXT: ld r3, 0(r3)
30 ; CHECK-NEXT: ld r4, 0(0)
31 ; CHECK-NEXT: ld r5, 56(0)
32 ; CHECK-NEXT: cmpdi cr1, r3, 0
33 ; CHECK-NEXT: cmpdi cr4, r4, 0
34 ; CHECK-NEXT: cmpdi cr6, r5, 0
35 ; CHECK-NEXT: cmpldi r3, 0
36 ; CHECK-NEXT: beq cr0, .LBB0_3
37 ; CHECK-NEXT: # %bb.1: # %bb10
38 ; CHECK-NEXT: lwz r3, 0(r3)
39 ; CHECK-NEXT: bc 12, 4*cr4+eq, .LBB0_4
40 ; CHECK-NEXT: .LBB0_2: # %bb14
41 ; CHECK-NEXT: lwz r5, 0(r3)
42 ; CHECK-NEXT: b .LBB0_5
43 ; CHECK-NEXT: .LBB0_3:
44 ; CHECK-NEXT: # implicit-def: $r3
45 ; CHECK-NEXT: bc 4, 4*cr4+eq, .LBB0_2
46 ; CHECK-NEXT: .LBB0_4:
47 ; CHECK-NEXT: # implicit-def: $r5
48 ; CHECK-NEXT: .LBB0_5: # %bb16
49 ; CHECK-NEXT: mfocrf r4, 64
50 ; CHECK-NEXT: crnot 4*cr2+un, 4*cr1+eq
51 ; CHECK-NEXT: crnot 4*cr5+lt, 4*cr6+eq
52 ; CHECK-NEXT: rotlwi r4, r4, 4
53 ; CHECK-NEXT: stw r4, -4(r1)
54 ; CHECK-NEXT: bc 12, 4*cr6+eq, .LBB0_7
55 ; CHECK-NEXT: # %bb.6: # %bb18
56 ; CHECK-NEXT: lwz r4, 0(r3)
57 ; CHECK-NEXT: b .LBB0_8
58 ; CHECK-NEXT: .LBB0_7:
59 ; CHECK-NEXT: # implicit-def: $r4
60 ; CHECK-NEXT: .LBB0_8: # %bb20
61 ; CHECK-NEXT: cmpwi r3, -1
62 ; CHECK-NEXT: cmpwi cr3, r4, -1
63 ; CHECK-NEXT: cmpwi cr7, r3, 0
64 ; CHECK-NEXT: cmpwi cr1, r4, 0
65 ; CHECK-NEXT: # implicit-def: $x3
66 ; CHECK-NEXT: crand 4*cr5+eq, gt, 4*cr2+un
67 ; CHECK-NEXT: crand 4*cr5+gt, 4*cr3+gt, 4*cr5+lt
68 ; CHECK-NEXT: setnbc r4, 4*cr5+eq
69 ; CHECK-NEXT: stw r4, -20(r1)
70 ; CHECK-NEXT: bc 4, 4*cr5+eq, .LBB0_10
71 ; CHECK-NEXT: # %bb.9: # %bb34
72 ; CHECK-NEXT: ld r3, 0(r3)
73 ; CHECK-NEXT: .LBB0_10: # %bb36
74 ; CHECK-NEXT: mfocrf r4, 2
75 ; CHECK-NEXT: cmpwi cr3, r5, 0
76 ; CHECK-NEXT: rotlwi r4, r4, 24
77 ; CHECK-NEXT: stw r4, -12(r1)
78 ; CHECK-NEXT: # implicit-def: $x4
79 ; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_12
80 ; CHECK-NEXT: # %bb.11: # %bb38
81 ; CHECK-NEXT: ld r4, 0(r3)
82 ; CHECK-NEXT: .LBB0_12: # %bb40
83 ; CHECK-NEXT: mcrf cr6, cr4
84 ; CHECK-NEXT: crnot 4*cr4+eq, 4*cr4+eq
85 ; CHECK-NEXT: crand 4*cr4+lt, 4*cr7+lt, 4*cr2+un
86 ; CHECK-NEXT: # implicit-def: $x6
87 ; CHECK-NEXT: crand 4*cr4+gt, 4*cr1+lt, 4*cr5+lt
88 ; CHECK-NEXT: bc 4, 4*cr4+gt, .LBB0_14
89 ; CHECK-NEXT: # %bb.13: # %bb48
90 ; CHECK-NEXT: ld r6, 0(r3)
91 ; CHECK-NEXT: .LBB0_14: # %bb50
92 ; CHECK-NEXT: cmpwi r5, -1
93 ; CHECK-NEXT: crand 4*cr4+un, 4*cr3+lt, 4*cr4+eq
94 ; CHECK-NEXT: # implicit-def: $r5
95 ; CHECK-NEXT: bc 4, 4*cr4+lt, .LBB0_16
96 ; CHECK-NEXT: # %bb.15: # %bb52
97 ; CHECK-NEXT: lwz r5, 0(r3)
98 ; CHECK-NEXT: .LBB0_16: # %bb54
99 ; CHECK-NEXT: setnbc r7, 4*cr5+gt
100 ; CHECK-NEXT: stw r7, -16(r1)
101 ; CHECK-NEXT: mfocrf r7, 2
102 ; CHECK-NEXT: rotlwi r7, r7, 24
103 ; CHECK-NEXT: stw r7, -8(r1)
104 ; CHECK-NEXT: # implicit-def: $r7
105 ; CHECK-NEXT: bc 4, 4*cr4+un, .LBB0_18
106 ; CHECK-NEXT: # %bb.17: # %bb56
107 ; CHECK-NEXT: lwz r7, 0(r3)
108 ; CHECK-NEXT: .LBB0_18: # %bb58
109 ; CHECK-NEXT: crand 4*cr5+gt, 4*cr7+eq, 4*cr2+un
110 ; CHECK-NEXT: mcrf cr2, cr1
111 ; CHECK-NEXT: cmpwi cr1, r5, 1
112 ; CHECK-NEXT: crand lt, gt, 4*cr4+eq
113 ; CHECK-NEXT: # implicit-def: $x5
114 ; CHECK-NEXT: setnbc r8, 4*cr5+gt
115 ; CHECK-NEXT: crand 4*cr5+lt, 4*cr2+eq, 4*cr5+lt
116 ; CHECK-NEXT: crand 4*cr4+eq, 4*cr3+eq, 4*cr4+eq
117 ; CHECK-NEXT: crand gt, 4*cr1+lt, 4*cr4+lt
118 ; CHECK-NEXT: stw r8, -24(r1)
119 ; CHECK-NEXT: setnbc r8, 4*cr5+lt
120 ; CHECK-NEXT: cmpwi cr5, r7, 1
121 ; CHECK-NEXT: stw r8, -28(r1)
122 ; CHECK-NEXT: lwz r6, 92(r6)
123 ; CHECK-NEXT: crand eq, 4*cr5+lt, 4*cr4+un
124 ; CHECK-NEXT: cmpwi cr6, r6, 1
125 ; CHECK-NEXT: crand un, 4*cr6+lt, 4*cr4+gt
126 ; CHECK-NEXT: bc 4, gt, .LBB0_20
127 ; CHECK-NEXT: # %bb.19: # %bb68
128 ; CHECK-NEXT: ld r5, 0(r3)
129 ; CHECK-NEXT: .LBB0_20: # %bb70
130 ; CHECK-NEXT: lwz r7, -20(r1)
131 ; CHECK-NEXT: # implicit-def: $cr5lt
132 ; CHECK-NEXT: mfocrf r6, 4
133 ; CHECK-NEXT: xxlxor f2, f2, f2
134 ; CHECK-NEXT: rlwimi r6, r7, 12, 20, 20
135 ; CHECK-NEXT: mtocrf 4, r6
136 ; CHECK-NEXT: ld r6, 0(r3)
137 ; CHECK-NEXT: crandc 4*cr5+gt, lt, 4*cr3+eq
138 ; CHECK-NEXT: lwz r8, -16(r1)
139 ; CHECK-NEXT: # implicit-def: $cr5eq
140 ; CHECK-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr7+eq
141 ; CHECK-NEXT: mfocrf r7, 4
142 ; CHECK-NEXT: rlwimi r7, r8, 10, 22, 22
143 ; CHECK-NEXT: mtocrf 4, r7
144 ; CHECK-NEXT: lwz r7, -24(r1)
145 ; CHECK-NEXT: # implicit-def: $cr5un
146 ; CHECK-NEXT: lwz r9, -28(r1)
147 ; CHECK-NEXT: crandc 4*cr5+eq, 4*cr5+eq, 4*cr2+eq
148 ; CHECK-NEXT: isel r3, r3, r5, 4*cr5+lt
149 ; CHECK-NEXT: crnor 4*cr5+lt, gt, 4*cr5+lt
150 ; CHECK-NEXT: crnor 4*cr5+gt, eq, 4*cr5+gt
151 ; CHECK-NEXT: crnor 4*cr5+eq, un, 4*cr5+eq
152 ; CHECK-NEXT: mfocrf r5, 4
153 ; CHECK-NEXT: rlwimi r5, r7, 9, 23, 23
154 ; CHECK-NEXT: setbc r7, 4*cr4+eq
155 ; CHECK-NEXT: mtocrf 4, r5
156 ; CHECK-NEXT: setbc r5, 4*cr5+un
157 ; CHECK-NEXT: # implicit-def: $cr5un
158 ; CHECK-NEXT: mfocrf r8, 4
159 ; CHECK-NEXT: add r5, r7, r5
160 ; CHECK-NEXT: rlwimi r8, r9, 9, 23, 23
161 ; CHECK-NEXT: lwz r9, -4(r1)
162 ; CHECK-NEXT: mtocrf 4, r8
163 ; CHECK-NEXT: mtocrf 128, r9
164 ; CHECK-NEXT: lwz r9, -8(r1)
165 ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
166 ; CHECK-NEXT: setbc r8, 4*cr5+un
167 ; CHECK-NEXT: isel r6, 0, r6, 4*cr5+gt
168 ; CHECK-NEXT: isel r4, 0, r4, 4*cr5+eq
169 ; CHECK-NEXT: add r5, r8, r5
170 ; CHECK-NEXT: iseleq r3, 0, r3
171 ; CHECK-NEXT: mtfprd f0, r5
172 ; CHECK-NEXT: mtocrf 128, r9
173 ; CHECK-NEXT: lwz r9, -12(r1)
174 ; CHECK-NEXT: lwz r12, 8(r1)
175 ; CHECK-NEXT: xscvsxddp f0, f0
176 ; CHECK-NEXT: iseleq r6, 0, r6
177 ; CHECK-NEXT: mtocrf 128, r9
178 ; CHECK-NEXT: add r3, r6, r3
179 ; CHECK-NEXT: mtocrf 32, r12
180 ; CHECK-NEXT: mtocrf 16, r12
181 ; CHECK-NEXT: mtocrf 8, r12
182 ; CHECK-NEXT: iseleq r4, 0, r4
183 ; CHECK-NEXT: add r3, r4, r3
184 ; CHECK-NEXT: xsmuldp f0, f0, f2
185 ; CHECK-NEXT: mtfprd f1, r3
186 ; CHECK-NEXT: xscvsxddp f1, f1
187 ; CHECK-NEXT: xsadddp f1, f0, f1
188 ; CHECK-NEXT: blr
189 bb:
190 %tmp = getelementptr inbounds %4, %4* null, i64 undef, i32 7
191 %tmp1 = load i64, i64* undef, align 8
192 %tmp2 = load i64, i64* null, align 8
193 %tmp3 = load i64, i64* %tmp, align 8
194 %tmp4 = icmp eq i64 %tmp1, 0
195 %tmp5 = icmp eq i64 %tmp2, 0
196 %tmp6 = icmp eq i64 %tmp3, 0
197 %tmp7 = xor i1 %tmp4, true
198 %tmp8 = xor i1 %tmp5, true
199 %tmp9 = xor i1 %tmp6, true
200 br i1 %tmp4, label %bb12, label %bb10
202 bb10: ; preds = %bb
203 %tmp11 = load i32, i32* undef, align 8
204 br label %bb12
206 bb12: ; preds = %bb10, %bb
207 %tmp13 = phi i32 [ undef, %bb ], [ %tmp11, %bb10 ]
208 br i1 %tmp5, label %bb16, label %bb14
210 bb14: ; preds = %bb12
211 %tmp15 = load i32, i32* undef, align 8
212 br label %bb16
214 bb16: ; preds = %bb14, %bb12
215 %tmp17 = phi i32 [ undef, %bb12 ], [ %tmp15, %bb14 ]
216 br i1 %tmp6, label %bb20, label %bb18
218 bb18: ; preds = %bb16
219 %tmp19 = load i32, i32* undef, align 8
220 br label %bb20
222 bb20: ; preds = %bb18, %bb16
223 %tmp21 = phi i32 [ undef, %bb16 ], [ %tmp19, %bb18 ]
224 %tmp22 = icmp slt i32 %tmp13, 0
225 %tmp23 = icmp slt i32 %tmp17, 0
226 %tmp24 = icmp slt i32 %tmp21, 0
227 %tmp25 = icmp eq i32 %tmp13, 0
228 %tmp26 = icmp eq i32 %tmp17, 0
229 %tmp27 = icmp eq i32 %tmp21, 0
230 %tmp28 = xor i1 %tmp22, true
231 %tmp29 = xor i1 %tmp23, true
232 %tmp30 = xor i1 %tmp24, true
233 %tmp31 = and i1 %tmp28, %tmp7
234 %tmp32 = and i1 %tmp29, %tmp8
235 %tmp33 = and i1 %tmp30, %tmp9
236 br i1 %tmp31, label %bb34, label %bb36
238 bb34: ; preds = %bb20
239 %tmp35 = load i64, i64* undef, align 8
240 br label %bb36
242 bb36: ; preds = %bb34, %bb20
243 %tmp37 = phi i64 [ undef, %bb20 ], [ %tmp35, %bb34 ]
244 br i1 %tmp33, label %bb38, label %bb40
246 bb38: ; preds = %bb36
247 %tmp39 = load i64, i64* undef, align 8
248 br label %bb40
250 bb40: ; preds = %bb38, %bb36
251 %tmp41 = phi i64 [ undef, %bb36 ], [ %tmp39, %bb38 ]
252 %tmp42 = and i1 %tmp25, %tmp7
253 %tmp43 = and i1 %tmp26, %tmp8
254 %tmp44 = and i1 %tmp27, %tmp9
255 %tmp45 = and i1 %tmp22, %tmp7
256 %tmp46 = and i1 %tmp23, %tmp8
257 %tmp47 = and i1 %tmp24, %tmp9
258 br i1 %tmp47, label %bb48, label %bb50
260 bb48: ; preds = %bb40
261 %tmp49 = load %3*, %3** undef, align 8
262 br label %bb50
264 bb50: ; preds = %bb48, %bb40
265 %tmp51 = phi %3* [ undef, %bb40 ], [ %tmp49, %bb48 ]
266 br i1 %tmp45, label %bb52, label %bb54
268 bb52: ; preds = %bb50
269 %tmp53 = load i32, i32* undef, align 8
270 br label %bb54
272 bb54: ; preds = %bb52, %bb50
273 %tmp55 = phi i32 [ undef, %bb50 ], [ %tmp53, %bb52 ]
274 br i1 %tmp46, label %bb56, label %bb58
276 bb56: ; preds = %bb54
277 %tmp57 = load i32, i32* undef, align 8
278 br label %bb58
280 bb58: ; preds = %bb56, %bb54
281 %tmp59 = phi i32 [ undef, %bb54 ], [ %tmp57, %bb56 ]
282 %tmp60 = getelementptr inbounds %3, %3* %tmp51, i64 0, i32 12
283 %tmp61 = load i32, i32* %tmp60, align 8
284 %tmp62 = icmp slt i32 %tmp55, 1
285 %tmp63 = icmp slt i32 %tmp59, 1
286 %tmp64 = icmp slt i32 %tmp61, 1
287 %tmp65 = and i1 %tmp62, %tmp45
288 %tmp66 = and i1 %tmp63, %tmp46
289 %tmp67 = and i1 %tmp64, %tmp47
290 br i1 %tmp65, label %bb68, label %bb70
292 bb68: ; preds = %bb58
293 %tmp69 = load i64, i64* undef, align 8
294 br label %bb70
296 bb70: ; preds = %bb68, %bb58
297 %tmp71 = phi i64 [ undef, %bb58 ], [ %tmp69, %bb68 ]
298 %tmp72 = load i64, i64* undef, align 8
299 %tmp73 = xor i1 %tmp25, true
300 %tmp74 = xor i1 %tmp26, true
301 %tmp75 = xor i1 %tmp27, true
302 %tmp76 = and i1 %tmp31, %tmp73
303 %tmp77 = and i1 %tmp32, %tmp74
304 %tmp78 = and i1 %tmp33, %tmp75
305 %tmp79 = select i1 %tmp76, i64 %tmp37, i64 %tmp71
306 %tmp80 = select i1 %tmp77, i64 undef, i64 %tmp72
307 %tmp81 = select i1 %tmp78, i64 %tmp41, i64 undef
308 %tmp82 = or i1 %tmp65, %tmp76
309 %tmp83 = or i1 %tmp66, %tmp77
310 %tmp84 = or i1 %tmp67, %tmp78
311 %tmp85 = zext i1 %tmp42 to i64
312 %tmp86 = add i64 0, %tmp85
313 %tmp87 = zext i1 %tmp43 to i64
314 %tmp88 = add i64 0, %tmp87
315 %tmp89 = zext i1 %tmp44 to i64
316 %tmp90 = add i64 0, %tmp89
317 %tmp91 = select i1 %tmp82, i64 %tmp79, i64 0
318 %tmp92 = add i64 0, %tmp91
319 %tmp93 = select i1 %tmp83, i64 %tmp80, i64 0
320 %tmp94 = add i64 0, %tmp93
321 %tmp95 = select i1 %tmp84, i64 %tmp81, i64 0
322 %tmp96 = add i64 0, %tmp95
323 %tmp97 = select i1 %tmp42, i64 undef, i64 %tmp92
324 %tmp98 = select i1 %tmp43, i64 undef, i64 %tmp94
325 %tmp99 = select i1 %tmp44, i64 undef, i64 %tmp96
326 %tmp100 = select i1 %tmp4, i64 0, i64 %tmp97
327 %tmp101 = select i1 %tmp5, i64 0, i64 %tmp98
328 %tmp102 = select i1 %tmp6, i64 0, i64 %tmp99
329 %tmp103 = add i64 %tmp88, %tmp86
330 %tmp104 = add i64 %tmp90, %tmp103
331 %tmp105 = add i64 0, %tmp104
332 %tmp106 = add i64 %tmp101, %tmp100
333 %tmp107 = add i64 %tmp102, %tmp106
334 %tmp108 = add i64 0, %tmp107
335 %tmp109 = sitofp i64 %tmp105 to double
336 %tmp110 = sitofp i64 %tmp108 to double
337 %tmp111 = fmul double %tmp109, 0.000000e+00
338 %tmp112 = fadd double %tmp111, %tmp110
339 ret double %tmp112
340 }