| blob | f6472d356006c9bda5ea3004bfec19ed0c54dc27 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
3 ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
4 ; RUN: < %s | FileCheck %s
6 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
7 ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \
8 ; RUN: < %s | FileCheck %s --check-prefix=P9BE
10 ; Function Attrs: norecurse nounwind readonly
11 define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
12 ; CHECK-LABEL: test_pre_inc_disable_1:
13 ; CHECK: # %bb.0: # %entry
14 ; CHECK-NEXT: lxsd v5, 0(r5)
15 ; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha
16 ; CHECK-NEXT: xxlxor v3, v3, v3
17 ; CHECK-NEXT: li r6, 0
18 ; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l
19 ; CHECK-NEXT: lxv v2, 0(r5)
20 ; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha
21 ; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l
22 ; CHECK-NEXT: lxv v4, 0(r5)
23 ; CHECK-NEXT: li r5, 4
24 ; CHECK-NEXT: vperm v0, v3, v5, v2
25 ; CHECK-NEXT: mtctr r5
26 ; CHECK-NEXT: li r5, 0
27 ; CHECK-NEXT: vperm v1, v3, v5, v4
28 ; CHECK-NEXT: xvnegsp v5, v0
29 ; CHECK-NEXT: xvnegsp v0, v1
30 ; CHECK-NEXT: .p2align 4
31 ; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader
32 ; CHECK-NEXT: #
33 ; CHECK-NEXT: lxsd v1, 0(r3)
34 ; CHECK-NEXT: add r7, r3, r4
35 ; CHECK-NEXT: vperm v6, v3, v1, v4
36 ; CHECK-NEXT: vperm v1, v3, v1, v2
37 ; CHECK-NEXT: xvnegsp v1, v1
38 ; CHECK-NEXT: xvnegsp v6, v6
39 ; CHECK-NEXT: vabsduw v1, v1, v5
40 ; CHECK-NEXT: vabsduw v6, v6, v0
41 ; CHECK-NEXT: vadduwm v1, v6, v1
42 ; CHECK-NEXT: xxswapd v6, v1
43 ; CHECK-NEXT: vadduwm v1, v1, v6
44 ; CHECK-NEXT: xxspltw v6, v1, 2
45 ; CHECK-NEXT: vadduwm v1, v1, v6
46 ; CHECK-NEXT: lxsdx v6, r3, r4
47 ; CHECK-NEXT: vextuwrx r3, r5, v1
48 ; CHECK-NEXT: vperm v7, v3, v6, v4
49 ; CHECK-NEXT: vperm v6, v3, v6, v2
50 ; CHECK-NEXT: add r6, r3, r6
51 ; CHECK-NEXT: add r3, r7, r4
52 ; CHECK-NEXT: xvnegsp v6, v6
53 ; CHECK-NEXT: xvnegsp v1, v7
54 ; CHECK-NEXT: vabsduw v6, v6, v5
55 ; CHECK-NEXT: vabsduw v1, v1, v0
56 ; CHECK-NEXT: vadduwm v1, v1, v6
57 ; CHECK-NEXT: xxswapd v6, v1
58 ; CHECK-NEXT: vadduwm v1, v1, v6
59 ; CHECK-NEXT: xxspltw v6, v1, 2
60 ; CHECK-NEXT: vadduwm v1, v1, v6
61 ; CHECK-NEXT: vextuwrx r8, r5, v1
62 ; CHECK-NEXT: add r6, r8, r6
63 ; CHECK-NEXT: bdnz .LBB0_1
64 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
65 ; CHECK-NEXT: extsw r3, r6
66 ; CHECK-NEXT: blr
67 ;
68 ; P9BE-LABEL: test_pre_inc_disable_1:
69 ; P9BE: # %bb.0: # %entry
70 ; P9BE-NEXT: lxsd v5, 0(r5)
71 ; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha
72 ; P9BE-NEXT: xxlxor v3, v3, v3
73 ; P9BE-NEXT: li r6, 0
74 ; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l
75 ; P9BE-NEXT: lxv v2, 0(r5)
76 ; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha
77 ; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l
78 ; P9BE-NEXT: lxv v4, 0(r5)
79 ; P9BE-NEXT: li r5, 4
80 ; P9BE-NEXT: vperm v0, v3, v5, v2
81 ; P9BE-NEXT: mtctr r5
82 ; P9BE-NEXT: li r5, 0
83 ; P9BE-NEXT: vperm v1, v3, v5, v4
84 ; P9BE-NEXT: xvnegsp v5, v0
85 ; P9BE-NEXT: xvnegsp v0, v1
86 ; P9BE-NEXT: .p2align 4
87 ; P9BE-NEXT: .LBB0_1: # %for.cond1.preheader
88 ; P9BE-NEXT: #
89 ; P9BE-NEXT: lxsd v1, 0(r3)
90 ; P9BE-NEXT: add r7, r3, r4
91 ; P9BE-NEXT: vperm v6, v3, v1, v4
92 ; P9BE-NEXT: vperm v1, v3, v1, v2
93 ; P9BE-NEXT: xvnegsp v1, v1
94 ; P9BE-NEXT: xvnegsp v6, v6
95 ; P9BE-NEXT: vabsduw v1, v1, v5
96 ; P9BE-NEXT: vabsduw v6, v6, v0
97 ; P9BE-NEXT: vadduwm v1, v6, v1
98 ; P9BE-NEXT: xxswapd v6, v1
99 ; P9BE-NEXT: vadduwm v1, v1, v6
100 ; P9BE-NEXT: xxspltw v6, v1, 1
101 ; P9BE-NEXT: vadduwm v1, v1, v6
102 ; P9BE-NEXT: lxsdx v6, r3, r4
103 ; P9BE-NEXT: vextuwlx r3, r5, v1
104 ; P9BE-NEXT: vperm v7, v3, v6, v4
105 ; P9BE-NEXT: vperm v6, v3, v6, v2
106 ; P9BE-NEXT: add r6, r3, r6
107 ; P9BE-NEXT: add r3, r7, r4
108 ; P9BE-NEXT: xvnegsp v6, v6
109 ; P9BE-NEXT: xvnegsp v1, v7
110 ; P9BE-NEXT: vabsduw v6, v6, v5
111 ; P9BE-NEXT: vabsduw v1, v1, v0
112 ; P9BE-NEXT: vadduwm v1, v1, v6
113 ; P9BE-NEXT: xxswapd v6, v1
114 ; P9BE-NEXT: vadduwm v1, v1, v6
115 ; P9BE-NEXT: xxspltw v6, v1, 1
116 ; P9BE-NEXT: vadduwm v1, v1, v6
117 ; P9BE-NEXT: vextuwlx r8, r5, v1
118 ; P9BE-NEXT: add r6, r8, r6
119 ; P9BE-NEXT: bdnz .LBB0_1
120 ; P9BE-NEXT: # %bb.2: # %for.cond.cleanup
121 ; P9BE-NEXT: extsw r3, r6
122 ; P9BE-NEXT: blr
123 entry:
124 %idx.ext = sext i32 %i_stride_pix1 to i64
125 %0 = bitcast i8* %pix2 to <8 x i8>*
126 %1 = load <8 x i8>, <8 x i8>* %0, align 1
127 %2 = zext <8 x i8> %1 to <8 x i32>
128 br label %for.cond1.preheader
130 for.cond1.preheader: ; preds = %for.cond1.preheader, %entry
131 %y.024 = phi i32 [ 0, %entry ], [ %inc9.1, %for.cond1.preheader ]
132 %i_sum.023 = phi i32 [ 0, %entry ], [ %op.extra.1, %for.cond1.preheader ]
133 %pix1.addr.022 = phi i8* [ %pix1, %entry ], [ %add.ptr.1, %for.cond1.preheader ]
134 %3 = bitcast i8* %pix1.addr.022 to <8 x i8>*
135 %4 = load <8 x i8>, <8 x i8>* %3, align 1
136 %5 = zext <8 x i8> %4 to <8 x i32>
137 %6 = sub nsw <8 x i32> %5, %2
138 %7 = icmp slt <8 x i32> %6, zeroinitializer
139 %8 = sub nsw <8 x i32> zeroinitializer, %6
140 %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
141 %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
142 %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
143 %rdx.shuf32 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
144 %bin.rdx33 = add nsw <8 x i32> %bin.rdx, %rdx.shuf32
145 %rdx.shuf34 = shufflevector <8 x i32> %bin.rdx33, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
146 %bin.rdx35 = add nsw <8 x i32> %bin.rdx33, %rdx.shuf34
147 %10 = extractelement <8 x i32> %bin.rdx35, i32 0
148 %op.extra = add nsw i32 %10, %i_sum.023
149 %add.ptr = getelementptr inbounds i8, i8* %pix1.addr.022, i64 %idx.ext
150 %11 = bitcast i8* %add.ptr to <8 x i8>*
151 %12 = load <8 x i8>, <8 x i8>* %11, align 1
152 %13 = zext <8 x i8> %12 to <8 x i32>
153 %14 = sub nsw <8 x i32> %13, %2
154 %15 = icmp slt <8 x i32> %14, zeroinitializer
155 %16 = sub nsw <8 x i32> zeroinitializer, %14
156 %17 = select <8 x i1> %15, <8 x i32> %16, <8 x i32> %14
157 %rdx.shuf.1 = shufflevector <8 x i32> %17, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
158 %bin.rdx.1 = add nsw <8 x i32> %17, %rdx.shuf.1
159 %rdx.shuf32.1 = shufflevector <8 x i32> %bin.rdx.1, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
160 %bin.rdx33.1 = add nsw <8 x i32> %bin.rdx.1, %rdx.shuf32.1
161 %rdx.shuf34.1 = shufflevector <8 x i32> %bin.rdx33.1, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
162 %bin.rdx35.1 = add nsw <8 x i32> %bin.rdx33.1, %rdx.shuf34.1
163 %18 = extractelement <8 x i32> %bin.rdx35.1, i32 0
164 %op.extra.1 = add nsw i32 %18, %op.extra
165 %add.ptr.1 = getelementptr inbounds i8, i8* %add.ptr, i64 %idx.ext
166 %inc9.1 = add nuw nsw i32 %y.024, 2
167 %exitcond.1 = icmp eq i32 %inc9.1, 8
168 br i1 %exitcond.1, label %for.cond.cleanup, label %for.cond1.preheader
170 for.cond.cleanup: ; preds = %for.cond1.preheader
171 ret i32 %op.extra.1
172 }
174 ; Function Attrs: norecurse nounwind readonly
175 define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
176 ; CHECK-LABEL: test_pre_inc_disable_2:
177 ; CHECK: # %bb.0: # %entry
178 ; CHECK-NEXT: lxsd v2, 0(r3)
179 ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
180 ; CHECK-NEXT: lxsd v1, 0(r4)
181 ; CHECK-NEXT: xxlxor v3, v3, v3
182 ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
183 ; CHECK-NEXT: lxv v4, 0(r3)
184 ; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha
185 ; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l
186 ; CHECK-NEXT: lxv v0, 0(r3)
187 ; CHECK-NEXT: li r3, 0
188 ; CHECK-NEXT: vperm v5, v3, v2, v4
189 ; CHECK-NEXT: vperm v2, v3, v2, v0
190 ; CHECK-NEXT: vperm v0, v3, v1, v0
191 ; CHECK-NEXT: vperm v3, v3, v1, v4
192 ; CHECK-NEXT: vabsduw v2, v2, v0
193 ; CHECK-NEXT: vabsduw v3, v5, v3
194 ; CHECK-NEXT: vadduwm v2, v3, v2
195 ; CHECK-NEXT: xxswapd v3, v2
196 ; CHECK-NEXT: vadduwm v2, v2, v3
197 ; CHECK-NEXT: xxspltw v3, v2, 2
198 ; CHECK-NEXT: vadduwm v2, v2, v3
199 ; CHECK-NEXT: vextuwrx r3, r3, v2
200 ; CHECK-NEXT: extsw r3, r3
201 ; CHECK-NEXT: blr
202 ;
203 ; P9BE-LABEL: test_pre_inc_disable_2:
204 ; P9BE: # %bb.0: # %entry
205 ; P9BE-NEXT: lxsd v2, 0(r3)
206 ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
207 ; P9BE-NEXT: lxsd v1, 0(r4)
208 ; P9BE-NEXT: xxlxor v3, v3, v3
209 ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
210 ; P9BE-NEXT: lxv v4, 0(r3)
211 ; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha
212 ; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l
213 ; P9BE-NEXT: lxv v0, 0(r3)
214 ; P9BE-NEXT: li r3, 0
215 ; P9BE-NEXT: vperm v5, v3, v2, v4
216 ; P9BE-NEXT: vperm v2, v3, v2, v0
217 ; P9BE-NEXT: vperm v0, v3, v1, v0
218 ; P9BE-NEXT: vperm v3, v3, v1, v4
219 ; P9BE-NEXT: vabsduw v2, v2, v0
220 ; P9BE-NEXT: vabsduw v3, v5, v3
221 ; P9BE-NEXT: vadduwm v2, v3, v2
222 ; P9BE-NEXT: xxswapd v3, v2
223 ; P9BE-NEXT: vadduwm v2, v2, v3
224 ; P9BE-NEXT: xxspltw v3, v2, 1
225 ; P9BE-NEXT: vadduwm v2, v2, v3
226 ; P9BE-NEXT: vextuwlx r3, r3, v2
227 ; P9BE-NEXT: extsw r3, r3
228 ; P9BE-NEXT: blr
229 entry:
230 %0 = bitcast i8* %pix1 to <8 x i8>*
231 %1 = load <8 x i8>, <8 x i8>* %0, align 1
232 %2 = zext <8 x i8> %1 to <8 x i32>
233 %3 = bitcast i8* %pix2 to <8 x i8>*
234 %4 = load <8 x i8>, <8 x i8>* %3, align 1
235 %5 = zext <8 x i8> %4 to <8 x i32>
236 %6 = sub nsw <8 x i32> %2, %5
237 %7 = icmp slt <8 x i32> %6, zeroinitializer
238 %8 = sub nsw <8 x i32> zeroinitializer, %6
239 %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6
240 %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
241 %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf
242 %rdx.shuf12 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
243 %bin.rdx13 = add nsw <8 x i32> %bin.rdx, %rdx.shuf12
244 %rdx.shuf14 = shufflevector <8 x i32> %bin.rdx13, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
245 %bin.rdx15 = add nsw <8 x i32> %bin.rdx13, %rdx.shuf14
246 %10 = extractelement <8 x i32> %bin.rdx15, i32 0
247 ret i32 %10
248 }
251 ; Generated from C source:
252 ;
253 ;#include <stdint.h>
254 ;#include <stdlib.h>
255 ;int test_pre_inc_disable_1( uint8_t *pix1, int i_stride_pix1, uint8_t *pix2 ) {
256 ; int i_sum = 0;
257 ; for( int y = 0; y < 8; y++ ) {
258 ; for( int x = 0; x < 8; x++) {
259 ; i_sum += abs( pix1[x] - pix2[x] )
260 ; }
261 ; pix1 += i_stride_pix1;
262 ; }
263 ; return i_sum;
264 ;}
266 ;int test_pre_inc_disable_2( uint8_t *pix1, uint8_t *pix2 ) {
267 ; int i_sum = 0;
268 ; for( int x = 0; x < 8; x++ ) {
269 ; i_sum += abs( pix1[x] - pix2[x] );
270 ; }
271 ;
272 ; return i_sum;
273 ;}
275 define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
276 ; CHECK-LABEL: test32:
277 ; CHECK: # %bb.0: # %entry
278 ; CHECK-NEXT: add r5, r3, r4
279 ; CHECK-NEXT: lxsiwzx v2, r3, r4
280 ; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha
281 ; CHECK-NEXT: xxlxor v3, v3, v3
282 ; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l
283 ; CHECK-NEXT: lxv v4, 0(r3)
284 ; CHECK-NEXT: li r3, 4
285 ; CHECK-NEXT: lxsiwzx v5, r5, r3
286 ; CHECK-NEXT: vperm v2, v2, v3, v4
287 ; CHECK-NEXT: vperm v3, v5, v3, v4
288 ; CHECK-NEXT: vspltisw v4, 8
289 ; CHECK-NEXT: vnegw v3, v3
290 ; CHECK-NEXT: vadduwm v4, v4, v4
291 ; CHECK-NEXT: vslw v3, v3, v4
292 ; CHECK-NEXT: vsubuwm v2, v3, v2
293 ; CHECK-NEXT: xxswapd vs0, v2
294 ; CHECK-NEXT: stxv vs0, 0(r3)
295 ; CHECK-NEXT: blr
296 ;
297 ; P9BE-LABEL: test32:
298 ; P9BE: # %bb.0: # %entry
299 ; P9BE-NEXT: add r5, r3, r4
300 ; P9BE-NEXT: lxsiwzx v2, r3, r4
301 ; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
302 ; P9BE-NEXT: xxlxor v3, v3, v3
303 ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
304 ; P9BE-NEXT: lxv v4, 0(r3)
305 ; P9BE-NEXT: li r3, 4
306 ; P9BE-NEXT: lxsiwzx v5, r5, r3
307 ; P9BE-NEXT: vperm v2, v3, v2, v4
308 ; P9BE-NEXT: vperm v3, v3, v5, v4
309 ; P9BE-NEXT: vspltisw v4, 8
310 ; P9BE-NEXT: vnegw v3, v3
311 ; P9BE-NEXT: vadduwm v4, v4, v4
312 ; P9BE-NEXT: vslw v3, v3, v4
313 ; P9BE-NEXT: vsubuwm v2, v3, v2
314 ; P9BE-NEXT: xxswapd vs0, v2
315 ; P9BE-NEXT: stxv vs0, 0(r3)
316 ; P9BE-NEXT: blr
317 entry:
318 %idx.ext63 = sext i32 %i_pix2 to i64
319 %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
320 %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
321 %0 = bitcast i8* %add.ptr64 to <4 x i8>*
322 %1 = load <4 x i8>, <4 x i8>* %0, align 1
323 %reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
324 %2 = zext <4 x i8> %reorder_shuffle117 to <4 x i32>
325 %3 = sub nsw <4 x i32> zeroinitializer, %2
326 %4 = bitcast i8* %arrayidx5.1 to <4 x i8>*
327 %5 = load <4 x i8>, <4 x i8>* %4, align 1
328 %reorder_shuffle115 = shufflevector <4 x i8> %5, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
329 %6 = zext <4 x i8> %reorder_shuffle115 to <4 x i32>
330 %7 = sub nsw <4 x i32> zeroinitializer, %6
331 %8 = shl nsw <4 x i32> %7, <i32 16, i32 16, i32 16, i32 16>
332 %9 = add nsw <4 x i32> %8, %3
333 %10 = sub nsw <4 x i32> %9, zeroinitializer
334 %11 = shufflevector <4 x i32> undef, <4 x i32> %10, <4 x i32> <i32 2, i32 7, i32 0, i32 5>
335 %12 = add nsw <4 x i32> zeroinitializer, %11
336 %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
337 store <4 x i32> %13, <4 x i32>* undef, align 16
338 ret void
339 }
341 define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
342 ; CHECK-LABEL: test16:
343 ; CHECK: # %bb.0: # %entry
344 ; CHECK-NEXT: sldi r4, r4, 1
345 ; CHECK-NEXT: li r7, 16
346 ; CHECK-NEXT: add r6, r3, r4
347 ; CHECK-NEXT: lxsihzx v4, r3, r4
348 ; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha
349 ; CHECK-NEXT: lxsihzx v2, r6, r7
350 ; CHECK-NEXT: li r6, 0
351 ; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l
352 ; CHECK-NEXT: mtvsrd v3, r6
353 ; CHECK-NEXT: vmrghh v4, v3, v4
354 ; CHECK-NEXT: vmrghh v2, v3, v2
355 ; CHECK-NEXT: vsplth v3, v3, 3
356 ; CHECK-NEXT: vmrglw v3, v4, v3
357 ; CHECK-NEXT: lxv v4, 0(r3)
358 ; CHECK-NEXT: li r3, 0
359 ; CHECK-NEXT: vperm v2, v2, v3, v4
360 ; CHECK-NEXT: xxspltw v3, v2, 2
361 ; CHECK-NEXT: vadduwm v2, v2, v3
362 ; CHECK-NEXT: vextuwrx r3, r3, v2
363 ; CHECK-NEXT: cmpw r3, r5
364 ; CHECK-NEXT: bgelr+ cr0
365 ; CHECK-NEXT: # %bb.1: # %if.then
366 ;
367 ; P9BE-LABEL: test16:
368 ; P9BE: # %bb.0: # %entry
369 ; P9BE-NEXT: sldi r4, r4, 1
370 ; P9BE-NEXT: li r7, 16
371 ; P9BE-NEXT: add r6, r3, r4
372 ; P9BE-NEXT: lxsihzx v5, r3, r4
373 ; P9BE-NEXT: addis r3, r2, .LCPI3_1@toc@ha
374 ; P9BE-NEXT: lxsihzx v2, r6, r7
375 ; P9BE-NEXT: addis r6, r2, .LCPI3_0@toc@ha
376 ; P9BE-NEXT: addi r3, r3, .LCPI3_1@toc@l
377 ; P9BE-NEXT: addi r6, r6, .LCPI3_0@toc@l
378 ; P9BE-NEXT: lxv v3, 0(r6)
379 ; P9BE-NEXT: li r6, 0
380 ; P9BE-NEXT: mtvsrwz v4, r6
381 ; P9BE-NEXT: vperm v2, v4, v2, v3
382 ; P9BE-NEXT: vperm v3, v4, v5, v3
383 ; P9BE-NEXT: vsplth v4, v4, 3
384 ; P9BE-NEXT: vmrghw v3, v4, v3
385 ; P9BE-NEXT: lxv v4, 0(r3)
386 ; P9BE-NEXT: li r3, 0
387 ; P9BE-NEXT: vperm v2, v3, v2, v4
388 ; P9BE-NEXT: xxspltw v3, v2, 1
389 ; P9BE-NEXT: vadduwm v2, v2, v3
390 ; P9BE-NEXT: vextuwlx r3, r3, v2
391 ; P9BE-NEXT: cmpw r3, r5
392 ; P9BE-NEXT: bgelr+ cr0
393 ; P9BE-NEXT: # %bb.1: # %if.then
394 entry:
395 %idxprom = sext i32 %delta to i64
396 %add14 = add nsw i32 %delta, 8
397 %idxprom15 = sext i32 %add14 to i64
398 br label %for.body
400 for.body: ; preds = %entry
401 %arrayidx8 = getelementptr inbounds i16, i16* %sums, i64 %idxprom
402 %0 = load i16, i16* %arrayidx8, align 2
403 %arrayidx16 = getelementptr inbounds i16, i16* %sums, i64 %idxprom15
404 %1 = load i16, i16* %arrayidx16, align 2
405 %2 = insertelement <4 x i16> undef, i16 %0, i32 2
406 %3 = insertelement <4 x i16> %2, i16 %1, i32 3
407 %4 = zext <4 x i16> %3 to <4 x i32>
408 %5 = sub nsw <4 x i32> zeroinitializer, %4
409 %6 = sub nsw <4 x i32> zeroinitializer, %5
410 %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
411 %bin.rdx = add <4 x i32> %7, zeroinitializer
412 %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
413 %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
414 %8 = extractelement <4 x i32> %bin.rdx55, i32 0
415 %op.extra = add nuw i32 %8, 0
416 %cmp25 = icmp slt i32 %op.extra, %thresh
417 br i1 %cmp25, label %if.then, label %if.end
419 if.then: ; preds = %for.body
420 unreachable
422 if.end: ; preds = %for.body
423 ret void
424 }
426 define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
427 ; CHECK-LABEL: test8:
428 ; CHECK: # %bb.0: # %entry
429 ; CHECK-NEXT: add r6, r3, r4
430 ; CHECK-NEXT: lxsibzx v2, r3, r4
431 ; CHECK-NEXT: li r3, 0
432 ; CHECK-NEXT: mtvsrd v3, r3
433 ; CHECK-NEXT: li r3, 8
434 ; CHECK-NEXT: lxsibzx v5, r6, r3
435 ; CHECK-NEXT: vspltb v4, v3, 7
436 ; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
437 ; CHECK-NEXT: vmrghb v2, v3, v2
438 ; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
439 ; CHECK-NEXT: vmrglh v2, v2, v4
440 ; CHECK-NEXT: vmrghb v3, v3, v5
441 ; CHECK-NEXT: vmrglw v2, v2, v4
442 ; CHECK-NEXT: vmrglh v3, v3, v4
443 ; CHECK-NEXT: vmrglw v3, v4, v3
444 ; CHECK-NEXT: lxv v4, 0(r3)
445 ; CHECK-NEXT: li r3, 0
446 ; CHECK-NEXT: vperm v2, v3, v2, v4
447 ; CHECK-NEXT: xxspltw v3, v2, 2
448 ; CHECK-NEXT: vadduwm v2, v2, v3
449 ; CHECK-NEXT: vextuwrx r3, r3, v2
450 ; CHECK-NEXT: cmpw r3, r5
451 ; CHECK-NEXT: bgelr+ cr0
452 ; CHECK-NEXT: # %bb.1: # %if.then
453 ;
454 ; P9BE-LABEL: test8:
455 ; P9BE: # %bb.0: # %entry
456 ; P9BE-NEXT: add r6, r3, r4
457 ; P9BE-NEXT: li r7, 8
458 ; P9BE-NEXT: lxsibzx v5, r3, r4
459 ; P9BE-NEXT: addis r3, r2, .LCPI4_1@toc@ha
460 ; P9BE-NEXT: lxsibzx v2, r6, r7
461 ; P9BE-NEXT: addis r6, r2, .LCPI4_0@toc@ha
462 ; P9BE-NEXT: addi r3, r3, .LCPI4_1@toc@l
463 ; P9BE-NEXT: addi r6, r6, .LCPI4_0@toc@l
464 ; P9BE-NEXT: lxv v3, 0(r6)
465 ; P9BE-NEXT: li r6, 0
466 ; P9BE-NEXT: mtvsrwz v4, r6
467 ; P9BE-NEXT: vperm v2, v4, v2, v3
468 ; P9BE-NEXT: vperm v3, v4, v5, v3
469 ; P9BE-NEXT: vspltb v4, v4, 7
470 ; P9BE-NEXT: vmrghh v3, v3, v4
471 ; P9BE-NEXT: xxspltw v4, v4, 0
472 ; P9BE-NEXT: vmrghw v2, v3, v2
473 ; P9BE-NEXT: lxv v3, 0(r3)
474 ; P9BE-NEXT: li r3, 0
475 ; P9BE-NEXT: vperm v2, v4, v2, v3
476 ; P9BE-NEXT: xxspltw v3, v2, 1
477 ; P9BE-NEXT: vadduwm v2, v2, v3
478 ; P9BE-NEXT: vextuwlx r3, r3, v2
479 ; P9BE-NEXT: cmpw r3, r5
480 ; P9BE-NEXT: bgelr+ cr0
481 ; P9BE-NEXT: # %bb.1: # %if.then
482 entry:
483 %idxprom = sext i32 %delta to i64
484 %add14 = add nsw i32 %delta, 8
485 %idxprom15 = sext i32 %add14 to i64
486 br label %for.body
488 for.body: ; preds = %entry
489 %arrayidx8 = getelementptr inbounds i8, i8* %sums, i64 %idxprom
490 %0 = load i8, i8* %arrayidx8, align 2
491 %arrayidx16 = getelementptr inbounds i8, i8* %sums, i64 %idxprom15
492 %1 = load i8, i8* %arrayidx16, align 2
493 %2 = insertelement <4 x i8> undef, i8 %0, i32 2
494 %3 = insertelement <4 x i8> %2, i8 %1, i32 3
495 %4 = zext <4 x i8> %3 to <4 x i32>
496 %5 = sub nsw <4 x i32> zeroinitializer, %4
497 %6 = sub nsw <4 x i32> zeroinitializer, %5
498 %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
499 %bin.rdx = add <4 x i32> %7, zeroinitializer
500 %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
501 %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
502 %8 = extractelement <4 x i32> %bin.rdx55, i32 0
503 %op.extra = add nuw i32 %8, 0
504 %cmp25 = icmp slt i32 %op.extra, %thresh
505 br i1 %cmp25, label %if.then, label %if.end
507 if.then: ; preds = %for.body
508 unreachable
510 if.end: ; preds = %for.body
511 ret void
512 }