| blob | 4598e797bc934c824afcfeca8eb18123f952349e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
3 ; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE
4 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
5 ; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU2
7 ; single tests (identical for -mattr=+spe and -mattr=+efpu2)
9 declare float @llvm.fabs.float(float)
10 define float @test_float_abs(float %a) #0 {
11 ; CHECK-LABEL: test_float_abs:
12 ; CHECK: # %bb.0: # %entry
13 ; CHECK-NEXT: efsabs 3, 3
14 ; CHECK-NEXT: blr
15 entry:
16 %0 = tail call float @llvm.fabs.float(float %a)
17 ret float %0
18 }
20 define float @test_fnabs(float %a) #0 {
21 ; CHECK-LABEL: test_fnabs:
22 ; CHECK: # %bb.0: # %entry
23 ; CHECK-NEXT: efsnabs 3, 3
24 ; CHECK-NEXT: blr
25 entry:
26 %0 = tail call float @llvm.fabs.float(float %a)
27 %sub = fsub float -0.000000e+00, %0
28 ret float %sub
29 }
31 define float @test_fdiv(float %a, float %b) #0 {
32 ; CHECK-LABEL: test_fdiv:
33 ; CHECK: # %bb.0: # %entry
34 ; CHECK-NEXT: efsdiv 3, 3, 4
35 ; CHECK-NEXT: blr
36 entry:
37 %v = fdiv float %a, %b
38 ret float %v
40 }
42 define float @test_fmul(float %a, float %b) #0 {
43 ; CHECK-LABEL: test_fmul:
44 ; CHECK: # %bb.0: # %entry
45 ; CHECK-NEXT: efsmul 3, 3, 4
46 ; CHECK-NEXT: blr
47 entry:
48 %v = fmul float %a, %b
49 ret float %v
50 }
52 define float @test_fadd(float %a, float %b) #0 {
53 ; CHECK-LABEL: test_fadd:
54 ; CHECK: # %bb.0: # %entry
55 ; CHECK-NEXT: efsadd 3, 3, 4
56 ; CHECK-NEXT: blr
57 entry:
58 %v = fadd float %a, %b
59 ret float %v
60 }
62 define float @test_fsub(float %a, float %b) #0 {
63 ; CHECK-LABEL: test_fsub:
64 ; CHECK: # %bb.0: # %entry
65 ; CHECK-NEXT: efssub 3, 3, 4
66 ; CHECK-NEXT: blr
67 entry:
68 %v = fsub float %a, %b
69 ret float %v
70 }
72 define float @test_fneg(float %a) #0 {
73 ; CHECK-LABEL: test_fneg:
74 ; CHECK: # %bb.0: # %entry
75 ; CHECK-NEXT: efsneg 3, 3
76 ; CHECK-NEXT: blr
77 entry:
78 %v = fsub float -0.0, %a
79 ret float %v
80 }
82 define i32 @test_fcmpgt(float %a, float %b) #0 {
83 ; CHECK-LABEL: test_fcmpgt:
84 ; CHECK: # %bb.0: # %entry
85 ; CHECK-NEXT: stwu 1, -16(1)
86 ; CHECK-NEXT: efscmpgt 0, 3, 4
87 ; CHECK-NEXT: ble 0, .LBB7_2
88 ; CHECK-NEXT: # %bb.1: # %tr
89 ; CHECK-NEXT: li 3, 1
90 ; CHECK-NEXT: b .LBB7_3
91 ; CHECK-NEXT: .LBB7_2: # %fa
92 ; CHECK-NEXT: li 3, 0
93 ; CHECK-NEXT: .LBB7_3: # %ret
94 ; CHECK-NEXT: stw 3, 12(1)
95 ; CHECK-NEXT: lwz 3, 12(1)
96 ; CHECK-NEXT: addi 1, 1, 16
97 ; CHECK-NEXT: blr
98 entry:
99 %r = alloca i32, align 4
100 %c = fcmp ogt float %a, %b
101 br i1 %c, label %tr, label %fa
102 tr:
103 store i32 1, i32* %r, align 4
104 br label %ret
105 fa:
106 store i32 0, i32* %r, align 4
107 br label %ret
108 ret:
109 %0 = load i32, i32* %r, align 4
110 ret i32 %0
111 }
113 define i32 @test_fcmpugt(float %a, float %b) #0 {
114 ; CHECK-LABEL: test_fcmpugt:
115 ; CHECK: # %bb.0: # %entry
116 ; CHECK-NEXT: stwu 1, -16(1)
117 ; CHECK-NEXT: efscmpeq 0, 4, 4
118 ; CHECK-NEXT: bc 4, 1, .LBB8_4
119 ; CHECK-NEXT: # %bb.1: # %entry
120 ; CHECK-NEXT: efscmpeq 0, 3, 3
121 ; CHECK-NEXT: bc 4, 1, .LBB8_4
122 ; CHECK-NEXT: # %bb.2: # %entry
123 ; CHECK-NEXT: efscmpgt 0, 3, 4
124 ; CHECK-NEXT: bc 12, 1, .LBB8_4
125 ; CHECK-NEXT: # %bb.3: # %fa
126 ; CHECK-NEXT: li 3, 0
127 ; CHECK-NEXT: b .LBB8_5
128 ; CHECK-NEXT: .LBB8_4: # %tr
129 ; CHECK-NEXT: li 3, 1
130 ; CHECK-NEXT: .LBB8_5: # %ret
131 ; CHECK-NEXT: stw 3, 12(1)
132 ; CHECK-NEXT: lwz 3, 12(1)
133 ; CHECK-NEXT: addi 1, 1, 16
134 ; CHECK-NEXT: blr
135 entry:
136 %r = alloca i32, align 4
137 %c = fcmp ugt float %a, %b
138 br i1 %c, label %tr, label %fa
139 tr:
140 store i32 1, i32* %r, align 4
141 br label %ret
142 fa:
143 store i32 0, i32* %r, align 4
144 br label %ret
145 ret:
146 %0 = load i32, i32* %r, align 4
147 ret i32 %0
148 }
150 define i32 @test_fcmple(float %a, float %b) #0 {
151 ; CHECK-LABEL: test_fcmple:
152 ; CHECK: # %bb.0: # %entry
153 ; CHECK-NEXT: stwu 1, -16(1)
154 ; CHECK-NEXT: efscmpeq 0, 3, 3
155 ; CHECK-NEXT: bc 4, 1, .LBB9_4
156 ; CHECK-NEXT: # %bb.1: # %entry
157 ; CHECK-NEXT: efscmpeq 0, 4, 4
158 ; CHECK-NEXT: bc 4, 1, .LBB9_4
159 ; CHECK-NEXT: # %bb.2: # %entry
160 ; CHECK-NEXT: efscmpgt 0, 3, 4
161 ; CHECK-NEXT: bc 12, 1, .LBB9_4
162 ; CHECK-NEXT: # %bb.3: # %tr
163 ; CHECK-NEXT: li 3, 1
164 ; CHECK-NEXT: b .LBB9_5
165 ; CHECK-NEXT: .LBB9_4: # %fa
166 ; CHECK-NEXT: li 3, 0
167 ; CHECK-NEXT: .LBB9_5: # %ret
168 ; CHECK-NEXT: stw 3, 12(1)
169 ; CHECK-NEXT: lwz 3, 12(1)
170 ; CHECK-NEXT: addi 1, 1, 16
171 ; CHECK-NEXT: blr
172 entry:
173 %r = alloca i32, align 4
174 %c = fcmp ole float %a, %b
175 br i1 %c, label %tr, label %fa
176 tr:
177 store i32 1, i32* %r, align 4
178 br label %ret
179 fa:
180 store i32 0, i32* %r, align 4
181 br label %ret
182 ret:
183 %0 = load i32, i32* %r, align 4
184 ret i32 %0
185 }
187 define i32 @test_fcmpule(float %a, float %b) #0 {
188 ; CHECK-LABEL: test_fcmpule:
189 ; CHECK: # %bb.0: # %entry
190 ; CHECK-NEXT: stwu 1, -16(1)
191 ; CHECK-NEXT: efscmpgt 0, 3, 4
192 ; CHECK-NEXT: bgt 0, .LBB10_2
193 ; CHECK-NEXT: # %bb.1: # %tr
194 ; CHECK-NEXT: li 3, 1
195 ; CHECK-NEXT: b .LBB10_3
196 ; CHECK-NEXT: .LBB10_2: # %fa
197 ; CHECK-NEXT: li 3, 0
198 ; CHECK-NEXT: .LBB10_3: # %ret
199 ; CHECK-NEXT: stw 3, 12(1)
200 ; CHECK-NEXT: lwz 3, 12(1)
201 ; CHECK-NEXT: addi 1, 1, 16
202 ; CHECK-NEXT: blr
203 entry:
204 %r = alloca i32, align 4
205 %c = fcmp ule float %a, %b
206 br i1 %c, label %tr, label %fa
207 tr:
208 store i32 1, i32* %r, align 4
209 br label %ret
210 fa:
211 store i32 0, i32* %r, align 4
212 br label %ret
213 ret:
214 %0 = load i32, i32* %r, align 4
215 ret i32 %0
216 }
218 ; The type of comparison found in C's if (x == y)
219 define i32 @test_fcmpeq(float %a, float %b) #0 {
220 ; CHECK-LABEL: test_fcmpeq:
221 ; CHECK: # %bb.0: # %entry
222 ; CHECK-NEXT: stwu 1, -16(1)
223 ; CHECK-NEXT: efscmpeq 0, 3, 4
224 ; CHECK-NEXT: ble 0, .LBB11_2
225 ; CHECK-NEXT: # %bb.1: # %tr
226 ; CHECK-NEXT: li 3, 1
227 ; CHECK-NEXT: b .LBB11_3
228 ; CHECK-NEXT: .LBB11_2: # %fa
229 ; CHECK-NEXT: li 3, 0
230 ; CHECK-NEXT: .LBB11_3: # %ret
231 ; CHECK-NEXT: stw 3, 12(1)
232 ; CHECK-NEXT: lwz 3, 12(1)
233 ; CHECK-NEXT: addi 1, 1, 16
234 ; CHECK-NEXT: blr
235 entry:
236 %r = alloca i32, align 4
237 %c = fcmp oeq float %a, %b
238 br i1 %c, label %tr, label %fa
239 tr:
240 store i32 1, i32* %r, align 4
241 br label %ret
242 fa:
243 store i32 0, i32* %r, align 4
244 br label %ret
245 ret:
246 %0 = load i32, i32* %r, align 4
247 ret i32 %0
248 }
250 ; (un)ordered tests are expanded to une and oeq so verify
251 define i1 @test_fcmpuno(float %a, float %b) #0 {
252 ; CHECK-LABEL: test_fcmpuno:
253 ; CHECK: # %bb.0: # %entry
254 ; CHECK-NEXT: efscmpeq 0, 3, 3
255 ; CHECK-NEXT: efscmpeq 1, 4, 4
256 ; CHECK-NEXT: li 5, 1
257 ; CHECK-NEXT: crand 20, 5, 1
258 ; CHECK-NEXT: bc 12, 20, .LBB12_2
259 ; CHECK-NEXT: # %bb.1: # %entry
260 ; CHECK-NEXT: ori 3, 5, 0
261 ; CHECK-NEXT: blr
262 ; CHECK-NEXT: .LBB12_2: # %entry
263 ; CHECK-NEXT: li 3, 0
264 ; CHECK-NEXT: blr
265 entry:
266 %r = fcmp uno float %a, %b
267 ret i1 %r
268 }
270 define i1 @test_fcmpord(float %a, float %b) #0 {
271 ; CHECK-LABEL: test_fcmpord:
272 ; CHECK: # %bb.0: # %entry
273 ; CHECK-NEXT: efscmpeq 0, 4, 4
274 ; CHECK-NEXT: efscmpeq 1, 3, 3
275 ; CHECK-NEXT: li 5, 1
276 ; CHECK-NEXT: crnand 20, 5, 1
277 ; CHECK-NEXT: bc 12, 20, .LBB13_2
278 ; CHECK-NEXT: # %bb.1: # %entry
279 ; CHECK-NEXT: ori 3, 5, 0
280 ; CHECK-NEXT: blr
281 ; CHECK-NEXT: .LBB13_2: # %entry
282 ; CHECK-NEXT: li 3, 0
283 ; CHECK-NEXT: blr
284 entry:
285 %r = fcmp ord float %a, %b
286 ret i1 %r
287 }
289 define i1 @test_fcmpueq(float %a, float %b) #0 {
290 ; CHECK-LABEL: test_fcmpueq:
291 ; CHECK: # %bb.0: # %entry
292 ; CHECK-NEXT: efscmpgt 0, 3, 4
293 ; CHECK-NEXT: efscmplt 1, 3, 4
294 ; CHECK-NEXT: li 5, 1
295 ; CHECK-NEXT: cror 20, 5, 1
296 ; CHECK-NEXT: bc 12, 20, .LBB14_2
297 ; CHECK-NEXT: # %bb.1: # %entry
298 ; CHECK-NEXT: ori 3, 5, 0
299 ; CHECK-NEXT: blr
300 ; CHECK-NEXT: .LBB14_2: # %entry
301 ; CHECK-NEXT: li 3, 0
302 ; CHECK-NEXT: blr
303 entry:
304 %r = fcmp ueq float %a, %b
305 ret i1 %r
306 }
308 define i1 @test_fcmpne(float %a, float %b) #0 {
309 ; CHECK-LABEL: test_fcmpne:
310 ; CHECK: # %bb.0: # %entry
311 ; CHECK-NEXT: efscmplt 0, 3, 4
312 ; CHECK-NEXT: efscmpgt 1, 3, 4
313 ; CHECK-NEXT: li 5, 1
314 ; CHECK-NEXT: crnor 20, 5, 1
315 ; CHECK-NEXT: bc 12, 20, .LBB15_2
316 ; CHECK-NEXT: # %bb.1: # %entry
317 ; CHECK-NEXT: ori 3, 5, 0
318 ; CHECK-NEXT: blr
319 ; CHECK-NEXT: .LBB15_2: # %entry
320 ; CHECK-NEXT: li 3, 0
321 ; CHECK-NEXT: blr
322 entry:
323 %r = fcmp one float %a, %b
324 ret i1 %r
325 }
327 define i32 @test_fcmpune(float %a, float %b) #0 {
328 ; CHECK-LABEL: test_fcmpune:
329 ; CHECK: # %bb.0: # %entry
330 ; CHECK-NEXT: stwu 1, -16(1)
331 ; CHECK-NEXT: efscmpeq 0, 3, 4
332 ; CHECK-NEXT: bgt 0, .LBB16_2
333 ; CHECK-NEXT: # %bb.1: # %tr
334 ; CHECK-NEXT: li 3, 1
335 ; CHECK-NEXT: b .LBB16_3
336 ; CHECK-NEXT: .LBB16_2: # %fa
337 ; CHECK-NEXT: li 3, 0
338 ; CHECK-NEXT: .LBB16_3: # %ret
339 ; CHECK-NEXT: stw 3, 12(1)
340 ; CHECK-NEXT: lwz 3, 12(1)
341 ; CHECK-NEXT: addi 1, 1, 16
342 ; CHECK-NEXT: blr
343 entry:
344 %r = alloca i32, align 4
345 %c = fcmp une float %a, %b
346 br i1 %c, label %tr, label %fa
347 tr:
348 store i32 1, i32* %r, align 4
349 br label %ret
350 fa:
351 store i32 0, i32* %r, align 4
352 br label %ret
353 ret:
354 %0 = load i32, i32* %r, align 4
355 ret i32 %0
356 }
358 define i32 @test_fcmplt(float %a, float %b) #0 {
359 ; CHECK-LABEL: test_fcmplt:
360 ; CHECK: # %bb.0: # %entry
361 ; CHECK-NEXT: stwu 1, -16(1)
362 ; CHECK-NEXT: efscmplt 0, 3, 4
363 ; CHECK-NEXT: ble 0, .LBB17_2
364 ; CHECK-NEXT: # %bb.1: # %tr
365 ; CHECK-NEXT: li 3, 1
366 ; CHECK-NEXT: b .LBB17_3
367 ; CHECK-NEXT: .LBB17_2: # %fa
368 ; CHECK-NEXT: li 3, 0
369 ; CHECK-NEXT: .LBB17_3: # %ret
370 ; CHECK-NEXT: stw 3, 12(1)
371 ; CHECK-NEXT: lwz 3, 12(1)
372 ; CHECK-NEXT: addi 1, 1, 16
373 ; CHECK-NEXT: blr
374 entry:
375 %r = alloca i32, align 4
376 %c = fcmp olt float %a, %b
377 br i1 %c, label %tr, label %fa
378 tr:
379 store i32 1, i32* %r, align 4
380 br label %ret
381 fa:
382 store i32 0, i32* %r, align 4
383 br label %ret
384 ret:
385 %0 = load i32, i32* %r, align 4
386 ret i32 %0
387 }
389 define i1 @test_fcmpult(float %a, float %b) #0 {
390 ; CHECK-LABEL: test_fcmpult:
391 ; CHECK: # %bb.0: # %entry
392 ; CHECK-NEXT: efscmpeq 0, 3, 3
393 ; CHECK-NEXT: efscmpeq 1, 4, 4
394 ; CHECK-NEXT: crnand 20, 5, 1
395 ; CHECK-NEXT: efscmplt 0, 3, 4
396 ; CHECK-NEXT: li 5, 1
397 ; CHECK-NEXT: crnor 20, 1, 20
398 ; CHECK-NEXT: bc 12, 20, .LBB18_2
399 ; CHECK-NEXT: # %bb.1: # %entry
400 ; CHECK-NEXT: ori 3, 5, 0
401 ; CHECK-NEXT: blr
402 ; CHECK-NEXT: .LBB18_2: # %entry
403 ; CHECK-NEXT: li 3, 0
404 ; CHECK-NEXT: blr
405 entry:
406 %r = fcmp ult float %a, %b
407 ret i1 %r
408 }
410 define i32 @test_fcmpge(float %a, float %b) #0 {
411 ; CHECK-LABEL: test_fcmpge:
412 ; CHECK: # %bb.0: # %entry
413 ; CHECK-NEXT: stwu 1, -16(1)
414 ; CHECK-NEXT: efscmpeq 0, 3, 3
415 ; CHECK-NEXT: bc 4, 1, .LBB19_4
416 ; CHECK-NEXT: # %bb.1: # %entry
417 ; CHECK-NEXT: efscmpeq 0, 4, 4
418 ; CHECK-NEXT: bc 4, 1, .LBB19_4
419 ; CHECK-NEXT: # %bb.2: # %entry
420 ; CHECK-NEXT: efscmplt 0, 3, 4
421 ; CHECK-NEXT: bc 12, 1, .LBB19_4
422 ; CHECK-NEXT: # %bb.3: # %tr
423 ; CHECK-NEXT: li 3, 1
424 ; CHECK-NEXT: b .LBB19_5
425 ; CHECK-NEXT: .LBB19_4: # %fa
426 ; CHECK-NEXT: li 3, 0
427 ; CHECK-NEXT: .LBB19_5: # %ret
428 ; CHECK-NEXT: stw 3, 12(1)
429 ; CHECK-NEXT: lwz 3, 12(1)
430 ; CHECK-NEXT: addi 1, 1, 16
431 ; CHECK-NEXT: blr
432 entry:
433 %r = alloca i32, align 4
434 %c = fcmp oge float %a, %b
435 br i1 %c, label %tr, label %fa
436 tr:
437 store i32 1, i32* %r, align 4
438 br label %ret
439 fa:
440 store i32 0, i32* %r, align 4
441 br label %ret
442 ret:
443 %0 = load i32, i32* %r, align 4
444 ret i32 %0
445 }
447 define i32 @test_fcmpuge(float %a, float %b) #0 {
448 ; CHECK-LABEL: test_fcmpuge:
449 ; CHECK: # %bb.0: # %entry
450 ; CHECK-NEXT: stwu 1, -16(1)
451 ; CHECK-NEXT: efscmplt 0, 3, 4
452 ; CHECK-NEXT: bgt 0, .LBB20_2
453 ; CHECK-NEXT: # %bb.1: # %tr
454 ; CHECK-NEXT: li 3, 1
455 ; CHECK-NEXT: b .LBB20_3
456 ; CHECK-NEXT: .LBB20_2: # %fa
457 ; CHECK-NEXT: li 3, 0
458 ; CHECK-NEXT: .LBB20_3: # %ret
459 ; CHECK-NEXT: stw 3, 12(1)
460 ; CHECK-NEXT: lwz 3, 12(1)
461 ; CHECK-NEXT: addi 1, 1, 16
462 ; CHECK-NEXT: blr
463 entry:
464 %r = alloca i32, align 4
465 %c = fcmp uge float %a, %b
466 br i1 %c, label %tr, label %fa
467 tr:
468 store i32 1, i32* %r, align 4
469 br label %ret
470 fa:
471 store i32 0, i32* %r, align 4
472 br label %ret
473 ret:
474 %0 = load i32, i32* %r, align 4
475 ret i32 %0
476 }
479 define i32 @test_ftoui(float %a) #0 {
480 ; CHECK-LABEL: test_ftoui:
481 ; CHECK: # %bb.0:
482 ; CHECK-NEXT: efsctuiz 3, 3
483 ; CHECK-NEXT: blr
484 %v = fptoui float %a to i32
485 ret i32 %v
486 }
488 define i32 @test_ftosi(float %a) #0 {
489 ; CHECK-LABEL: test_ftosi:
490 ; CHECK: # %bb.0:
491 ; CHECK-NEXT: efsctsiz 3, 3
492 ; CHECK-NEXT: blr
493 %v = fptosi float %a to i32
494 ret i32 %v
495 }
497 define float @test_ffromui(i32 %a) #0 {
498 ; CHECK-LABEL: test_ffromui:
499 ; CHECK: # %bb.0:
500 ; CHECK-NEXT: efscfui 3, 3
501 ; CHECK-NEXT: blr
502 %v = uitofp i32 %a to float
503 ret float %v
504 }
506 define float @test_ffromsi(i32 %a) #0 {
507 ; CHECK-LABEL: test_ffromsi:
508 ; CHECK: # %bb.0:
509 ; CHECK-NEXT: efscfsi 3, 3
510 ; CHECK-NEXT: blr
511 %v = sitofp i32 %a to float
512 ret float %v
513 }
515 define i32 @test_fasmconst(float %x) #0 {
516 ; CHECK-LABEL: test_fasmconst:
517 ; CHECK: # %bb.0: # %entry
518 ; CHECK-NEXT: stwu 1, -32(1)
519 ; CHECK-NEXT: stw 3, 20(1)
520 ; CHECK-NEXT: stw 3, 24(1)
521 ; CHECK-NEXT: lwz 3, 20(1)
522 ; CHECK-NEXT: #APP
523 ; CHECK-NEXT: efsctsi 3, 3
524 ; CHECK-NEXT: #NO_APP
525 ; CHECK-NEXT: addi 1, 1, 32
526 ; CHECK-NEXT: blr
527 entry:
528 %x.addr = alloca float, align 8
529 store float %x, float* %x.addr, align 8
530 %0 = load float, float* %x.addr, align 8
531 %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)
532 ret i32 %1
533 ; Check that it's not loading a double
534 }
535 attributes #0 = { nounwind }
537 ; Double tests
538 ; results depend on -mattr=+spe or -mattr=+efpu2
540 define float @test_dtos(double %a) #0 {
541 ; SPE-LABEL: test_dtos:
542 ; SPE: # %bb.0: # %entry
543 ; SPE-NEXT: evmergelo 3, 3, 4
544 ; SPE-NEXT: efscfd 3, 3
545 ; SPE-NEXT: blr
546 ;
547 ; EFPU2-LABEL: test_dtos:
548 ; EFPU2: # %bb.0: # %entry
549 ; EFPU2-NEXT: mflr 0
550 ; EFPU2-NEXT: stw 0, 4(1)
551 ; EFPU2-NEXT: stwu 1, -16(1)
552 ; EFPU2-NEXT: bl __truncdfsf2
553 ; EFPU2-NEXT: lwz 0, 20(1)
554 ; EFPU2-NEXT: addi 1, 1, 16
555 ; EFPU2-NEXT: mtlr 0
556 ; EFPU2-NEXT: blr
557 entry:
558 %v = fptrunc double %a to float
559 ret float %v
560 }
562 define void @test_double_abs(double * %aa) #0 {
563 ; SPE-LABEL: test_double_abs:
564 ; SPE: # %bb.0: # %entry
565 ; SPE-NEXT: evldd 4, 0(3)
566 ; SPE-NEXT: efdabs 4, 4
567 ; SPE-NEXT: evstdd 4, 0(3)
568 ; SPE-NEXT: blr
569 ;
570 ; EFPU2-LABEL: test_double_abs:
571 ; EFPU2: # %bb.0: # %entry
572 ; EFPU2-NEXT: lwz 4, 0(3)
573 ; EFPU2-NEXT: clrlwi 4, 4, 1
574 ; EFPU2-NEXT: stw 4, 0(3)
575 ; EFPU2-NEXT: blr
576 entry:
577 %0 = load double, double * %aa
578 %1 = tail call double @llvm.fabs.f64(double %0) #2
579 store double %1, double * %aa
580 ret void
581 }
583 ; Function Attrs: nounwind readnone
584 declare double @llvm.fabs.f64(double) #1
586 define void @test_dnabs(double * %aa) #0 {
587 ; SPE-LABEL: test_dnabs:
588 ; SPE: # %bb.0: # %entry
589 ; SPE-NEXT: evldd 4, 0(3)
590 ; SPE-NEXT: efdnabs 4, 4
591 ; SPE-NEXT: evstdd 4, 0(3)
592 ; SPE-NEXT: blr
593 ;
594 ; EFPU2-LABEL: test_dnabs:
595 ; EFPU2: # %bb.0: # %entry
596 ; EFPU2-NEXT: lwz 4, 0(3)
597 ; EFPU2-NEXT: oris 4, 4, 32768
598 ; EFPU2-NEXT: stw 4, 0(3)
599 ; EFPU2-NEXT: blr
600 entry:
601 %0 = load double, double * %aa
602 %1 = tail call double @llvm.fabs.f64(double %0) #2
603 %sub = fsub double -0.000000e+00, %1
604 store double %sub, double * %aa
605 ret void
606 }
608 define double @test_ddiv(double %a, double %b) #0 {
609 ; SPE-LABEL: test_ddiv:
610 ; SPE: # %bb.0: # %entry
611 ; SPE-NEXT: evmergelo 5, 5, 6
612 ; SPE-NEXT: evmergelo 3, 3, 4
613 ; SPE-NEXT: efddiv 4, 3, 5
614 ; SPE-NEXT: evmergehi 3, 4, 4
615 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
616 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
617 ; SPE-NEXT: blr
618 ;
619 ; EFPU2-LABEL: test_ddiv:
620 ; EFPU2: # %bb.0: # %entry
621 ; EFPU2-NEXT: mflr 0
622 ; EFPU2-NEXT: stw 0, 4(1)
623 ; EFPU2-NEXT: stwu 1, -16(1)
624 ; EFPU2-NEXT: bl __divdf3
625 ; EFPU2-NEXT: lwz 0, 20(1)
626 ; EFPU2-NEXT: addi 1, 1, 16
627 ; EFPU2-NEXT: mtlr 0
628 ; EFPU2-NEXT: blr
629 entry:
630 %v = fdiv double %a, %b
631 ret double %v
633 }
635 define double @test_dmul(double %a, double %b) #0 {
636 ; SPE-LABEL: test_dmul:
637 ; SPE: # %bb.0: # %entry
638 ; SPE-NEXT: evmergelo 5, 5, 6
639 ; SPE-NEXT: evmergelo 3, 3, 4
640 ; SPE-NEXT: efdmul 4, 3, 5
641 ; SPE-NEXT: evmergehi 3, 4, 4
642 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
643 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
644 ; SPE-NEXT: blr
645 ;
646 ; EFPU2-LABEL: test_dmul:
647 ; EFPU2: # %bb.0: # %entry
648 ; EFPU2-NEXT: mflr 0
649 ; EFPU2-NEXT: stw 0, 4(1)
650 ; EFPU2-NEXT: stwu 1, -16(1)
651 ; EFPU2-NEXT: bl __muldf3
652 ; EFPU2-NEXT: lwz 0, 20(1)
653 ; EFPU2-NEXT: addi 1, 1, 16
654 ; EFPU2-NEXT: mtlr 0
655 ; EFPU2-NEXT: blr
656 entry:
657 %v = fmul double %a, %b
658 ret double %v
659 }
661 define double @test_dadd(double %a, double %b) #0 {
662 ; SPE-LABEL: test_dadd:
663 ; SPE: # %bb.0: # %entry
664 ; SPE-NEXT: evmergelo 5, 5, 6
665 ; SPE-NEXT: evmergelo 3, 3, 4
666 ; SPE-NEXT: efdadd 4, 3, 5
667 ; SPE-NEXT: evmergehi 3, 4, 4
668 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
669 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
670 ; SPE-NEXT: blr
671 ;
672 ; EFPU2-LABEL: test_dadd:
673 ; EFPU2: # %bb.0: # %entry
674 ; EFPU2-NEXT: mflr 0
675 ; EFPU2-NEXT: stw 0, 4(1)
676 ; EFPU2-NEXT: stwu 1, -16(1)
677 ; EFPU2-NEXT: bl __adddf3
678 ; EFPU2-NEXT: lwz 0, 20(1)
679 ; EFPU2-NEXT: addi 1, 1, 16
680 ; EFPU2-NEXT: mtlr 0
681 ; EFPU2-NEXT: blr
682 entry:
683 %v = fadd double %a, %b
684 ret double %v
685 }
687 define double @test_dsub(double %a, double %b) #0 {
688 ; SPE-LABEL: test_dsub:
689 ; SPE: # %bb.0: # %entry
690 ; SPE-NEXT: evmergelo 5, 5, 6
691 ; SPE-NEXT: evmergelo 3, 3, 4
692 ; SPE-NEXT: efdsub 4, 3, 5
693 ; SPE-NEXT: evmergehi 3, 4, 4
694 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
695 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
696 ; SPE-NEXT: blr
697 ;
698 ; EFPU2-LABEL: test_dsub:
699 ; EFPU2: # %bb.0: # %entry
700 ; EFPU2-NEXT: mflr 0
701 ; EFPU2-NEXT: stw 0, 4(1)
702 ; EFPU2-NEXT: stwu 1, -16(1)
703 ; EFPU2-NEXT: bl __subdf3
704 ; EFPU2-NEXT: lwz 0, 20(1)
705 ; EFPU2-NEXT: addi 1, 1, 16
706 ; EFPU2-NEXT: mtlr 0
707 ; EFPU2-NEXT: blr
708 entry:
709 %v = fsub double %a, %b
710 ret double %v
711 }
713 define double @test_dneg(double %a) #0 {
714 ; SPE-LABEL: test_dneg:
715 ; SPE: # %bb.0: # %entry
716 ; SPE-NEXT: evmergelo 3, 3, 4
717 ; SPE-NEXT: efdneg 4, 3
718 ; SPE-NEXT: evmergehi 3, 4, 4
719 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
720 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
721 ; SPE-NEXT: blr
722 ;
723 ; EFPU2-LABEL: test_dneg:
724 ; EFPU2: # %bb.0: # %entry
725 ; EFPU2-NEXT: xoris 3, 3, 32768
726 ; EFPU2-NEXT: blr
727 entry:
728 %v = fsub double -0.0, %a
729 ret double %v
730 }
732 define double @test_stod(float %a) #0 {
733 ; SPE-LABEL: test_stod:
734 ; SPE: # %bb.0: # %entry
735 ; SPE-NEXT: efdcfs 4, 3
736 ; SPE-NEXT: evmergehi 3, 4, 4
737 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
738 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
739 ; SPE-NEXT: blr
740 ;
741 ; EFPU2-LABEL: test_stod:
742 ; EFPU2: # %bb.0: # %entry
743 ; EFPU2-NEXT: mflr 0
744 ; EFPU2-NEXT: stw 0, 4(1)
745 ; EFPU2-NEXT: stwu 1, -16(1)
746 ; EFPU2-NEXT: bl __extendsfdf2
747 ; EFPU2-NEXT: lwz 0, 20(1)
748 ; EFPU2-NEXT: addi 1, 1, 16
749 ; EFPU2-NEXT: mtlr 0
750 ; EFPU2-NEXT: blr
751 entry:
752 %v = fpext float %a to double
753 ret double %v
754 }
756 ; (un)ordered tests are expanded to une and oeq so verify
757 define i1 @test_dcmpuno(double %a, double %b) #0 {
758 ; SPE-LABEL: test_dcmpuno:
759 ; SPE: # %bb.0: # %entry
760 ; SPE-NEXT: evmergelo 5, 5, 6
761 ; SPE-NEXT: evmergelo 3, 3, 4
762 ; SPE-NEXT: li 7, 1
763 ; SPE-NEXT: efdcmpeq 0, 3, 3
764 ; SPE-NEXT: efdcmpeq 1, 5, 5
765 ; SPE-NEXT: crand 20, 5, 1
766 ; SPE-NEXT: bc 12, 20, .LBB35_2
767 ; SPE-NEXT: # %bb.1: # %entry
768 ; SPE-NEXT: ori 3, 7, 0
769 ; SPE-NEXT: blr
770 ; SPE-NEXT: .LBB35_2: # %entry
771 ; SPE-NEXT: li 3, 0
772 ; SPE-NEXT: blr
773 ;
774 ; EFPU2-LABEL: test_dcmpuno:
775 ; EFPU2: # %bb.0: # %entry
776 ; EFPU2-NEXT: mflr 0
777 ; EFPU2-NEXT: stw 0, 4(1)
778 ; EFPU2-NEXT: stwu 1, -16(1)
779 ; EFPU2-NEXT: bl __unorddf2
780 ; EFPU2-NEXT: cntlzw 3, 3
781 ; EFPU2-NEXT: not 3, 3
782 ; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31
783 ; EFPU2-NEXT: lwz 0, 20(1)
784 ; EFPU2-NEXT: addi 1, 1, 16
785 ; EFPU2-NEXT: mtlr 0
786 ; EFPU2-NEXT: blr
787 entry:
788 %r = fcmp uno double %a, %b
789 ret i1 %r
790 }
792 define i1 @test_dcmpord(double %a, double %b) #0 {
793 ; SPE-LABEL: test_dcmpord:
794 ; SPE: # %bb.0: # %entry
795 ; SPE-NEXT: evmergelo 3, 3, 4
796 ; SPE-NEXT: evmergelo 4, 5, 6
797 ; SPE-NEXT: li 7, 1
798 ; SPE-NEXT: efdcmpeq 0, 4, 4
799 ; SPE-NEXT: efdcmpeq 1, 3, 3
800 ; SPE-NEXT: crnand 20, 5, 1
801 ; SPE-NEXT: bc 12, 20, .LBB36_2
802 ; SPE-NEXT: # %bb.1: # %entry
803 ; SPE-NEXT: ori 3, 7, 0
804 ; SPE-NEXT: blr
805 ; SPE-NEXT: .LBB36_2: # %entry
806 ; SPE-NEXT: li 3, 0
807 ; SPE-NEXT: blr
808 ;
809 ; EFPU2-LABEL: test_dcmpord:
810 ; EFPU2: # %bb.0: # %entry
811 ; EFPU2-NEXT: mflr 0
812 ; EFPU2-NEXT: stw 0, 4(1)
813 ; EFPU2-NEXT: stwu 1, -16(1)
814 ; EFPU2-NEXT: bl __unorddf2
815 ; EFPU2-NEXT: cntlzw 3, 3
816 ; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31
817 ; EFPU2-NEXT: lwz 0, 20(1)
818 ; EFPU2-NEXT: addi 1, 1, 16
819 ; EFPU2-NEXT: mtlr 0
820 ; EFPU2-NEXT: blr
821 entry:
822 %r = fcmp ord double %a, %b
823 ret i1 %r
824 }
826 define i32 @test_dcmpgt(double %a, double %b) #0 {
827 ; SPE-LABEL: test_dcmpgt:
828 ; SPE: # %bb.0: # %entry
829 ; SPE-NEXT: stwu 1, -16(1)
830 ; SPE-NEXT: evmergelo 5, 5, 6
831 ; SPE-NEXT: evmergelo 3, 3, 4
832 ; SPE-NEXT: efdcmpgt 0, 3, 5
833 ; SPE-NEXT: ble 0, .LBB37_2
834 ; SPE-NEXT: # %bb.1: # %tr
835 ; SPE-NEXT: li 3, 1
836 ; SPE-NEXT: b .LBB37_3
837 ; SPE-NEXT: .LBB37_2: # %fa
838 ; SPE-NEXT: li 3, 0
839 ; SPE-NEXT: .LBB37_3: # %ret
840 ; SPE-NEXT: stw 3, 12(1)
841 ; SPE-NEXT: lwz 3, 12(1)
842 ; SPE-NEXT: addi 1, 1, 16
843 ; SPE-NEXT: blr
844 ;
845 ; EFPU2-LABEL: test_dcmpgt:
846 ; EFPU2: # %bb.0: # %entry
847 ; EFPU2-NEXT: mflr 0
848 ; EFPU2-NEXT: stw 0, 4(1)
849 ; EFPU2-NEXT: stwu 1, -16(1)
850 ; EFPU2-NEXT: bl __gtdf2
851 ; EFPU2-NEXT: cmpwi 3, 1
852 ; EFPU2-NEXT: blt 0, .LBB37_2
853 ; EFPU2-NEXT: # %bb.1: # %tr
854 ; EFPU2-NEXT: li 3, 1
855 ; EFPU2-NEXT: b .LBB37_3
856 ; EFPU2-NEXT: .LBB37_2: # %fa
857 ; EFPU2-NEXT: li 3, 0
858 ; EFPU2-NEXT: .LBB37_3: # %ret
859 ; EFPU2-NEXT: stw 3, 12(1)
860 ; EFPU2-NEXT: lwz 3, 12(1)
861 ; EFPU2-NEXT: lwz 0, 20(1)
862 ; EFPU2-NEXT: addi 1, 1, 16
863 ; EFPU2-NEXT: mtlr 0
864 ; EFPU2-NEXT: blr
865 entry:
866 %r = alloca i32, align 4
867 %c = fcmp ogt double %a, %b
868 br i1 %c, label %tr, label %fa
869 tr:
870 store i32 1, i32* %r, align 4
871 br label %ret
872 fa:
873 store i32 0, i32* %r, align 4
874 br label %ret
875 ret:
876 %0 = load i32, i32* %r, align 4
877 ret i32 %0
878 }
880 define i32 @test_dcmpugt(double %a, double %b) #0 {
881 ; SPE-LABEL: test_dcmpugt:
882 ; SPE: # %bb.0: # %entry
883 ; SPE-NEXT: stwu 1, -16(1)
884 ; SPE-NEXT: evmergelo 3, 3, 4
885 ; SPE-NEXT: evmergelo 4, 5, 6
886 ; SPE-NEXT: efdcmpeq 0, 4, 4
887 ; SPE-NEXT: bc 4, 1, .LBB38_4
888 ; SPE-NEXT: # %bb.1: # %entry
889 ; SPE-NEXT: efdcmpeq 0, 3, 3
890 ; SPE-NEXT: bc 4, 1, .LBB38_4
891 ; SPE-NEXT: # %bb.2: # %entry
892 ; SPE-NEXT: efdcmpgt 0, 3, 4
893 ; SPE-NEXT: bc 12, 1, .LBB38_4
894 ; SPE-NEXT: # %bb.3: # %fa
895 ; SPE-NEXT: li 3, 0
896 ; SPE-NEXT: b .LBB38_5
897 ; SPE-NEXT: .LBB38_4: # %tr
898 ; SPE-NEXT: li 3, 1
899 ; SPE-NEXT: .LBB38_5: # %ret
900 ; SPE-NEXT: stw 3, 12(1)
901 ; SPE-NEXT: lwz 3, 12(1)
902 ; SPE-NEXT: addi 1, 1, 16
903 ; SPE-NEXT: blr
904 ;
905 ; EFPU2-LABEL: test_dcmpugt:
906 ; EFPU2: # %bb.0: # %entry
907 ; EFPU2-NEXT: mflr 0
908 ; EFPU2-NEXT: stw 0, 4(1)
909 ; EFPU2-NEXT: stwu 1, -16(1)
910 ; EFPU2-NEXT: bl __ledf2
911 ; EFPU2-NEXT: cmpwi 3, 1
912 ; EFPU2-NEXT: blt 0, .LBB38_2
913 ; EFPU2-NEXT: # %bb.1: # %tr
914 ; EFPU2-NEXT: li 3, 1
915 ; EFPU2-NEXT: b .LBB38_3
916 ; EFPU2-NEXT: .LBB38_2: # %fa
917 ; EFPU2-NEXT: li 3, 0
918 ; EFPU2-NEXT: .LBB38_3: # %ret
919 ; EFPU2-NEXT: stw 3, 12(1)
920 ; EFPU2-NEXT: lwz 3, 12(1)
921 ; EFPU2-NEXT: lwz 0, 20(1)
922 ; EFPU2-NEXT: addi 1, 1, 16
923 ; EFPU2-NEXT: mtlr 0
924 ; EFPU2-NEXT: blr
925 entry:
926 %r = alloca i32, align 4
927 %c = fcmp ugt double %a, %b
928 br i1 %c, label %tr, label %fa
929 tr:
930 store i32 1, i32* %r, align 4
931 br label %ret
932 fa:
933 store i32 0, i32* %r, align 4
934 br label %ret
935 ret:
936 %0 = load i32, i32* %r, align 4
937 ret i32 %0
938 }
940 define i32 @test_dcmple(double %a, double %b) #0 {
941 ; SPE-LABEL: test_dcmple:
942 ; SPE: # %bb.0: # %entry
943 ; SPE-NEXT: stwu 1, -16(1)
944 ; SPE-NEXT: evmergelo 5, 5, 6
945 ; SPE-NEXT: evmergelo 3, 3, 4
946 ; SPE-NEXT: efdcmpgt 0, 3, 5
947 ; SPE-NEXT: bgt 0, .LBB39_2
948 ; SPE-NEXT: # %bb.1: # %tr
949 ; SPE-NEXT: li 3, 1
950 ; SPE-NEXT: b .LBB39_3
951 ; SPE-NEXT: .LBB39_2: # %fa
952 ; SPE-NEXT: li 3, 0
953 ; SPE-NEXT: .LBB39_3: # %ret
954 ; SPE-NEXT: stw 3, 12(1)
955 ; SPE-NEXT: lwz 3, 12(1)
956 ; SPE-NEXT: addi 1, 1, 16
957 ; SPE-NEXT: blr
958 ;
959 ; EFPU2-LABEL: test_dcmple:
960 ; EFPU2: # %bb.0: # %entry
961 ; EFPU2-NEXT: mflr 0
962 ; EFPU2-NEXT: stw 0, 4(1)
963 ; EFPU2-NEXT: stwu 1, -16(1)
964 ; EFPU2-NEXT: bl __gtdf2
965 ; EFPU2-NEXT: cmpwi 3, 0
966 ; EFPU2-NEXT: bgt 0, .LBB39_2
967 ; EFPU2-NEXT: # %bb.1: # %tr
968 ; EFPU2-NEXT: li 3, 1
969 ; EFPU2-NEXT: b .LBB39_3
970 ; EFPU2-NEXT: .LBB39_2: # %fa
971 ; EFPU2-NEXT: li 3, 0
972 ; EFPU2-NEXT: .LBB39_3: # %ret
973 ; EFPU2-NEXT: stw 3, 12(1)
974 ; EFPU2-NEXT: lwz 3, 12(1)
975 ; EFPU2-NEXT: lwz 0, 20(1)
976 ; EFPU2-NEXT: addi 1, 1, 16
977 ; EFPU2-NEXT: mtlr 0
978 ; EFPU2-NEXT: blr
979 entry:
980 %r = alloca i32, align 4
981 %c = fcmp ule double %a, %b
982 br i1 %c, label %tr, label %fa
983 tr:
984 store i32 1, i32* %r, align 4
985 br label %ret
986 fa:
987 store i32 0, i32* %r, align 4
988 br label %ret
989 ret:
990 %0 = load i32, i32* %r, align 4
991 ret i32 %0
992 }
994 define i32 @test_dcmpule(double %a, double %b) #0 {
995 ; SPE-LABEL: test_dcmpule:
996 ; SPE: # %bb.0: # %entry
997 ; SPE-NEXT: stwu 1, -16(1)
998 ; SPE-NEXT: evmergelo 5, 5, 6
999 ; SPE-NEXT: evmergelo 3, 3, 4
1000 ; SPE-NEXT: efdcmpgt 0, 3, 5
1001 ; SPE-NEXT: bgt 0, .LBB40_2
1002 ; SPE-NEXT: # %bb.1: # %tr
1003 ; SPE-NEXT: li 3, 1
1004 ; SPE-NEXT: b .LBB40_3
1005 ; SPE-NEXT: .LBB40_2: # %fa
1006 ; SPE-NEXT: li 3, 0
1007 ; SPE-NEXT: .LBB40_3: # %ret
1008 ; SPE-NEXT: stw 3, 12(1)
1009 ; SPE-NEXT: lwz 3, 12(1)
1010 ; SPE-NEXT: addi 1, 1, 16
1011 ; SPE-NEXT: blr
1012 ;
1013 ; EFPU2-LABEL: test_dcmpule:
1014 ; EFPU2: # %bb.0: # %entry
1015 ; EFPU2-NEXT: mflr 0
1016 ; EFPU2-NEXT: stw 0, 4(1)
1017 ; EFPU2-NEXT: stwu 1, -16(1)
1018 ; EFPU2-NEXT: bl __gtdf2
1019 ; EFPU2-NEXT: cmpwi 3, 0
1020 ; EFPU2-NEXT: bgt 0, .LBB40_2
1021 ; EFPU2-NEXT: # %bb.1: # %tr
1022 ; EFPU2-NEXT: li 3, 1
1023 ; EFPU2-NEXT: b .LBB40_3
1024 ; EFPU2-NEXT: .LBB40_2: # %fa
1025 ; EFPU2-NEXT: li 3, 0
1026 ; EFPU2-NEXT: .LBB40_3: # %ret
1027 ; EFPU2-NEXT: stw 3, 12(1)
1028 ; EFPU2-NEXT: lwz 3, 12(1)
1029 ; EFPU2-NEXT: lwz 0, 20(1)
1030 ; EFPU2-NEXT: addi 1, 1, 16
1031 ; EFPU2-NEXT: mtlr 0
1032 ; EFPU2-NEXT: blr
1033 entry:
1034 %r = alloca i32, align 4
1035 %c = fcmp ule double %a, %b
1036 br i1 %c, label %tr, label %fa
1037 tr:
1038 store i32 1, i32* %r, align 4
1039 br label %ret
1040 fa:
1041 store i32 0, i32* %r, align 4
1042 br label %ret
1043 ret:
1044 %0 = load i32, i32* %r, align 4
1045 ret i32 %0
1046 }
1048 ; The type of comparison found in C's if (x == y)
1049 define i32 @test_dcmpeq(double %a, double %b) #0 {
1050 ; SPE-LABEL: test_dcmpeq:
1051 ; SPE: # %bb.0: # %entry
1052 ; SPE-NEXT: stwu 1, -16(1)
1053 ; SPE-NEXT: evmergelo 5, 5, 6
1054 ; SPE-NEXT: evmergelo 3, 3, 4
1055 ; SPE-NEXT: efdcmpeq 0, 3, 5
1056 ; SPE-NEXT: ble 0, .LBB41_2
1057 ; SPE-NEXT: # %bb.1: # %tr
1058 ; SPE-NEXT: li 3, 1
1059 ; SPE-NEXT: b .LBB41_3
1060 ; SPE-NEXT: .LBB41_2: # %fa
1061 ; SPE-NEXT: li 3, 0
1062 ; SPE-NEXT: .LBB41_3: # %ret
1063 ; SPE-NEXT: stw 3, 12(1)
1064 ; SPE-NEXT: lwz 3, 12(1)
1065 ; SPE-NEXT: addi 1, 1, 16
1066 ; SPE-NEXT: blr
1067 ;
1068 ; EFPU2-LABEL: test_dcmpeq:
1069 ; EFPU2: # %bb.0: # %entry
1070 ; EFPU2-NEXT: mflr 0
1071 ; EFPU2-NEXT: stw 0, 4(1)
1072 ; EFPU2-NEXT: stwu 1, -16(1)
1073 ; EFPU2-NEXT: bl __nedf2
1074 ; EFPU2-NEXT: cmplwi 3, 0
1075 ; EFPU2-NEXT: bne 0, .LBB41_2
1076 ; EFPU2-NEXT: # %bb.1: # %tr
1077 ; EFPU2-NEXT: li 3, 1
1078 ; EFPU2-NEXT: b .LBB41_3
1079 ; EFPU2-NEXT: .LBB41_2: # %fa
1080 ; EFPU2-NEXT: li 3, 0
1081 ; EFPU2-NEXT: .LBB41_3: # %ret
1082 ; EFPU2-NEXT: stw 3, 12(1)
1083 ; EFPU2-NEXT: lwz 3, 12(1)
1084 ; EFPU2-NEXT: lwz 0, 20(1)
1085 ; EFPU2-NEXT: addi 1, 1, 16
1086 ; EFPU2-NEXT: mtlr 0
1087 ; EFPU2-NEXT: blr
1088 entry:
1089 %r = alloca i32, align 4
1090 %c = fcmp oeq double %a, %b
1091 br i1 %c, label %tr, label %fa
1092 tr:
1093 store i32 1, i32* %r, align 4
1094 br label %ret
1095 fa:
1096 store i32 0, i32* %r, align 4
1097 br label %ret
1098 ret:
1099 %0 = load i32, i32* %r, align 4
1100 ret i32 %0
1101 }
1103 define i32 @test_dcmpueq(double %a, double %b) #0 {
1104 ; SPE-LABEL: test_dcmpueq:
1105 ; SPE: # %bb.0: # %entry
1106 ; SPE-NEXT: stwu 1, -16(1)
1107 ; SPE-NEXT: evmergelo 5, 5, 6
1108 ; SPE-NEXT: evmergelo 3, 3, 4
1109 ; SPE-NEXT: efdcmplt 0, 3, 5
1110 ; SPE-NEXT: bc 12, 1, .LBB42_3
1111 ; SPE-NEXT: # %bb.1: # %entry
1112 ; SPE-NEXT: efdcmpgt 0, 3, 5
1113 ; SPE-NEXT: bc 12, 1, .LBB42_3
1114 ; SPE-NEXT: # %bb.2: # %tr
1115 ; SPE-NEXT: li 3, 1
1116 ; SPE-NEXT: b .LBB42_4
1117 ; SPE-NEXT: .LBB42_3: # %fa
1118 ; SPE-NEXT: li 3, 0
1119 ; SPE-NEXT: .LBB42_4: # %ret
1120 ; SPE-NEXT: stw 3, 12(1)
1121 ; SPE-NEXT: lwz 3, 12(1)
1122 ; SPE-NEXT: addi 1, 1, 16
1123 ; SPE-NEXT: blr
1124 ;
1125 ; EFPU2-LABEL: test_dcmpueq:
1126 ; EFPU2: # %bb.0: # %entry
1127 ; EFPU2-NEXT: mflr 0
1128 ; EFPU2-NEXT: stw 0, 4(1)
1129 ; EFPU2-NEXT: stwu 1, -80(1)
1130 ; EFPU2-NEXT: mfcr 12
1131 ; EFPU2-NEXT: stw 12, 76(1)
1132 ; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
1133 ; EFPU2-NEXT: mr 27, 3
1134 ; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
1135 ; EFPU2-NEXT: mr 28, 4
1136 ; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
1137 ; EFPU2-NEXT: mr 29, 5
1138 ; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
1139 ; EFPU2-NEXT: mr 30, 6
1140 ; EFPU2-NEXT: bl __eqdf2
1141 ; EFPU2-NEXT: cmpwi 2, 3, 0
1142 ; EFPU2-NEXT: mr 3, 27
1143 ; EFPU2-NEXT: mr 4, 28
1144 ; EFPU2-NEXT: mr 5, 29
1145 ; EFPU2-NEXT: mr 6, 30
1146 ; EFPU2-NEXT: bl __unorddf2
1147 ; EFPU2-NEXT: bc 12, 10, .LBB42_3
1148 ; EFPU2-NEXT: # %bb.1: # %entry
1149 ; EFPU2-NEXT: cmpwi 3, 0
1150 ; EFPU2-NEXT: bc 4, 2, .LBB42_3
1151 ; EFPU2-NEXT: # %bb.2: # %fa
1152 ; EFPU2-NEXT: li 3, 0
1153 ; EFPU2-NEXT: b .LBB42_4
1154 ; EFPU2-NEXT: .LBB42_3: # %tr
1155 ; EFPU2-NEXT: li 3, 1
1156 ; EFPU2-NEXT: .LBB42_4: # %ret
1157 ; EFPU2-NEXT: stw 3, 20(1)
1158 ; EFPU2-NEXT: lwz 3, 20(1)
1159 ; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
1160 ; EFPU2-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
1161 ; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
1162 ; EFPU2-NEXT: lwz 12, 76(1)
1163 ; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
1164 ; EFPU2-NEXT: mtcrf 32, 12 # cr2
1165 ; EFPU2-NEXT: lwz 0, 84(1)
1166 ; EFPU2-NEXT: addi 1, 1, 80
1167 ; EFPU2-NEXT: mtlr 0
1168 ; EFPU2-NEXT: blr
1169 entry:
1170 %r = alloca i32, align 4
1171 %c = fcmp ueq double %a, %b
1172 br i1 %c, label %tr, label %fa
1173 tr:
1174 store i32 1, i32* %r, align 4
1175 br label %ret
1176 fa:
1177 store i32 0, i32* %r, align 4
1178 br label %ret
1179 ret:
1180 %0 = load i32, i32* %r, align 4
1181 ret i32 %0
1182 }
1184 define i1 @test_dcmpne(double %a, double %b) #0 {
1185 ; SPE-LABEL: test_dcmpne:
1186 ; SPE: # %bb.0: # %entry
1187 ; SPE-NEXT: evmergelo 5, 5, 6
1188 ; SPE-NEXT: evmergelo 3, 3, 4
1189 ; SPE-NEXT: li 7, 1
1190 ; SPE-NEXT: efdcmplt 0, 3, 5
1191 ; SPE-NEXT: efdcmpgt 1, 3, 5
1192 ; SPE-NEXT: crnor 20, 5, 1
1193 ; SPE-NEXT: bc 12, 20, .LBB43_2
1194 ; SPE-NEXT: # %bb.1: # %entry
1195 ; SPE-NEXT: ori 3, 7, 0
1196 ; SPE-NEXT: blr
1197 ; SPE-NEXT: .LBB43_2: # %entry
1198 ; SPE-NEXT: li 3, 0
1199 ; SPE-NEXT: blr
1200 ;
1201 ; EFPU2-LABEL: test_dcmpne:
1202 ; EFPU2: # %bb.0: # %entry
1203 ; EFPU2-NEXT: mflr 0
1204 ; EFPU2-NEXT: stw 0, 4(1)
1205 ; EFPU2-NEXT: stwu 1, -80(1)
1206 ; EFPU2-NEXT: mfcr 12
1207 ; EFPU2-NEXT: stw 12, 76(1)
1208 ; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
1209 ; EFPU2-NEXT: mr 27, 3
1210 ; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
1211 ; EFPU2-NEXT: mr 28, 4
1212 ; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
1213 ; EFPU2-NEXT: mr 29, 5
1214 ; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
1215 ; EFPU2-NEXT: mr 30, 6
1216 ; EFPU2-NEXT: bl __unorddf2
1217 ; EFPU2-NEXT: cmpwi 2, 3, 0
1218 ; EFPU2-NEXT: mr 3, 27
1219 ; EFPU2-NEXT: mr 4, 28
1220 ; EFPU2-NEXT: mr 5, 29
1221 ; EFPU2-NEXT: mr 6, 30
1222 ; EFPU2-NEXT: bl __eqdf2
1223 ; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
1224 ; EFPU2-NEXT: cmpwi 3, 0
1225 ; EFPU2-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
1226 ; EFPU2-NEXT: li 4, 1
1227 ; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
1228 ; EFPU2-NEXT: crorc 20, 2, 10
1229 ; EFPU2-NEXT: lwz 12, 76(1)
1230 ; EFPU2-NEXT: bc 12, 20, .LBB43_2
1231 ; EFPU2-NEXT: # %bb.1: # %entry
1232 ; EFPU2-NEXT: ori 3, 4, 0
1233 ; EFPU2-NEXT: b .LBB43_3
1234 ; EFPU2-NEXT: .LBB43_2: # %entry
1235 ; EFPU2-NEXT: li 3, 0
1236 ; EFPU2-NEXT: .LBB43_3: # %entry
1237 ; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
1238 ; EFPU2-NEXT: mtcrf 32, 12 # cr2
1239 ; EFPU2-NEXT: lwz 0, 84(1)
1240 ; EFPU2-NEXT: addi 1, 1, 80
1241 ; EFPU2-NEXT: mtlr 0
1242 ; EFPU2-NEXT: blr
1243 entry:
1244 %r = fcmp one double %a, %b
1245 ret i1 %r
1246 }
1248 define i32 @test_dcmpune(double %a, double %b) #0 {
1249 ; SPE-LABEL: test_dcmpune:
1250 ; SPE: # %bb.0: # %entry
1251 ; SPE-NEXT: stwu 1, -16(1)
1252 ; SPE-NEXT: evmergelo 5, 5, 6
1253 ; SPE-NEXT: evmergelo 3, 3, 4
1254 ; SPE-NEXT: efdcmpeq 0, 3, 5
1255 ; SPE-NEXT: bgt 0, .LBB44_2
1256 ; SPE-NEXT: # %bb.1: # %tr
1257 ; SPE-NEXT: li 3, 1
1258 ; SPE-NEXT: b .LBB44_3
1259 ; SPE-NEXT: .LBB44_2: # %fa
1260 ; SPE-NEXT: li 3, 0
1261 ; SPE-NEXT: .LBB44_3: # %ret
1262 ; SPE-NEXT: stw 3, 12(1)
1263 ; SPE-NEXT: lwz 3, 12(1)
1264 ; SPE-NEXT: addi 1, 1, 16
1265 ; SPE-NEXT: blr
1266 ;
1267 ; EFPU2-LABEL: test_dcmpune:
1268 ; EFPU2: # %bb.0: # %entry
1269 ; EFPU2-NEXT: mflr 0
1270 ; EFPU2-NEXT: stw 0, 4(1)
1271 ; EFPU2-NEXT: stwu 1, -16(1)
1272 ; EFPU2-NEXT: bl __eqdf2
1273 ; EFPU2-NEXT: cmplwi 3, 0
1274 ; EFPU2-NEXT: beq 0, .LBB44_2
1275 ; EFPU2-NEXT: # %bb.1: # %tr
1276 ; EFPU2-NEXT: li 3, 1
1277 ; EFPU2-NEXT: b .LBB44_3
1278 ; EFPU2-NEXT: .LBB44_2: # %fa
1279 ; EFPU2-NEXT: li 3, 0
1280 ; EFPU2-NEXT: .LBB44_3: # %ret
1281 ; EFPU2-NEXT: stw 3, 12(1)
1282 ; EFPU2-NEXT: lwz 3, 12(1)
1283 ; EFPU2-NEXT: lwz 0, 20(1)
1284 ; EFPU2-NEXT: addi 1, 1, 16
1285 ; EFPU2-NEXT: mtlr 0
1286 ; EFPU2-NEXT: blr
1287 entry:
1288 %r = alloca i32, align 4
1289 %c = fcmp une double %a, %b
1290 br i1 %c, label %tr, label %fa
1291 tr:
1292 store i32 1, i32* %r, align 4
1293 br label %ret
1294 fa:
1295 store i32 0, i32* %r, align 4
1296 br label %ret
1297 ret:
1298 %0 = load i32, i32* %r, align 4
1299 ret i32 %0
1300 }
1302 define i32 @test_dcmplt(double %a, double %b) #0 {
1303 ; SPE-LABEL: test_dcmplt:
1304 ; SPE: # %bb.0: # %entry
1305 ; SPE-NEXT: stwu 1, -16(1)
1306 ; SPE-NEXT: evmergelo 5, 5, 6
1307 ; SPE-NEXT: evmergelo 3, 3, 4
1308 ; SPE-NEXT: efdcmplt 0, 3, 5
1309 ; SPE-NEXT: ble 0, .LBB45_2
1310 ; SPE-NEXT: # %bb.1: # %tr
1311 ; SPE-NEXT: li 3, 1
1312 ; SPE-NEXT: b .LBB45_3
1313 ; SPE-NEXT: .LBB45_2: # %fa
1314 ; SPE-NEXT: li 3, 0
1315 ; SPE-NEXT: .LBB45_3: # %ret
1316 ; SPE-NEXT: stw 3, 12(1)
1317 ; SPE-NEXT: lwz 3, 12(1)
1318 ; SPE-NEXT: addi 1, 1, 16
1319 ; SPE-NEXT: blr
1320 ;
1321 ; EFPU2-LABEL: test_dcmplt:
1322 ; EFPU2: # %bb.0: # %entry
1323 ; EFPU2-NEXT: mflr 0
1324 ; EFPU2-NEXT: stw 0, 4(1)
1325 ; EFPU2-NEXT: stwu 1, -16(1)
1326 ; EFPU2-NEXT: bl __ltdf2
1327 ; EFPU2-NEXT: cmpwi 3, -1
1328 ; EFPU2-NEXT: bgt 0, .LBB45_2
1329 ; EFPU2-NEXT: # %bb.1: # %tr
1330 ; EFPU2-NEXT: li 3, 1
1331 ; EFPU2-NEXT: b .LBB45_3
1332 ; EFPU2-NEXT: .LBB45_2: # %fa
1333 ; EFPU2-NEXT: li 3, 0
1334 ; EFPU2-NEXT: .LBB45_3: # %ret
1335 ; EFPU2-NEXT: stw 3, 12(1)
1336 ; EFPU2-NEXT: lwz 3, 12(1)
1337 ; EFPU2-NEXT: lwz 0, 20(1)
1338 ; EFPU2-NEXT: addi 1, 1, 16
1339 ; EFPU2-NEXT: mtlr 0
1340 ; EFPU2-NEXT: blr
1341 entry:
1342 %r = alloca i32, align 4
1343 %c = fcmp olt double %a, %b
1344 br i1 %c, label %tr, label %fa
1345 tr:
1346 store i32 1, i32* %r, align 4
1347 br label %ret
1348 fa:
1349 store i32 0, i32* %r, align 4
1350 br label %ret
1351 ret:
1352 %0 = load i32, i32* %r, align 4
1353 ret i32 %0
1354 }
1356 define i32 @test_dcmpult(double %a, double %b) #0 {
1357 ; SPE-LABEL: test_dcmpult:
1358 ; SPE: # %bb.0: # %entry
1359 ; SPE-NEXT: stwu 1, -16(1)
1360 ; SPE-NEXT: evmergelo 3, 3, 4
1361 ; SPE-NEXT: evmergelo 4, 5, 6
1362 ; SPE-NEXT: efdcmpeq 0, 4, 4
1363 ; SPE-NEXT: bc 4, 1, .LBB46_4
1364 ; SPE-NEXT: # %bb.1: # %entry
1365 ; SPE-NEXT: efdcmpeq 0, 3, 3
1366 ; SPE-NEXT: bc 4, 1, .LBB46_4
1367 ; SPE-NEXT: # %bb.2: # %entry
1368 ; SPE-NEXT: efdcmplt 0, 3, 4
1369 ; SPE-NEXT: bc 12, 1, .LBB46_4
1370 ; SPE-NEXT: # %bb.3: # %fa
1371 ; SPE-NEXT: li 3, 0
1372 ; SPE-NEXT: b .LBB46_5
1373 ; SPE-NEXT: .LBB46_4: # %tr
1374 ; SPE-NEXT: li 3, 1
1375 ; SPE-NEXT: .LBB46_5: # %ret
1376 ; SPE-NEXT: stw 3, 12(1)
1377 ; SPE-NEXT: lwz 3, 12(1)
1378 ; SPE-NEXT: addi 1, 1, 16
1379 ; SPE-NEXT: blr
1380 ;
1381 ; EFPU2-LABEL: test_dcmpult:
1382 ; EFPU2: # %bb.0: # %entry
1383 ; EFPU2-NEXT: mflr 0
1384 ; EFPU2-NEXT: stw 0, 4(1)
1385 ; EFPU2-NEXT: stwu 1, -16(1)
1386 ; EFPU2-NEXT: bl __gedf2
1387 ; EFPU2-NEXT: cmpwi 3, -1
1388 ; EFPU2-NEXT: bgt 0, .LBB46_2
1389 ; EFPU2-NEXT: # %bb.1: # %tr
1390 ; EFPU2-NEXT: li 3, 1
1391 ; EFPU2-NEXT: b .LBB46_3
1392 ; EFPU2-NEXT: .LBB46_2: # %fa
1393 ; EFPU2-NEXT: li 3, 0
1394 ; EFPU2-NEXT: .LBB46_3: # %ret
1395 ; EFPU2-NEXT: stw 3, 12(1)
1396 ; EFPU2-NEXT: lwz 3, 12(1)
1397 ; EFPU2-NEXT: lwz 0, 20(1)
1398 ; EFPU2-NEXT: addi 1, 1, 16
1399 ; EFPU2-NEXT: mtlr 0
1400 ; EFPU2-NEXT: blr
1401 entry:
1402 %r = alloca i32, align 4
1403 %c = fcmp ult double %a, %b
1404 br i1 %c, label %tr, label %fa
1405 tr:
1406 store i32 1, i32* %r, align 4
1407 br label %ret
1408 fa:
1409 store i32 0, i32* %r, align 4
1410 br label %ret
1411 ret:
1412 %0 = load i32, i32* %r, align 4
1413 ret i32 %0
1414 }
1416 define i1 @test_dcmpge(double %a, double %b) #0 {
1417 ; SPE-LABEL: test_dcmpge:
1418 ; SPE: # %bb.0: # %entry
1419 ; SPE-NEXT: evmergelo 3, 3, 4
1420 ; SPE-NEXT: evmergelo 4, 5, 6
1421 ; SPE-NEXT: li 7, 1
1422 ; SPE-NEXT: efdcmpeq 0, 4, 4
1423 ; SPE-NEXT: efdcmpeq 1, 3, 3
1424 ; SPE-NEXT: efdcmplt 5, 3, 4
1425 ; SPE-NEXT: crand 24, 5, 1
1426 ; SPE-NEXT: crorc 20, 21, 24
1427 ; SPE-NEXT: bc 12, 20, .LBB47_2
1428 ; SPE-NEXT: # %bb.1: # %entry
1429 ; SPE-NEXT: ori 3, 7, 0
1430 ; SPE-NEXT: blr
1431 ; SPE-NEXT: .LBB47_2: # %entry
1432 ; SPE-NEXT: li 3, 0
1433 ; SPE-NEXT: blr
1434 ;
1435 ; EFPU2-LABEL: test_dcmpge:
1436 ; EFPU2: # %bb.0: # %entry
1437 ; EFPU2-NEXT: mflr 0
1438 ; EFPU2-NEXT: stw 0, 4(1)
1439 ; EFPU2-NEXT: stwu 1, -16(1)
1440 ; EFPU2-NEXT: bl __gedf2
1441 ; EFPU2-NEXT: not 3, 3
1442 ; EFPU2-NEXT: srwi 3, 3, 31
1443 ; EFPU2-NEXT: lwz 0, 20(1)
1444 ; EFPU2-NEXT: addi 1, 1, 16
1445 ; EFPU2-NEXT: mtlr 0
1446 ; EFPU2-NEXT: blr
1447 entry:
1448 %r = fcmp oge double %a, %b
1449 ret i1 %r
1450 }
1452 define i32 @test_dcmpuge(double %a, double %b) #0 {
1453 ; SPE-LABEL: test_dcmpuge:
1454 ; SPE: # %bb.0: # %entry
1455 ; SPE-NEXT: stwu 1, -16(1)
1456 ; SPE-NEXT: evmergelo 5, 5, 6
1457 ; SPE-NEXT: evmergelo 3, 3, 4
1458 ; SPE-NEXT: efdcmplt 0, 3, 5
1459 ; SPE-NEXT: bgt 0, .LBB48_2
1460 ; SPE-NEXT: # %bb.1: # %tr
1461 ; SPE-NEXT: li 3, 1
1462 ; SPE-NEXT: b .LBB48_3
1463 ; SPE-NEXT: .LBB48_2: # %fa
1464 ; SPE-NEXT: li 3, 0
1465 ; SPE-NEXT: .LBB48_3: # %ret
1466 ; SPE-NEXT: stw 3, 12(1)
1467 ; SPE-NEXT: lwz 3, 12(1)
1468 ; SPE-NEXT: addi 1, 1, 16
1469 ; SPE-NEXT: blr
1470 ;
1471 ; EFPU2-LABEL: test_dcmpuge:
1472 ; EFPU2: # %bb.0: # %entry
1473 ; EFPU2-NEXT: mflr 0
1474 ; EFPU2-NEXT: stw 0, 4(1)
1475 ; EFPU2-NEXT: stwu 1, -16(1)
1476 ; EFPU2-NEXT: bl __ltdf2
1477 ; EFPU2-NEXT: cmpwi 3, 0
1478 ; EFPU2-NEXT: blt 0, .LBB48_2
1479 ; EFPU2-NEXT: # %bb.1: # %tr
1480 ; EFPU2-NEXT: li 3, 1
1481 ; EFPU2-NEXT: b .LBB48_3
1482 ; EFPU2-NEXT: .LBB48_2: # %fa
1483 ; EFPU2-NEXT: li 3, 0
1484 ; EFPU2-NEXT: .LBB48_3: # %ret
1485 ; EFPU2-NEXT: stw 3, 12(1)
1486 ; EFPU2-NEXT: lwz 3, 12(1)
1487 ; EFPU2-NEXT: lwz 0, 20(1)
1488 ; EFPU2-NEXT: addi 1, 1, 16
1489 ; EFPU2-NEXT: mtlr 0
1490 ; EFPU2-NEXT: blr
1491 entry:
1492 %r = alloca i32, align 4
1493 %c = fcmp uge double %a, %b
1494 br i1 %c, label %tr, label %fa
1495 tr:
1496 store i32 1, i32* %r, align 4
1497 br label %ret
1498 fa:
1499 store i32 0, i32* %r, align 4
1500 br label %ret
1501 ret:
1502 %0 = load i32, i32* %r, align 4
1503 ret i32 %0
1504 }
1506 define double @test_dselect(double %a, double %b, i1 %c) #0 {
1507 ; SPE-LABEL: test_dselect:
1508 ; SPE: # %bb.0: # %entry
1509 ; SPE-NEXT: andi. 7, 7, 1
1510 ; SPE-NEXT: evmergelo 5, 5, 6
1511 ; SPE-NEXT: evmergelo 4, 3, 4
1512 ; SPE-NEXT: bc 12, 1, .LBB49_2
1513 ; SPE-NEXT: # %bb.1: # %entry
1514 ; SPE-NEXT: evor 4, 5, 5
1515 ; SPE-NEXT: .LBB49_2: # %entry
1516 ; SPE-NEXT: evmergehi 3, 4, 4
1517 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
1518 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
1519 ; SPE-NEXT: blr
1520 ;
1521 ; EFPU2-LABEL: test_dselect:
1522 ; EFPU2: # %bb.0: # %entry
1523 ; EFPU2-NEXT: andi. 7, 7, 1
1524 ; EFPU2-NEXT: bclr 12, 1, 0
1525 ; EFPU2-NEXT: # %bb.1: # %entry
1526 ; EFPU2-NEXT: ori 3, 5, 0
1527 ; EFPU2-NEXT: ori 4, 6, 0
1528 ; EFPU2-NEXT: blr
1529 entry:
1530 %r = select i1 %c, double %a, double %b
1531 ret double %r
1532 }
1534 define i32 @test_dtoui(double %a) #0 {
1535 ; SPE-LABEL: test_dtoui:
1536 ; SPE: # %bb.0: # %entry
1537 ; SPE-NEXT: evmergelo 3, 3, 4
1538 ; SPE-NEXT: efdctuiz 3, 3
1539 ; SPE-NEXT: blr
1540 ;
1541 ; EFPU2-LABEL: test_dtoui:
1542 ; EFPU2: # %bb.0: # %entry
1543 ; EFPU2-NEXT: mflr 0
1544 ; EFPU2-NEXT: stw 0, 4(1)
1545 ; EFPU2-NEXT: stwu 1, -16(1)
1546 ; EFPU2-NEXT: bl __fixunsdfsi
1547 ; EFPU2-NEXT: lwz 0, 20(1)
1548 ; EFPU2-NEXT: addi 1, 1, 16
1549 ; EFPU2-NEXT: mtlr 0
1550 ; EFPU2-NEXT: blr
1551 entry:
1552 %v = fptoui double %a to i32
1553 ret i32 %v
1554 }
1556 define i32 @test_dtosi(double %a) #0 {
1557 ; SPE-LABEL: test_dtosi:
1558 ; SPE: # %bb.0: # %entry
1559 ; SPE-NEXT: evmergelo 3, 3, 4
1560 ; SPE-NEXT: efdctsiz 3, 3
1561 ; SPE-NEXT: blr
1562 ;
1563 ; EFPU2-LABEL: test_dtosi:
1564 ; EFPU2: # %bb.0: # %entry
1565 ; EFPU2-NEXT: mflr 0
1566 ; EFPU2-NEXT: stw 0, 4(1)
1567 ; EFPU2-NEXT: stwu 1, -16(1)
1568 ; EFPU2-NEXT: bl __fixdfsi
1569 ; EFPU2-NEXT: lwz 0, 20(1)
1570 ; EFPU2-NEXT: addi 1, 1, 16
1571 ; EFPU2-NEXT: mtlr 0
1572 ; EFPU2-NEXT: blr
1573 entry:
1574 %v = fptosi double %a to i32
1575 ret i32 %v
1576 }
1578 define double @test_dfromui(i32 %a) #0 {
1579 ; SPE-LABEL: test_dfromui:
1580 ; SPE: # %bb.0: # %entry
1581 ; SPE-NEXT: efdcfui 4, 3
1582 ; SPE-NEXT: evmergehi 3, 4, 4
1583 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
1584 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
1585 ; SPE-NEXT: blr
1586 ;
1587 ; EFPU2-LABEL: test_dfromui:
1588 ; EFPU2: # %bb.0: # %entry
1589 ; EFPU2-NEXT: mflr 0
1590 ; EFPU2-NEXT: stw 0, 4(1)
1591 ; EFPU2-NEXT: stwu 1, -16(1)
1592 ; EFPU2-NEXT: bl __floatunsidf
1593 ; EFPU2-NEXT: lwz 0, 20(1)
1594 ; EFPU2-NEXT: addi 1, 1, 16
1595 ; EFPU2-NEXT: mtlr 0
1596 ; EFPU2-NEXT: blr
1597 entry:
1598 %v = uitofp i32 %a to double
1599 ret double %v
1600 }
1602 define double @test_dfromsi(i32 %a) #0 {
1603 ; SPE-LABEL: test_dfromsi:
1604 ; SPE: # %bb.0: # %entry
1605 ; SPE-NEXT: efdcfsi 4, 3
1606 ; SPE-NEXT: evmergehi 3, 4, 4
1607 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
1608 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
1609 ; SPE-NEXT: blr
1610 ;
1611 ; EFPU2-LABEL: test_dfromsi:
1612 ; EFPU2: # %bb.0: # %entry
1613 ; EFPU2-NEXT: mflr 0
1614 ; EFPU2-NEXT: stw 0, 4(1)
1615 ; EFPU2-NEXT: stwu 1, -16(1)
1616 ; EFPU2-NEXT: bl __floatsidf
1617 ; EFPU2-NEXT: lwz 0, 20(1)
1618 ; EFPU2-NEXT: addi 1, 1, 16
1619 ; EFPU2-NEXT: mtlr 0
1620 ; EFPU2-NEXT: blr
1621 entry:
1622 %v = sitofp i32 %a to double
1623 ret double %v
1624 }
1626 declare double @test_spill_spe_regs(double, double);
1627 define dso_local void @test_func2() #0 {
1628 ; CHECK-LABEL: test_func2:
1629 ; CHECK: # %bb.0: # %entry
1630 ; CHECK-NEXT: blr
1631 entry:
1632 ret void
1633 }
1635 declare void @test_memset(i8* nocapture writeonly, i8, i32, i1)
1636 @global_var1 = global i32 0, align 4
1637 define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) #0 {
1638 ; SPE-LABEL: test_spill:
1639 ; SPE: # %bb.0: # %entry
1640 ; SPE-NEXT: mflr 0
1641 ; SPE-NEXT: stw 0, 4(1)
1642 ; SPE-NEXT: stwu 1, -272(1)
1643 ; SPE-NEXT: li 5, 256
1644 ; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill
1645 ; SPE-NEXT: li 5, 264
1646 ; SPE-NEXT: evstddx 31, 1, 5 # 8-byte Folded Spill
1647 ; SPE-NEXT: li 5, .LCPI55_0@l
1648 ; SPE-NEXT: lis 6, .LCPI55_0@ha
1649 ; SPE-NEXT: evlddx 5, 6, 5
1650 ; SPE-NEXT: evstdd 14, 128(1) # 8-byte Folded Spill
1651 ; SPE-NEXT: evstdd 15, 136(1) # 8-byte Folded Spill
1652 ; SPE-NEXT: evstdd 16, 144(1) # 8-byte Folded Spill
1653 ; SPE-NEXT: evstdd 17, 152(1) # 8-byte Folded Spill
1654 ; SPE-NEXT: evstdd 18, 160(1) # 8-byte Folded Spill
1655 ; SPE-NEXT: evstdd 19, 168(1) # 8-byte Folded Spill
1656 ; SPE-NEXT: evstdd 20, 176(1) # 8-byte Folded Spill
1657 ; SPE-NEXT: evstdd 21, 184(1) # 8-byte Folded Spill
1658 ; SPE-NEXT: evstdd 22, 192(1) # 8-byte Folded Spill
1659 ; SPE-NEXT: evstdd 23, 200(1) # 8-byte Folded Spill
1660 ; SPE-NEXT: evstdd 24, 208(1) # 8-byte Folded Spill
1661 ; SPE-NEXT: evstdd 25, 216(1) # 8-byte Folded Spill
1662 ; SPE-NEXT: evstdd 26, 224(1) # 8-byte Folded Spill
1663 ; SPE-NEXT: evstdd 27, 232(1) # 8-byte Folded Spill
1664 ; SPE-NEXT: evstdd 28, 240(1) # 8-byte Folded Spill
1665 ; SPE-NEXT: evstdd 29, 248(1) # 8-byte Folded Spill
1666 ; SPE-NEXT: evmergelo 3, 3, 4
1667 ; SPE-NEXT: lwz 4, 280(1)
1668 ; SPE-NEXT: efdadd 3, 3, 3
1669 ; SPE-NEXT: efdadd 3, 3, 5
1670 ; SPE-NEXT: evstdd 3, 24(1) # 8-byte Folded Spill
1671 ; SPE-NEXT: stw 4, 20(1) # 4-byte Folded Spill
1672 ; SPE-NEXT: #APP
1673 ; SPE-NEXT: #NO_APP
1674 ; SPE-NEXT: addi 3, 1, 76
1675 ; SPE-NEXT: li 4, 0
1676 ; SPE-NEXT: li 5, 24
1677 ; SPE-NEXT: li 6, 1
1678 ; SPE-NEXT: li 30, 0
1679 ; SPE-NEXT: bl test_memset
1680 ; SPE-NEXT: lwz 3, 20(1) # 4-byte Folded Reload
1681 ; SPE-NEXT: stw 30, 0(3)
1682 ; SPE-NEXT: bl test_func2
1683 ; SPE-NEXT: addi 3, 1, 32
1684 ; SPE-NEXT: li 4, 0
1685 ; SPE-NEXT: li 5, 20
1686 ; SPE-NEXT: li 6, 1
1687 ; SPE-NEXT: bl test_memset
1688 ; SPE-NEXT: evldd 4, 24(1) # 8-byte Folded Reload
1689 ; SPE-NEXT: li 5, 264
1690 ; SPE-NEXT: evmergehi 3, 4, 4
1691 ; SPE-NEXT: evlddx 31, 1, 5 # 8-byte Folded Reload
1692 ; SPE-NEXT: li 5, 256
1693 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
1694 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
1695 ; SPE-NEXT: evlddx 30, 1, 5 # 8-byte Folded Reload
1696 ; SPE-NEXT: evldd 29, 248(1) # 8-byte Folded Reload
1697 ; SPE-NEXT: evldd 28, 240(1) # 8-byte Folded Reload
1698 ; SPE-NEXT: evldd 27, 232(1) # 8-byte Folded Reload
1699 ; SPE-NEXT: evldd 26, 224(1) # 8-byte Folded Reload
1700 ; SPE-NEXT: evldd 25, 216(1) # 8-byte Folded Reload
1701 ; SPE-NEXT: evldd 24, 208(1) # 8-byte Folded Reload
1702 ; SPE-NEXT: evldd 23, 200(1) # 8-byte Folded Reload
1703 ; SPE-NEXT: evldd 22, 192(1) # 8-byte Folded Reload
1704 ; SPE-NEXT: evldd 21, 184(1) # 8-byte Folded Reload
1705 ; SPE-NEXT: evldd 20, 176(1) # 8-byte Folded Reload
1706 ; SPE-NEXT: evldd 19, 168(1) # 8-byte Folded Reload
1707 ; SPE-NEXT: evldd 18, 160(1) # 8-byte Folded Reload
1708 ; SPE-NEXT: evldd 17, 152(1) # 8-byte Folded Reload
1709 ; SPE-NEXT: evldd 16, 144(1) # 8-byte Folded Reload
1710 ; SPE-NEXT: evldd 15, 136(1) # 8-byte Folded Reload
1711 ; SPE-NEXT: evldd 14, 128(1) # 8-byte Folded Reload
1712 ; SPE-NEXT: lwz 0, 276(1)
1713 ; SPE-NEXT: addi 1, 1, 272
1714 ; SPE-NEXT: mtlr 0
1715 ; SPE-NEXT: blr
1716 ;
1717 ; EFPU2-LABEL: test_spill:
1718 ; EFPU2: # %bb.0: # %entry
1719 ; EFPU2-NEXT: mflr 0
1720 ; EFPU2-NEXT: stw 0, 4(1)
1721 ; EFPU2-NEXT: stwu 1, -144(1)
1722 ; EFPU2-NEXT: mr 5, 3
1723 ; EFPU2-NEXT: mr 6, 4
1724 ; EFPU2-NEXT: evstdd 27, 104(1) # 8-byte Folded Spill
1725 ; EFPU2-NEXT: evstdd 28, 112(1) # 8-byte Folded Spill
1726 ; EFPU2-NEXT: evstdd 29, 120(1) # 8-byte Folded Spill
1727 ; EFPU2-NEXT: evstdd 30, 128(1) # 8-byte Folded Spill
1728 ; EFPU2-NEXT: lwz 28, 152(1)
1729 ; EFPU2-NEXT: bl __adddf3
1730 ; EFPU2-NEXT: lis 5, 16393
1731 ; EFPU2-NEXT: lis 6, -4069
1732 ; EFPU2-NEXT: ori 5, 5, 8697
1733 ; EFPU2-NEXT: ori 6, 6, 34414
1734 ; EFPU2-NEXT: #APP
1735 ; EFPU2-NEXT: #NO_APP
1736 ; EFPU2-NEXT: bl __adddf3
1737 ; EFPU2-NEXT: mr 30, 3
1738 ; EFPU2-NEXT: mr 29, 4
1739 ; EFPU2-NEXT: addi 3, 1, 52
1740 ; EFPU2-NEXT: li 4, 0
1741 ; EFPU2-NEXT: li 5, 24
1742 ; EFPU2-NEXT: li 6, 1
1743 ; EFPU2-NEXT: li 27, 0
1744 ; EFPU2-NEXT: bl test_memset
1745 ; EFPU2-NEXT: stw 27, 0(28)
1746 ; EFPU2-NEXT: bl test_func2
1747 ; EFPU2-NEXT: addi 3, 1, 8
1748 ; EFPU2-NEXT: li 4, 0
1749 ; EFPU2-NEXT: li 5, 20
1750 ; EFPU2-NEXT: li 6, 1
1751 ; EFPU2-NEXT: bl test_memset
1752 ; EFPU2-NEXT: mr 3, 30
1753 ; EFPU2-NEXT: mr 4, 29
1754 ; EFPU2-NEXT: evldd 30, 128(1) # 8-byte Folded Reload
1755 ; EFPU2-NEXT: evldd 29, 120(1) # 8-byte Folded Reload
1756 ; EFPU2-NEXT: evldd 28, 112(1) # 8-byte Folded Reload
1757 ; EFPU2-NEXT: evldd 27, 104(1) # 8-byte Folded Reload
1758 ; EFPU2-NEXT: lwz 0, 148(1)
1759 ; EFPU2-NEXT: addi 1, 1, 144
1760 ; EFPU2-NEXT: mtlr 0
1761 ; EFPU2-NEXT: blr
1762 entry:
1763 %v1 = alloca [13 x i32], align 4
1764 %v2 = alloca [11 x i32], align 4
1765 %0 = fadd double %a, %a
1766 call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
1767 %1 = fadd double %0, 3.14159
1768 %2 = bitcast [13 x i32]* %v1 to i8*
1769 call void @test_memset(i8* align 4 %2, i8 0, i32 24, i1 true)
1770 store i32 0, i32* %a5, align 4
1771 call void @test_func2()
1772 %3 = bitcast [11 x i32]* %v2 to i8*
1773 call void @test_memset(i8* align 4 %3, i8 0, i32 20, i1 true)
1774 br label %return
1776 return:
1777 ret double %1
1779 }
1781 define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
1782 ; CHECK-LABEL: test_fma:
1783 ; CHECK: # %bb.0: # %entry
1784 ; CHECK-NEXT: mflr 0
1785 ; CHECK-NEXT: stw 0, 4(1)
1786 ; CHECK-NEXT: stwu 1, -32(1)
1787 ; CHECK-NEXT: cmpwi 3, 1
1788 ; CHECK-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
1789 ; CHECK-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
1790 ; CHECK-NEXT: blt 0, .LBB56_3
1791 ; CHECK-NEXT: # %bb.1: # %for.body.preheader
1792 ; CHECK-NEXT: mr 30, 3
1793 ; CHECK-NEXT: li 29, 0
1794 ; CHECK-NEXT: # implicit-def: $r5
1795 ; CHECK-NEXT: .LBB56_2: # %for.body
1796 ; CHECK-NEXT: #
1797 ; CHECK-NEXT: efscfsi 3, 29
1798 ; CHECK-NEXT: mr 4, 3
1799 ; CHECK-NEXT: bl fmaf
1800 ; CHECK-NEXT: addi 29, 29, 1
1801 ; CHECK-NEXT: cmplw 30, 29
1802 ; CHECK-NEXT: mr 5, 3
1803 ; CHECK-NEXT: bne 0, .LBB56_2
1804 ; CHECK-NEXT: b .LBB56_4
1805 ; CHECK-NEXT: .LBB56_3:
1806 ; CHECK-NEXT: # implicit-def: $r5
1807 ; CHECK-NEXT: .LBB56_4: # %for.cond.cleanup
1808 ; CHECK-NEXT: mr 3, 5
1809 ; CHECK-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
1810 ; CHECK-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
1811 ; CHECK-NEXT: lwz 0, 36(1)
1812 ; CHECK-NEXT: addi 1, 1, 32
1813 ; CHECK-NEXT: mtlr 0
1814 ; CHECK-NEXT: blr
1815 entry:
1816 %cmp8 = icmp sgt i32 %d, 0
1817 br i1 %cmp8, label %for.body, label %for.cond.cleanup
1819 for.cond.cleanup: ; preds = %for.body, %entry
1820 %e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ]
1821 ret float %e.0.lcssa
1823 for.body: ; preds = %for.body, %entry
1824 %f.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
1825 %e.09 = phi float [ %0, %for.body ], [ undef, %entry ]
1826 %conv = sitofp i32 %f.010 to float
1827 %0 = tail call float @llvm.fma.f32(float %conv, float %conv, float %e.09)
1828 %inc = add nuw nsw i32 %f.010, 1
1829 %exitcond = icmp eq i32 %inc, %d
1830 br i1 %exitcond, label %for.cond.cleanup, label %for.body
1831 }
1833 ; Function Attrs: nounwind readnone speculatable willreturn
1834 declare float @llvm.fma.f32(float, float, float) #1
1836 attributes #1 = { nounwind readnone speculatable willreturn }
1838 %struct.a = type { float, float }
1840 declare i32 @foo(double)
1842 define void @d(%struct.a* %e, %struct.a* %f) #0 {
1843 ; SPE-LABEL: d:
1844 ; SPE: # %bb.0: # %entry
1845 ; SPE-NEXT: mflr 0
1846 ; SPE-NEXT: stw 0, 4(1)
1847 ; SPE-NEXT: stwu 1, -48(1)
1848 ; SPE-NEXT: lwz 4, 0(4)
1849 ; SPE-NEXT: lwz 3, 0(3)
1850 ; SPE-NEXT: evstdd 29, 24(1) # 8-byte Folded Spill
1851 ; SPE-NEXT: efdcfs 29, 4
1852 ; SPE-NEXT: evstdd 28, 16(1) # 8-byte Folded Spill
1853 ; SPE-NEXT: mr 4, 29
1854 ; SPE-NEXT: evstdd 30, 32(1) # 8-byte Folded Spill
1855 ; SPE-NEXT: efdcfs 30, 3
1856 ; SPE-NEXT: evmergehi 3, 29, 29
1857 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
1858 ; SPE-NEXT: bl foo
1859 ; SPE-NEXT: mr 28, 3
1860 ; SPE-NEXT: evmergehi 3, 30, 30
1861 ; SPE-NEXT: mr 4, 30
1862 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
1863 ; SPE-NEXT: bl foo
1864 ; SPE-NEXT: efdcfsi 3, 28
1865 ; SPE-NEXT: evldd 30, 32(1) # 8-byte Folded Reload
1866 ; SPE-NEXT: efdmul 3, 29, 3
1867 ; SPE-NEXT: efscfd 3, 3
1868 ; SPE-NEXT: evldd 29, 24(1) # 8-byte Folded Reload
1869 ; SPE-NEXT: stw 3, 0(3)
1870 ; SPE-NEXT: evldd 28, 16(1) # 8-byte Folded Reload
1871 ; SPE-NEXT: lwz 0, 52(1)
1872 ; SPE-NEXT: addi 1, 1, 48
1873 ; SPE-NEXT: mtlr 0
1874 ; SPE-NEXT: blr
1875 ;
1876 ; EFPU2-LABEL: d:
1877 ; EFPU2: # %bb.0: # %entry
1878 ; EFPU2-NEXT: mflr 0
1879 ; EFPU2-NEXT: stw 0, 4(1)
1880 ; EFPU2-NEXT: stwu 1, -64(1)
1881 ; EFPU2-NEXT: lwz 3, 0(3)
1882 ; EFPU2-NEXT: evstdd 26, 16(1) # 8-byte Folded Spill
1883 ; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
1884 ; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
1885 ; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
1886 ; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
1887 ; EFPU2-NEXT: mr 30, 4
1888 ; EFPU2-NEXT: bl __extendsfdf2
1889 ; EFPU2-NEXT: mr 28, 3
1890 ; EFPU2-NEXT: lwz 3, 0(30)
1891 ; EFPU2-NEXT: mr 29, 4
1892 ; EFPU2-NEXT: bl __extendsfdf2
1893 ; EFPU2-NEXT: mr 30, 4
1894 ; EFPU2-NEXT: mr 27, 3
1895 ; EFPU2-NEXT: bl foo
1896 ; EFPU2-NEXT: mr 26, 3
1897 ; EFPU2-NEXT: mr 3, 28
1898 ; EFPU2-NEXT: mr 4, 29
1899 ; EFPU2-NEXT: bl foo
1900 ; EFPU2-NEXT: mr 3, 26
1901 ; EFPU2-NEXT: bl __floatsidf
1902 ; EFPU2-NEXT: mr 6, 4
1903 ; EFPU2-NEXT: mr 5, 3
1904 ; EFPU2-NEXT: mr 3, 27
1905 ; EFPU2-NEXT: mr 4, 30
1906 ; EFPU2-NEXT: bl __muldf3
1907 ; EFPU2-NEXT: bl __truncdfsf2
1908 ; EFPU2-NEXT: stw 3, 0(3)
1909 ; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
1910 ; EFPU2-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
1911 ; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
1912 ; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
1913 ; EFPU2-NEXT: evldd 26, 16(1) # 8-byte Folded Reload
1914 ; EFPU2-NEXT: lwz 0, 68(1)
1915 ; EFPU2-NEXT: addi 1, 1, 64
1916 ; EFPU2-NEXT: mtlr 0
1917 ; EFPU2-NEXT: blr
1918 entry:
1919 %0 = getelementptr %struct.a, %struct.a* %f, i32 0, i32 0
1920 %1 = load float, float* undef
1921 %conv = fpext float %1 to double
1922 %2 = load float, float* %0
1923 %g = fpext float %2 to double
1924 %3 = call i32 @foo(double %g)
1925 %h = call i32 @foo(double %conv)
1926 %n = sitofp i32 %3 to double
1927 %k = fmul double %g, %n
1928 %l = fptrunc double %k to float
1929 store float %l, float* undef
1930 ret void
1931 }
1932 attributes #0 = { nounwind }