| blob | a2e7176654f87cdfc43e7c909c17bef7d5aebc4b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le < %s | FileCheck %s
4 define i64 @test1(i64* %a, i64* %b) {
5 ; CHECK-LABEL: test1:
6 ; CHECK: # %bb.0: # %entry
7 ; CHECK-NEXT: mr 5, 3
8 ; CHECK-NEXT: ld 3, 0(3)
9 ; CHECK-NEXT: ld 4, 0(4)
10 ; CHECK-NEXT: mtvsrd 34, 3
11 ; CHECK-NEXT: add 3, 3, 4
12 ; CHECK-NEXT: mtvsrd 35, 4
13 ; CHECK-NEXT: vavgsb 2, 2, 3
14 ; CHECK-NEXT: stxsdx 34, 0, 5
15 ; CHECK-NEXT: blr
16 entry:
17 %lhs = load i64, i64* %a, align 8
18 %rhs = load i64, i64* %b, align 8
19 %sum = add i64 %lhs, %rhs
20 %lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
21 %rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
22 %lhc = bitcast <2 x i64> %lv to <16 x i8>
23 %rhc = bitcast <2 x i64> %rv to <16 x i8>
24 %add = call <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8> %lhc, <16 x i8> %rhc)
25 %cb = bitcast <16 x i8> %add to <2 x i64>
26 %fv = extractelement <2 x i64> %cb, i32 0
27 store i64 %fv, i64* %a, align 8
28 ret i64 %sum
29 }
31 define i64 @test2(i64* %a, i64* %b) {
32 ; CHECK-LABEL: test2:
33 ; CHECK: # %bb.0: # %entry
34 ; CHECK-NEXT: mr 5, 3
35 ; CHECK-NEXT: ld 3, 0(3)
36 ; CHECK-NEXT: ld 4, 0(4)
37 ; CHECK-NEXT: mtvsrd 34, 3
38 ; CHECK-NEXT: add 3, 3, 4
39 ; CHECK-NEXT: mtvsrd 35, 4
40 ; CHECK-NEXT: vadduhm 2, 2, 3
41 ; CHECK-NEXT: stxsdx 34, 0, 5
42 ; CHECK-NEXT: blr
43 entry:
44 %lhs = load i64, i64* %a, align 8
45 %rhs = load i64, i64* %b, align 8
46 %sum = add i64 %lhs, %rhs
47 %lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
48 %rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
49 %lhc = bitcast <2 x i64> %lv to <8 x i16>
50 %rhc = bitcast <2 x i64> %rv to <8 x i16>
51 %add = add <8 x i16> %lhc, %rhc
52 %cb = bitcast <8 x i16> %add to <2 x i64>
53 %fv = extractelement <2 x i64> %cb, i32 0
54 store i64 %fv, i64* %a, align 8
55 ret i64 %sum
56 }
58 ; Ensure that vec-ops with multiple uses aren't simplified.
59 define signext i16 @vecop_uses(i16* %addr) {
60 ; CHECK-LABEL: vecop_uses:
61 ; CHECK: # %bb.0: # %entry
62 ; CHECK-NEXT: li 4, 16
63 ; CHECK-NEXT: lxvd2x 1, 0, 3
64 ; CHECK-NEXT: lxvd2x 0, 3, 4
65 ; CHECK-NEXT: xxswapd 35, 1
66 ; CHECK-NEXT: xxswapd 34, 0
67 ; CHECK-NEXT: vminsh 2, 3, 2
68 ; CHECK-NEXT: xxswapd 35, 34
69 ; CHECK-NEXT: vminsh 2, 2, 3
70 ; CHECK-NEXT: xxspltw 35, 34, 2
71 ; CHECK-NEXT: vminsh 2, 2, 3
72 ; CHECK-NEXT: vsplth 3, 2, 6
73 ; CHECK-NEXT: vminsh 2, 2, 3
74 ; CHECK-NEXT: xxswapd 0, 34
75 ; CHECK-NEXT: mffprd 3, 0
76 ; CHECK-NEXT: clrldi 3, 3, 48
77 ; CHECK-NEXT: extsh 3, 3
78 ; CHECK-NEXT: blr
79 entry:
80 %0 = bitcast i16* %addr to <16 x i16>*
81 %1 = load <16 x i16>, <16 x i16>* %0, align 2
82 %2 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %1)
83 ret i16 %2
84 }
86 define signext i32 @vecop_uses2([4 x i32]* %a, [4 x i32]* %b, [4 x i32]* %c) {
87 ; CHECK-LABEL: vecop_uses2:
88 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: lxvd2x 0, 0, 3
90 ; CHECK-NEXT: lxvd2x 1, 0, 4
91 ; CHECK-NEXT: xxswapd 34, 0
92 ; CHECK-NEXT: xxswapd 35, 1
93 ; CHECK-NEXT: xxsldwi 0, 34, 34, 3
94 ; CHECK-NEXT: vmuluwm 2, 3, 2
95 ; CHECK-NEXT: mffprwz 3, 0
96 ; CHECK-NEXT: xxswapd 0, 34
97 ; CHECK-NEXT: extsw 3, 3
98 ; CHECK-NEXT: stxvd2x 0, 0, 5
99 ; CHECK-NEXT: blr
100 entry:
101 %0 = bitcast [4 x i32]* %a to <4 x i32>*
102 %1 = load <4 x i32>, <4 x i32>* %0, align 4
103 %2 = bitcast [4 x i32]* %b to <4 x i32>*
104 %3 = load <4 x i32>, <4 x i32>* %2, align 4
105 %4 = mul <4 x i32> %3, %1
106 %5 = bitcast [4 x i32]* %c to <4 x i32>*
107 store <4 x i32> %4, <4 x i32>* %5, align 4
108 %6 = extractelement <4 x i32> %1, i32 3
109 ret i32 %6
110 }
112 declare <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8>, <16 x i8>)
113 declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)