| blob | 9824d9e99fde06f50ede5bab2ac5080194d5bd6d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6 ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-BE
9 define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
10 ; CHECK-LABEL: test8x32:
11 ; CHECK: # %bb.0:
12 ; CHECK-NEXT: rldimi r3, r4, 32, 0
13 ; CHECK-NEXT: rldimi r5, r6, 32, 0
14 ; CHECK-NEXT: addis r11, r2, .LCPI0_0@toc@ha
15 ; CHECK-NEXT: rldimi r7, r8, 32, 0
16 ; CHECK-NEXT: rldimi r9, r10, 32, 0
17 ; CHECK-NEXT: mtfprd f0, r3
18 ; CHECK-NEXT: addi r3, r11, .LCPI0_0@toc@l
19 ; CHECK-NEXT: mtfprd f1, r5
20 ; CHECK-NEXT: lvx v4, 0, r3
21 ; CHECK-NEXT: mtfprd f2, r7
22 ; CHECK-NEXT: mtfprd f3, r9
23 ; CHECK-NEXT: xxmrghd v2, vs1, vs0
24 ; CHECK-NEXT: xxmrghd v3, vs3, vs2
25 ; CHECK-NEXT: vperm v2, v3, v2, v4
26 ; CHECK-NEXT: blr
27 ;
28 ; CHECK-BE-LABEL: test8x32:
29 ; CHECK-BE: # %bb.0:
30 ; CHECK-BE-NEXT: stw r10, -80(r1)
31 ; CHECK-BE-NEXT: stw r9, -96(r1)
32 ; CHECK-BE-NEXT: stw r8, -112(r1)
33 ; CHECK-BE-NEXT: stw r7, -128(r1)
34 ; CHECK-BE-NEXT: stw r6, -16(r1)
35 ; CHECK-BE-NEXT: stw r5, -32(r1)
36 ; CHECK-BE-NEXT: stw r4, -48(r1)
37 ; CHECK-BE-NEXT: stw r3, -64(r1)
38 ; CHECK-BE-NEXT: addi r3, r1, -80
39 ; CHECK-BE-NEXT: lxvw4x v2, 0, r3
40 ; CHECK-BE-NEXT: addi r3, r1, -96
41 ; CHECK-BE-NEXT: lxvw4x v3, 0, r3
42 ; CHECK-BE-NEXT: addi r3, r1, -112
43 ; CHECK-BE-NEXT: lxvw4x v4, 0, r3
44 ; CHECK-BE-NEXT: addi r3, r1, -128
45 ; CHECK-BE-NEXT: lxvw4x v5, 0, r3
46 ; CHECK-BE-NEXT: addi r3, r1, -16
47 ; CHECK-BE-NEXT: lxvw4x v0, 0, r3
48 ; CHECK-BE-NEXT: addi r3, r1, -32
49 ; CHECK-BE-NEXT: lxvw4x v1, 0, r3
50 ; CHECK-BE-NEXT: addi r3, r1, -48
51 ; CHECK-BE-NEXT: lxvw4x v6, 0, r3
52 ; CHECK-BE-NEXT: addi r3, r1, -64
53 ; CHECK-BE-NEXT: lxvw4x v7, 0, r3
54 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
55 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
56 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
57 ; CHECK-BE-NEXT: vmrghw v4, v1, v0
58 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
59 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
60 ; CHECK-BE-NEXT: lxvw4x v8, 0, r3
61 ; CHECK-BE-NEXT: vmrghw v5, v7, v6
62 ; CHECK-BE-NEXT: xxmrghd v3, v5, v4
63 ; CHECK-BE-NEXT: vperm v2, v3, v2, v8
64 ; CHECK-BE-NEXT: blr
65 %v10 = insertelement <8 x i32> undef, i32 %i1, i32 0
66 %v11 = insertelement <8 x i32> %v10, i32 %i2, i32 1
67 %v12 = insertelement <8 x i32> %v11, i32 %i3, i32 2
68 %v13 = insertelement <8 x i32> %v12, i32 %i4, i32 3
69 %v14 = insertelement <8 x i32> %v13, i32 %i5, i32 4
70 %v15 = insertelement <8 x i32> %v14, i32 %i6, i32 5
71 %v16 = insertelement <8 x i32> %v15, i32 %i7, i32 6
72 %v17 = insertelement <8 x i32> %v16, i32 %i8, i32 7
73 %v2 = trunc <8 x i32> %v17 to <8 x i8>
74 ret <8 x i8> %v2
75 }
77 define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) {
78 ; CHECK-LABEL: test4x64:
79 ; CHECK: # %bb.0:
80 ; CHECK-NEXT: addis r7, r2, .LCPI1_0@toc@ha
81 ; CHECK-NEXT: mtfprd f0, r5
82 ; CHECK-NEXT: mtfprd f1, r6
83 ; CHECK-NEXT: mtfprd f2, r3
84 ; CHECK-NEXT: addi r3, r7, .LCPI1_0@toc@l
85 ; CHECK-NEXT: mtfprd f3, r4
86 ; CHECK-NEXT: xxmrghd v2, vs1, vs0
87 ; CHECK-NEXT: lvx v4, 0, r3
88 ; CHECK-NEXT: xxmrghd v3, vs3, vs2
89 ; CHECK-NEXT: vperm v2, v2, v3, v4
90 ; CHECK-NEXT: blr
91 ;
92 ; CHECK-BE-LABEL: test4x64:
93 ; CHECK-BE: # %bb.0:
94 ; CHECK-BE-NEXT: std r6, -8(r1)
95 ; CHECK-BE-NEXT: std r5, -16(r1)
96 ; CHECK-BE-NEXT: std r4, -24(r1)
97 ; CHECK-BE-NEXT: std r3, -32(r1)
98 ; CHECK-BE-NEXT: addi r3, r1, -32
99 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
100 ; CHECK-BE-NEXT: addi r7, r1, -16
101 ; CHECK-BE-NEXT: lxvd2x v3, 0, r3
102 ; CHECK-BE-NEXT: addi r3, r4, .LCPI1_0@toc@l
103 ; CHECK-BE-NEXT: lxvd2x v2, 0, r7
104 ; CHECK-BE-NEXT: lxvw4x v4, 0, r3
105 ; CHECK-BE-NEXT: vperm v2, v3, v2, v4
106 ; CHECK-BE-NEXT: blr
107 %v10 = insertelement <4 x i64> undef, i64 %i1, i32 0
108 %v11 = insertelement <4 x i64> %v10, i64 %i2, i32 1
109 %v12 = insertelement <4 x i64> %v11, i64 %i3, i32 2
110 %v13 = insertelement <4 x i64> %v12, i64 %i4, i32 3
111 %v2 = trunc <4 x i64> %v13 to <4 x i16>
112 ret <4 x i16> %v2
113 }
115 define dso_local <8 x i16> @test8x24(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
116 ; CHECK-LABEL: test8x24:
117 ; CHECK: # %bb.0:
118 ; CHECK-NEXT: mtvsrd v2, r3
119 ; CHECK-NEXT: mtvsrd v3, r4
120 ; CHECK-NEXT: mtvsrd v4, r5
121 ; CHECK-NEXT: mtvsrd v5, r6
122 ; CHECK-NEXT: mtvsrd v0, r7
123 ; CHECK-NEXT: mtvsrd v1, r8
124 ; CHECK-NEXT: vmrghh v2, v3, v2
125 ; CHECK-NEXT: mtvsrd v3, r9
126 ; CHECK-NEXT: vmrghh v4, v5, v4
127 ; CHECK-NEXT: mtvsrd v5, r10
128 ; CHECK-NEXT: vmrghh v0, v1, v0
129 ; CHECK-NEXT: vmrghh v3, v5, v3
130 ; CHECK-NEXT: vmrglw v2, v4, v2
131 ; CHECK-NEXT: vmrglw v3, v3, v0
132 ; CHECK-NEXT: xxmrgld v2, v3, v2
133 ; CHECK-NEXT: blr
134 ;
135 ; CHECK-BE-LABEL: test8x24:
136 ; CHECK-BE: # %bb.0:
137 ; CHECK-BE-NEXT: sth r10, -16(r1)
138 ; CHECK-BE-NEXT: sth r9, -32(r1)
139 ; CHECK-BE-NEXT: sth r8, -48(r1)
140 ; CHECK-BE-NEXT: sth r7, -64(r1)
141 ; CHECK-BE-NEXT: sth r6, -80(r1)
142 ; CHECK-BE-NEXT: sth r5, -96(r1)
143 ; CHECK-BE-NEXT: sth r4, -112(r1)
144 ; CHECK-BE-NEXT: sth r3, -128(r1)
145 ; CHECK-BE-NEXT: addi r3, r1, -16
146 ; CHECK-BE-NEXT: lxvw4x v2, 0, r3
147 ; CHECK-BE-NEXT: addi r3, r1, -32
148 ; CHECK-BE-NEXT: lxvw4x v3, 0, r3
149 ; CHECK-BE-NEXT: addi r3, r1, -48
150 ; CHECK-BE-NEXT: lxvw4x v4, 0, r3
151 ; CHECK-BE-NEXT: addi r3, r1, -64
152 ; CHECK-BE-NEXT: lxvw4x v5, 0, r3
153 ; CHECK-BE-NEXT: addi r3, r1, -80
154 ; CHECK-BE-NEXT: lxvw4x v0, 0, r3
155 ; CHECK-BE-NEXT: addi r3, r1, -96
156 ; CHECK-BE-NEXT: lxvw4x v1, 0, r3
157 ; CHECK-BE-NEXT: addi r3, r1, -112
158 ; CHECK-BE-NEXT: lxvw4x v6, 0, r3
159 ; CHECK-BE-NEXT: addi r3, r1, -128
160 ; CHECK-BE-NEXT: lxvw4x v7, 0, r3
161 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
162 ; CHECK-BE-NEXT: vmrghh v3, v5, v4
163 ; CHECK-BE-NEXT: vmrghh v4, v1, v0
164 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
165 ; CHECK-BE-NEXT: vmrghh v5, v7, v6
166 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
167 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
168 ; CHECK-BE-NEXT: blr
169 %i11 = trunc i32 %i1 to i24
170 %i21 = trunc i32 %i2 to i24
171 %i31 = trunc i32 %i3 to i24
172 %i41 = trunc i32 %i4 to i24
173 %i51 = trunc i32 %i5 to i24
174 %i61 = trunc i32 %i6 to i24
175 %i71 = trunc i32 %i7 to i24
176 %i81 = trunc i32 %i8 to i24
177 %v10 = insertelement <8 x i24> undef, i24 %i11, i32 0
178 %v11 = insertelement <8 x i24> %v10, i24 %i21, i32 1
179 %v12 = insertelement <8 x i24> %v11, i24 %i31, i32 2
180 %v13 = insertelement <8 x i24> %v12, i24 %i41, i32 3
181 %v14 = insertelement <8 x i24> %v13, i24 %i51, i32 4
182 %v15 = insertelement <8 x i24> %v14, i24 %i61, i32 5
183 %v16 = insertelement <8 x i24> %v15, i24 %i71, i32 6
184 %v17 = insertelement <8 x i24> %v16, i24 %i81, i32 7
185 %v2 = trunc <8 x i24> %v17 to <8 x i16>
186 ret <8 x i16> %v2
187 }