| blob | 9493e571a8cc34bf716bdf0188b1554712ab3631 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: mtfprd f0, r3
16 ; CHECK-P8-NEXT: mffprd r3, f0
17 ; CHECK-P8-NEXT: clrldi r4, r3, 56
18 ; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
19 ; CHECK-P8-NEXT: clrlwi r4, r4, 24
20 ; CHECK-P8-NEXT: clrlwi r3, r3, 24
21 ; CHECK-P8-NEXT: mtfprwz f0, r4
22 ; CHECK-P8-NEXT: mtfprwz f1, r3
23 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
24 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
25 ; CHECK-P8-NEXT: xscvdpspn v2, f0
26 ; CHECK-P8-NEXT: xscvdpspn v3, f1
27 ; CHECK-P8-NEXT: vmrghw v2, v3, v2
28 ; CHECK-P8-NEXT: xxswapd vs0, v2
29 ; CHECK-P8-NEXT: mffprd r3, f0
30 ; CHECK-P8-NEXT: blr
31 ;
32 ; CHECK-P9-LABEL: test2elt:
33 ; CHECK-P9: # %bb.0: # %entry
34 ; CHECK-P9-NEXT: mtvsrws v2, r3
35 ; CHECK-P9-NEXT: vextractub v3, v2, 15
36 ; CHECK-P9-NEXT: vextractub v2, v2, 14
37 ; CHECK-P9-NEXT: xscvuxdsp f0, v3
38 ; CHECK-P9-NEXT: xscvdpspn v3, f0
39 ; CHECK-P9-NEXT: xscvuxdsp f0, v2
40 ; CHECK-P9-NEXT: xscvdpspn v2, f0
41 ; CHECK-P9-NEXT: vmrghw v2, v2, v3
42 ; CHECK-P9-NEXT: mfvsrld r3, v2
43 ; CHECK-P9-NEXT: blr
44 ;
45 ; CHECK-BE-LABEL: test2elt:
46 ; CHECK-BE: # %bb.0: # %entry
47 ; CHECK-BE-NEXT: mtvsrws v2, r3
48 ; CHECK-BE-NEXT: vextractub v3, v2, 2
49 ; CHECK-BE-NEXT: vextractub v2, v2, 0
50 ; CHECK-BE-NEXT: xscvuxdsp f0, v3
51 ; CHECK-BE-NEXT: xscvdpspn v3, f0
52 ; CHECK-BE-NEXT: xscvuxdsp f0, v2
53 ; CHECK-BE-NEXT: xscvdpspn v2, f0
54 ; CHECK-BE-NEXT: vmrgow v2, v2, v3
55 ; CHECK-BE-NEXT: mfvsrd r3, v2
56 ; CHECK-BE-NEXT: blr
57 entry:
58 %0 = bitcast i16 %a.coerce to <2 x i8>
59 %1 = uitofp <2 x i8> %0 to <2 x float>
60 %2 = bitcast <2 x float> %1 to i64
61 ret i64 %2
62 }
64 define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 {
65 ; CHECK-P8-LABEL: test4elt:
66 ; CHECK-P8: # %bb.0: # %entry
67 ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
68 ; CHECK-P8-NEXT: mtvsrwz v2, r3
69 ; CHECK-P8-NEXT: addi r4, r4, .LCPI1_0@toc@l
70 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
71 ; CHECK-P8-NEXT: lvx v3, 0, r4
72 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
73 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
74 ; CHECK-P8-NEXT: blr
75 ;
76 ; CHECK-P9-LABEL: test4elt:
77 ; CHECK-P9: # %bb.0: # %entry
78 ; CHECK-P9-NEXT: mtvsrwz v2, r3
79 ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
80 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
81 ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
82 ; CHECK-P9-NEXT: lxv v3, 0(r3)
83 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
84 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
85 ; CHECK-P9-NEXT: blr
86 ;
87 ; CHECK-BE-LABEL: test4elt:
88 ; CHECK-BE: # %bb.0: # %entry
89 ; CHECK-BE-NEXT: mtvsrwz v2, r3
90 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
91 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
92 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
93 ; CHECK-BE-NEXT: lxv v3, 0(r3)
94 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
95 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
96 ; CHECK-BE-NEXT: blr
97 entry:
98 %0 = bitcast i32 %a.coerce to <4 x i8>
99 %1 = uitofp <4 x i8> %0 to <4 x float>
100 ret <4 x float> %1
101 }
103 define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
104 ; CHECK-P8-LABEL: test8elt:
105 ; CHECK-P8: # %bb.0: # %entry
106 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
107 ; CHECK-P8-NEXT: addis r6, r2, .LCPI2_1@toc@ha
108 ; CHECK-P8-NEXT: mtvsrd v2, r4
109 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
110 ; CHECK-P8-NEXT: addi r4, r6, .LCPI2_1@toc@l
111 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
112 ; CHECK-P8-NEXT: lvx v3, 0, r5
113 ; CHECK-P8-NEXT: lvx v5, 0, r4
114 ; CHECK-P8-NEXT: li r4, 16
115 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
116 ; CHECK-P8-NEXT: vperm v2, v4, v2, v5
117 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
118 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
119 ; CHECK-P8-NEXT: stvx v3, 0, r3
120 ; CHECK-P8-NEXT: stvx v2, r3, r4
121 ; CHECK-P8-NEXT: blr
122 ;
123 ; CHECK-P9-LABEL: test8elt:
124 ; CHECK-P9: # %bb.0: # %entry
125 ; CHECK-P9-NEXT: mtvsrd v2, r4
126 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
127 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
128 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
129 ; CHECK-P9-NEXT: lxv v3, 0(r4)
130 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
131 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
132 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
133 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
134 ; CHECK-P9-NEXT: lxv v3, 0(r4)
135 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
136 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
137 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
138 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
139 ; CHECK-P9-NEXT: blr
140 ;
141 ; CHECK-BE-LABEL: test8elt:
142 ; CHECK-BE: # %bb.0: # %entry
143 ; CHECK-BE-NEXT: mtvsrd v2, r4
144 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
145 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
146 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
147 ; CHECK-BE-NEXT: lxv v3, 0(r4)
148 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
149 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
150 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
151 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
152 ; CHECK-BE-NEXT: lxv v3, 0(r4)
153 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
154 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
155 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
156 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
157 ; CHECK-BE-NEXT: blr
158 entry:
159 %0 = bitcast i64 %a.coerce to <8 x i8>
160 %1 = uitofp <8 x i8> %0 to <8 x float>
161 store <8 x float> %1, <8 x float>* %agg.result, align 32
162 ret void
163 }
165 define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
166 ; CHECK-P8-LABEL: test16elt:
167 ; CHECK-P8: # %bb.0: # %entry
168 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha
169 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_2@toc@ha
170 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
171 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l
172 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_2@toc@l
173 ; CHECK-P8-NEXT: lvx v3, 0, r4
174 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha
175 ; CHECK-P8-NEXT: lvx v5, 0, r5
176 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha
177 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l
178 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l
179 ; CHECK-P8-NEXT: lvx v0, 0, r4
180 ; CHECK-P8-NEXT: lvx v1, 0, r5
181 ; CHECK-P8-NEXT: li r4, 48
182 ; CHECK-P8-NEXT: li r5, 32
183 ; CHECK-P8-NEXT: vperm v5, v4, v2, v5
184 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
185 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0
186 ; CHECK-P8-NEXT: vperm v2, v4, v2, v1
187 ; CHECK-P8-NEXT: xvcvuxwsp v4, v5
188 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
189 ; CHECK-P8-NEXT: xvcvuxwsp v5, v0
190 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
191 ; CHECK-P8-NEXT: stvx v4, r3, r5
192 ; CHECK-P8-NEXT: stvx v3, 0, r3
193 ; CHECK-P8-NEXT: stvx v5, r3, r4
194 ; CHECK-P8-NEXT: li r4, 16
195 ; CHECK-P8-NEXT: stvx v2, r3, r4
196 ; CHECK-P8-NEXT: blr
197 ;
198 ; CHECK-P9-LABEL: test16elt:
199 ; CHECK-P9: # %bb.0: # %entry
200 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
201 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
202 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
203 ; CHECK-P9-NEXT: lxv v3, 0(r4)
204 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
205 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
206 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
207 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
208 ; CHECK-P9-NEXT: lxv v3, 0(r4)
209 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
210 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
211 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
212 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
213 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
214 ; CHECK-P9-NEXT: lxv v3, 0(r4)
215 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
216 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
217 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
218 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
219 ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
220 ; CHECK-P9-NEXT: lxv v3, 0(r4)
221 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
222 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
223 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
224 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
225 ; CHECK-P9-NEXT: blr
226 ;
227 ; CHECK-BE-LABEL: test16elt:
228 ; CHECK-BE: # %bb.0: # %entry
229 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
230 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
231 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
232 ; CHECK-BE-NEXT: lxv v3, 0(r4)
233 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
234 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
235 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
236 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
237 ; CHECK-BE-NEXT: lxv v3, 0(r4)
238 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
239 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
240 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
241 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
242 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
243 ; CHECK-BE-NEXT: lxv v3, 0(r4)
244 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
245 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
246 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
247 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
248 ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3
249 ; CHECK-BE-NEXT: lxv v3, 0(r4)
250 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
251 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
252 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2
253 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
254 ; CHECK-BE-NEXT: blr
255 entry:
256 %0 = uitofp <16 x i8> %a to <16 x float>
257 store <16 x float> %0, <16 x float>* %agg.result, align 64
258 ret void
259 }
261 define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
262 ; CHECK-P8-LABEL: test2elt_signed:
263 ; CHECK-P8: # %bb.0: # %entry
264 ; CHECK-P8-NEXT: mtfprd f0, r3
265 ; CHECK-P8-NEXT: mffprd r3, f0
266 ; CHECK-P8-NEXT: clrldi r4, r3, 56
267 ; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
268 ; CHECK-P8-NEXT: extsb r4, r4
269 ; CHECK-P8-NEXT: extsb r3, r3
270 ; CHECK-P8-NEXT: mtfprwa f0, r4
271 ; CHECK-P8-NEXT: mtfprwa f1, r3
272 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
273 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
274 ; CHECK-P8-NEXT: xscvdpspn v2, f0
275 ; CHECK-P8-NEXT: xscvdpspn v3, f1
276 ; CHECK-P8-NEXT: vmrghw v2, v3, v2
277 ; CHECK-P8-NEXT: xxswapd vs0, v2
278 ; CHECK-P8-NEXT: mffprd r3, f0
279 ; CHECK-P8-NEXT: blr
280 ;
281 ; CHECK-P9-LABEL: test2elt_signed:
282 ; CHECK-P9: # %bb.0: # %entry
283 ; CHECK-P9-NEXT: mtvsrws v2, r3
284 ; CHECK-P9-NEXT: vextractub v3, v2, 15
285 ; CHECK-P9-NEXT: vextractub v2, v2, 14
286 ; CHECK-P9-NEXT: vextsh2d v3, v3
287 ; CHECK-P9-NEXT: vextsh2d v2, v2
288 ; CHECK-P9-NEXT: xscvsxdsp f0, v3
289 ; CHECK-P9-NEXT: xscvdpspn v3, f0
290 ; CHECK-P9-NEXT: xscvsxdsp f0, v2
291 ; CHECK-P9-NEXT: xscvdpspn v2, f0
292 ; CHECK-P9-NEXT: vmrghw v2, v2, v3
293 ; CHECK-P9-NEXT: mfvsrld r3, v2
294 ; CHECK-P9-NEXT: blr
295 ;
296 ; CHECK-BE-LABEL: test2elt_signed:
297 ; CHECK-BE: # %bb.0: # %entry
298 ; CHECK-BE-NEXT: mtvsrws v2, r3
299 ; CHECK-BE-NEXT: vextractub v3, v2, 2
300 ; CHECK-BE-NEXT: vextractub v2, v2, 0
301 ; CHECK-BE-NEXT: vextsh2d v3, v3
302 ; CHECK-BE-NEXT: vextsh2d v2, v2
303 ; CHECK-BE-NEXT: xscvsxdsp f0, v3
304 ; CHECK-BE-NEXT: xscvdpspn v3, f0
305 ; CHECK-BE-NEXT: xscvsxdsp f0, v2
306 ; CHECK-BE-NEXT: xscvdpspn v2, f0
307 ; CHECK-BE-NEXT: vmrgow v2, v2, v3
308 ; CHECK-BE-NEXT: mfvsrd r3, v2
309 ; CHECK-BE-NEXT: blr
310 entry:
311 %0 = bitcast i16 %a.coerce to <2 x i8>
312 %1 = sitofp <2 x i8> %0 to <2 x float>
313 %2 = bitcast <2 x float> %1 to i64
314 ret i64 %2
315 }
317 define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 {
318 ; CHECK-P8-LABEL: test4elt_signed:
319 ; CHECK-P8: # %bb.0: # %entry
320 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha
321 ; CHECK-P8-NEXT: mtvsrwz v3, r3
322 ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_0@toc@l
323 ; CHECK-P8-NEXT: lvx v2, 0, r4
324 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
325 ; CHECK-P8-NEXT: vspltisw v3, 12
326 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
327 ; CHECK-P8-NEXT: vslw v2, v2, v3
328 ; CHECK-P8-NEXT: vsraw v2, v2, v3
329 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
330 ; CHECK-P8-NEXT: blr
331 ;
332 ; CHECK-P9-LABEL: test4elt_signed:
333 ; CHECK-P9: # %bb.0: # %entry
334 ; CHECK-P9-NEXT: mtvsrwz v2, r3
335 ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
336 ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
337 ; CHECK-P9-NEXT: lxv v3, 0(r3)
338 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
339 ; CHECK-P9-NEXT: vextsb2w v2, v2
340 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2
341 ; CHECK-P9-NEXT: blr
342 ;
343 ; CHECK-BE-LABEL: test4elt_signed:
344 ; CHECK-BE: # %bb.0: # %entry
345 ; CHECK-BE-NEXT: mtvsrwz v2, r3
346 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
347 ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
348 ; CHECK-BE-NEXT: lxv v3, 0(r3)
349 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
350 ; CHECK-BE-NEXT: vextsb2w v2, v2
351 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2
352 ; CHECK-BE-NEXT: blr
353 entry:
354 %0 = bitcast i32 %a.coerce to <4 x i8>
355 %1 = sitofp <4 x i8> %0 to <4 x float>
356 ret <4 x float> %1
357 }
359 define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
360 ; CHECK-P8-LABEL: test8elt_signed:
361 ; CHECK-P8: # %bb.0: # %entry
362 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
363 ; CHECK-P8-NEXT: addis r6, r2, .LCPI6_1@toc@ha
364 ; CHECK-P8-NEXT: mtvsrd v3, r4
365 ; CHECK-P8-NEXT: vspltisw v5, 12
366 ; CHECK-P8-NEXT: li r4, 16
367 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
368 ; CHECK-P8-NEXT: lvx v2, 0, r5
369 ; CHECK-P8-NEXT: addi r5, r6, .LCPI6_1@toc@l
370 ; CHECK-P8-NEXT: lvx v4, 0, r5
371 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
372 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
373 ; CHECK-P8-NEXT: vadduwm v4, v5, v5
374 ; CHECK-P8-NEXT: vslw v2, v2, v4
375 ; CHECK-P8-NEXT: vslw v3, v3, v4
376 ; CHECK-P8-NEXT: vsraw v2, v2, v4
377 ; CHECK-P8-NEXT: vsraw v3, v3, v4
378 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
379 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3
380 ; CHECK-P8-NEXT: stvx v2, 0, r3
381 ; CHECK-P8-NEXT: stvx v3, r3, r4
382 ; CHECK-P8-NEXT: blr
383 ;
384 ; CHECK-P9-LABEL: test8elt_signed:
385 ; CHECK-P9: # %bb.0: # %entry
386 ; CHECK-P9-NEXT: mtvsrd v2, r4
387 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
388 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
389 ; CHECK-P9-NEXT: lxv v3, 0(r4)
390 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
391 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
392 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
393 ; CHECK-P9-NEXT: vextsb2w v3, v3
394 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
395 ; CHECK-P9-NEXT: lxv v3, 0(r4)
396 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
397 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
398 ; CHECK-P9-NEXT: vextsb2w v2, v2
399 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
400 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
401 ; CHECK-P9-NEXT: blr
402 ;
403 ; CHECK-BE-LABEL: test8elt_signed:
404 ; CHECK-BE: # %bb.0: # %entry
405 ; CHECK-BE-NEXT: mtvsrd v2, r4
406 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
407 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
408 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
409 ; CHECK-BE-NEXT: lxv v4, 0(r4)
410 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
411 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
412 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
413 ; CHECK-BE-NEXT: vextsb2w v3, v3
414 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
415 ; CHECK-BE-NEXT: lxv v3, 0(r4)
416 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
417 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
418 ; CHECK-BE-NEXT: vextsb2w v2, v2
419 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
420 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
421 ; CHECK-BE-NEXT: blr
422 entry:
423 %0 = bitcast i64 %a.coerce to <8 x i8>
424 %1 = sitofp <8 x i8> %0 to <8 x float>
425 store <8 x float> %1, <8 x float>* %agg.result, align 32
426 ret void
427 }
429 define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 {
430 ; CHECK-P8-LABEL: test16elt_signed:
431 ; CHECK-P8: # %bb.0: # %entry
432 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha
433 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha
434 ; CHECK-P8-NEXT: vspltisw v1, 12
435 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l
436 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l
437 ; CHECK-P8-NEXT: lvx v3, 0, r4
438 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha
439 ; CHECK-P8-NEXT: lvx v4, 0, r5
440 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha
441 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l
442 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l
443 ; CHECK-P8-NEXT: lvx v5, 0, r4
444 ; CHECK-P8-NEXT: lvx v0, 0, r5
445 ; CHECK-P8-NEXT: li r4, 48
446 ; CHECK-P8-NEXT: li r5, 32
447 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
448 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
449 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
450 ; CHECK-P8-NEXT: vperm v2, v2, v2, v0
451 ; CHECK-P8-NEXT: vadduwm v0, v1, v1
452 ; CHECK-P8-NEXT: vslw v3, v3, v0
453 ; CHECK-P8-NEXT: vslw v4, v4, v0
454 ; CHECK-P8-NEXT: vslw v5, v5, v0
455 ; CHECK-P8-NEXT: vslw v2, v2, v0
456 ; CHECK-P8-NEXT: vsraw v3, v3, v0
457 ; CHECK-P8-NEXT: vsraw v4, v4, v0
458 ; CHECK-P8-NEXT: vsraw v5, v5, v0
459 ; CHECK-P8-NEXT: vsraw v2, v2, v0
460 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3
461 ; CHECK-P8-NEXT: xvcvsxwsp v4, v4
462 ; CHECK-P8-NEXT: xvcvsxwsp v5, v5
463 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
464 ; CHECK-P8-NEXT: stvx v3, 0, r3
465 ; CHECK-P8-NEXT: stvx v4, r3, r5
466 ; CHECK-P8-NEXT: stvx v5, r3, r4
467 ; CHECK-P8-NEXT: li r4, 16
468 ; CHECK-P8-NEXT: stvx v2, r3, r4
469 ; CHECK-P8-NEXT: blr
470 ;
471 ; CHECK-P9-LABEL: test16elt_signed:
472 ; CHECK-P9: # %bb.0: # %entry
473 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
474 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
475 ; CHECK-P9-NEXT: lxv v3, 0(r4)
476 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
477 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
478 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
479 ; CHECK-P9-NEXT: vextsb2w v3, v3
480 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
481 ; CHECK-P9-NEXT: lxv v3, 0(r4)
482 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
483 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
484 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
485 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
486 ; CHECK-P9-NEXT: vextsb2w v3, v3
487 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
488 ; CHECK-P9-NEXT: lxv v3, 0(r4)
489 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
490 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
491 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
492 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
493 ; CHECK-P9-NEXT: vextsb2w v3, v3
494 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3
495 ; CHECK-P9-NEXT: lxv v3, 0(r4)
496 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
497 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
498 ; CHECK-P9-NEXT: vextsb2w v2, v2
499 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
500 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
501 ; CHECK-P9-NEXT: blr
502 ;
503 ; CHECK-BE-LABEL: test16elt_signed:
504 ; CHECK-BE: # %bb.0: # %entry
505 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
506 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
507 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
508 ; CHECK-BE-NEXT: lxv v3, 0(r4)
509 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
510 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
511 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
512 ; CHECK-BE-NEXT: vextsb2w v3, v3
513 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
514 ; CHECK-BE-NEXT: lxv v3, 0(r4)
515 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
516 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
517 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
518 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
519 ; CHECK-BE-NEXT: vextsb2w v3, v3
520 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v3
521 ; CHECK-BE-NEXT: lxv v3, 0(r4)
522 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
523 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
524 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
525 ; CHECK-BE-NEXT: stxv vs1, 48(r3)
526 ; CHECK-BE-NEXT: vextsb2w v3, v3
527 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
528 ; CHECK-BE-NEXT: lxv v3, 0(r4)
529 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
530 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
531 ; CHECK-BE-NEXT: vextsb2w v2, v2
532 ; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
533 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
534 ; CHECK-BE-NEXT: blr
535 entry:
536 %0 = sitofp <16 x i8> %a to <16 x float>
537 store <16 x float> %0, <16 x float>* %agg.result, align 64
538 ret void
539 }