| blob | a62f006eaeb1227697b463f0bd77bc9a14423dd3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
3 ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
4 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
5 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
6 ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
7 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
8 ; RUN: -check-prefix=CHECK-REG %s
9 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
10 ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 \
11 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
12 ; RUN: -check-prefix=CHECK-FISL %s
13 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \
14 ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \
15 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
16 ; RUN: -check-prefix=CHECK-LE %s
18 define double @test1(double %a, double %b) {
19 ; CHECK-LABEL: test1:
20 ; CHECK: # %bb.0: # %entry
21 ; CHECK-NEXT: xsmuldp f1, f1, f2
22 ; CHECK-NEXT: blr
23 ;
24 ; CHECK-REG-LABEL: test1:
25 ; CHECK-REG: # %bb.0: # %entry
26 ; CHECK-REG-NEXT: xsmuldp f1, f1, f2
27 ; CHECK-REG-NEXT: blr
28 ;
29 ; CHECK-FISL-LABEL: test1:
30 ; CHECK-FISL: # %bb.0: # %entry
31 ; CHECK-FISL-NEXT: xsmuldp f1, f1, f2
32 ; CHECK-FISL-NEXT: blr
33 ;
34 ; CHECK-LE-LABEL: test1:
35 ; CHECK-LE: # %bb.0: # %entry
36 ; CHECK-LE-NEXT: xsmuldp f1, f1, f2
37 ; CHECK-LE-NEXT: blr
38 entry:
39 %v = fmul double %a, %b
40 ret double %v
43 }
45 define double @test2(double %a, double %b) {
46 ; CHECK-LABEL: test2:
47 ; CHECK: # %bb.0: # %entry
48 ; CHECK-NEXT: xsdivdp f1, f1, f2
49 ; CHECK-NEXT: blr
50 ;
51 ; CHECK-REG-LABEL: test2:
52 ; CHECK-REG: # %bb.0: # %entry
53 ; CHECK-REG-NEXT: xsdivdp f1, f1, f2
54 ; CHECK-REG-NEXT: blr
55 ;
56 ; CHECK-FISL-LABEL: test2:
57 ; CHECK-FISL: # %bb.0: # %entry
58 ; CHECK-FISL-NEXT: xsdivdp f1, f1, f2
59 ; CHECK-FISL-NEXT: blr
60 ;
61 ; CHECK-LE-LABEL: test2:
62 ; CHECK-LE: # %bb.0: # %entry
63 ; CHECK-LE-NEXT: xsdivdp f1, f1, f2
64 ; CHECK-LE-NEXT: blr
65 entry:
66 %v = fdiv double %a, %b
67 ret double %v
70 }
72 define double @test3(double %a, double %b) {
73 ; CHECK-LABEL: test3:
74 ; CHECK: # %bb.0: # %entry
75 ; CHECK-NEXT: xsadddp f1, f1, f2
76 ; CHECK-NEXT: blr
77 ;
78 ; CHECK-REG-LABEL: test3:
79 ; CHECK-REG: # %bb.0: # %entry
80 ; CHECK-REG-NEXT: xsadddp f1, f1, f2
81 ; CHECK-REG-NEXT: blr
82 ;
83 ; CHECK-FISL-LABEL: test3:
84 ; CHECK-FISL: # %bb.0: # %entry
85 ; CHECK-FISL-NEXT: xsadddp f1, f1, f2
86 ; CHECK-FISL-NEXT: blr
87 ;
88 ; CHECK-LE-LABEL: test3:
89 ; CHECK-LE: # %bb.0: # %entry
90 ; CHECK-LE-NEXT: xsadddp f1, f1, f2
91 ; CHECK-LE-NEXT: blr
92 entry:
93 %v = fadd double %a, %b
94 ret double %v
97 }
99 define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
100 ; CHECK-LABEL: test4:
101 ; CHECK: # %bb.0: # %entry
102 ; CHECK-NEXT: xvadddp v2, v2, v3
103 ; CHECK-NEXT: blr
104 ;
105 ; CHECK-REG-LABEL: test4:
106 ; CHECK-REG: # %bb.0: # %entry
107 ; CHECK-REG-NEXT: xvadddp v2, v2, v3
108 ; CHECK-REG-NEXT: blr
109 ;
110 ; CHECK-FISL-LABEL: test4:
111 ; CHECK-FISL: # %bb.0: # %entry
112 ; CHECK-FISL-NEXT: xvadddp v2, v2, v3
113 ; CHECK-FISL-NEXT: blr
114 ;
115 ; CHECK-LE-LABEL: test4:
116 ; CHECK-LE: # %bb.0: # %entry
117 ; CHECK-LE-NEXT: xvadddp v2, v2, v3
118 ; CHECK-LE-NEXT: blr
119 entry:
120 %v = fadd <2 x double> %a, %b
121 ret <2 x double> %v
124 }
126 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
127 ; CHECK-LABEL: test5:
128 ; CHECK: # %bb.0: # %entry
129 ; CHECK-NEXT: xxlxor v2, v2, v3
130 ; CHECK-NEXT: blr
131 ;
132 ; CHECK-REG-LABEL: test5:
133 ; CHECK-REG: # %bb.0: # %entry
134 ; CHECK-REG-NEXT: xxlxor v2, v2, v3
135 ; CHECK-REG-NEXT: blr
136 ;
137 ; CHECK-FISL-LABEL: test5:
138 ; CHECK-FISL: # %bb.0: # %entry
139 ; CHECK-FISL-NEXT: xxlxor v2, v2, v3
140 ; CHECK-FISL-NEXT: blr
141 ;
142 ; CHECK-LE-LABEL: test5:
143 ; CHECK-LE: # %bb.0: # %entry
144 ; CHECK-LE-NEXT: xxlxor v2, v2, v3
145 ; CHECK-LE-NEXT: blr
146 entry:
147 %v = xor <4 x i32> %a, %b
148 ret <4 x i32> %v
152 }
154 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
155 ; CHECK-LABEL: test6:
156 ; CHECK: # %bb.0: # %entry
157 ; CHECK-NEXT: xxlxor v2, v2, v3
158 ; CHECK-NEXT: blr
159 ;
160 ; CHECK-REG-LABEL: test6:
161 ; CHECK-REG: # %bb.0: # %entry
162 ; CHECK-REG-NEXT: xxlxor v2, v2, v3
163 ; CHECK-REG-NEXT: blr
164 ;
165 ; CHECK-FISL-LABEL: test6:
166 ; CHECK-FISL: # %bb.0: # %entry
167 ; CHECK-FISL-NEXT: xxlxor v2, v2, v3
168 ; CHECK-FISL-NEXT: blr
169 ;
170 ; CHECK-LE-LABEL: test6:
171 ; CHECK-LE: # %bb.0: # %entry
172 ; CHECK-LE-NEXT: xxlxor v2, v2, v3
173 ; CHECK-LE-NEXT: blr
174 entry:
175 %v = xor <8 x i16> %a, %b
176 ret <8 x i16> %v
180 }
182 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
183 ; CHECK-LABEL: test7:
184 ; CHECK: # %bb.0: # %entry
185 ; CHECK-NEXT: xxlxor v2, v2, v3
186 ; CHECK-NEXT: blr
187 ;
188 ; CHECK-REG-LABEL: test7:
189 ; CHECK-REG: # %bb.0: # %entry
190 ; CHECK-REG-NEXT: xxlxor v2, v2, v3
191 ; CHECK-REG-NEXT: blr
192 ;
193 ; CHECK-FISL-LABEL: test7:
194 ; CHECK-FISL: # %bb.0: # %entry
195 ; CHECK-FISL-NEXT: xxlxor v2, v2, v3
196 ; CHECK-FISL-NEXT: blr
197 ;
198 ; CHECK-LE-LABEL: test7:
199 ; CHECK-LE: # %bb.0: # %entry
200 ; CHECK-LE-NEXT: xxlxor v2, v2, v3
201 ; CHECK-LE-NEXT: blr
202 entry:
203 %v = xor <16 x i8> %a, %b
204 ret <16 x i8> %v
208 }
210 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
211 ; CHECK-LABEL: test8:
212 ; CHECK: # %bb.0: # %entry
213 ; CHECK-NEXT: xxlor v2, v2, v3
214 ; CHECK-NEXT: blr
215 ;
216 ; CHECK-REG-LABEL: test8:
217 ; CHECK-REG: # %bb.0: # %entry
218 ; CHECK-REG-NEXT: xxlor v2, v2, v3
219 ; CHECK-REG-NEXT: blr
220 ;
221 ; CHECK-FISL-LABEL: test8:
222 ; CHECK-FISL: # %bb.0: # %entry
223 ; CHECK-FISL-NEXT: xxlor v2, v2, v3
224 ; CHECK-FISL-NEXT: blr
225 ;
226 ; CHECK-LE-LABEL: test8:
227 ; CHECK-LE: # %bb.0: # %entry
228 ; CHECK-LE-NEXT: xxlor v2, v2, v3
229 ; CHECK-LE-NEXT: blr
230 entry:
231 %v = or <4 x i32> %a, %b
232 ret <4 x i32> %v
236 }
238 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
239 ; CHECK-LABEL: test9:
240 ; CHECK: # %bb.0: # %entry
241 ; CHECK-NEXT: xxlor v2, v2, v3
242 ; CHECK-NEXT: blr
243 ;
244 ; CHECK-REG-LABEL: test9:
245 ; CHECK-REG: # %bb.0: # %entry
246 ; CHECK-REG-NEXT: xxlor v2, v2, v3
247 ; CHECK-REG-NEXT: blr
248 ;
249 ; CHECK-FISL-LABEL: test9:
250 ; CHECK-FISL: # %bb.0: # %entry
251 ; CHECK-FISL-NEXT: xxlor v2, v2, v3
252 ; CHECK-FISL-NEXT: blr
253 ;
254 ; CHECK-LE-LABEL: test9:
255 ; CHECK-LE: # %bb.0: # %entry
256 ; CHECK-LE-NEXT: xxlor v2, v2, v3
257 ; CHECK-LE-NEXT: blr
258 entry:
259 %v = or <8 x i16> %a, %b
260 ret <8 x i16> %v
264 }
266 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
267 ; CHECK-LABEL: test10:
268 ; CHECK: # %bb.0: # %entry
269 ; CHECK-NEXT: xxlor v2, v2, v3
270 ; CHECK-NEXT: blr
271 ;
272 ; CHECK-REG-LABEL: test10:
273 ; CHECK-REG: # %bb.0: # %entry
274 ; CHECK-REG-NEXT: xxlor v2, v2, v3
275 ; CHECK-REG-NEXT: blr
276 ;
277 ; CHECK-FISL-LABEL: test10:
278 ; CHECK-FISL: # %bb.0: # %entry
279 ; CHECK-FISL-NEXT: xxlor v2, v2, v3
280 ; CHECK-FISL-NEXT: blr
281 ;
282 ; CHECK-LE-LABEL: test10:
283 ; CHECK-LE: # %bb.0: # %entry
284 ; CHECK-LE-NEXT: xxlor v2, v2, v3
285 ; CHECK-LE-NEXT: blr
286 entry:
287 %v = or <16 x i8> %a, %b
288 ret <16 x i8> %v
292 }
294 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
295 ; CHECK-LABEL: test11:
296 ; CHECK: # %bb.0: # %entry
297 ; CHECK-NEXT: xxland v2, v2, v3
298 ; CHECK-NEXT: blr
299 ;
300 ; CHECK-REG-LABEL: test11:
301 ; CHECK-REG: # %bb.0: # %entry
302 ; CHECK-REG-NEXT: xxland v2, v2, v3
303 ; CHECK-REG-NEXT: blr
304 ;
305 ; CHECK-FISL-LABEL: test11:
306 ; CHECK-FISL: # %bb.0: # %entry
307 ; CHECK-FISL-NEXT: xxland v2, v2, v3
308 ; CHECK-FISL-NEXT: blr
309 ;
310 ; CHECK-LE-LABEL: test11:
311 ; CHECK-LE: # %bb.0: # %entry
312 ; CHECK-LE-NEXT: xxland v2, v2, v3
313 ; CHECK-LE-NEXT: blr
314 entry:
315 %v = and <4 x i32> %a, %b
316 ret <4 x i32> %v
320 }
322 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
323 ; CHECK-LABEL: test12:
324 ; CHECK: # %bb.0: # %entry
325 ; CHECK-NEXT: xxland v2, v2, v3
326 ; CHECK-NEXT: blr
327 ;
328 ; CHECK-REG-LABEL: test12:
329 ; CHECK-REG: # %bb.0: # %entry
330 ; CHECK-REG-NEXT: xxland v2, v2, v3
331 ; CHECK-REG-NEXT: blr
332 ;
333 ; CHECK-FISL-LABEL: test12:
334 ; CHECK-FISL: # %bb.0: # %entry
335 ; CHECK-FISL-NEXT: xxland v2, v2, v3
336 ; CHECK-FISL-NEXT: blr
337 ;
338 ; CHECK-LE-LABEL: test12:
339 ; CHECK-LE: # %bb.0: # %entry
340 ; CHECK-LE-NEXT: xxland v2, v2, v3
341 ; CHECK-LE-NEXT: blr
342 entry:
343 %v = and <8 x i16> %a, %b
344 ret <8 x i16> %v
348 }
350 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
351 ; CHECK-LABEL: test13:
352 ; CHECK: # %bb.0: # %entry
353 ; CHECK-NEXT: xxland v2, v2, v3
354 ; CHECK-NEXT: blr
355 ;
356 ; CHECK-REG-LABEL: test13:
357 ; CHECK-REG: # %bb.0: # %entry
358 ; CHECK-REG-NEXT: xxland v2, v2, v3
359 ; CHECK-REG-NEXT: blr
360 ;
361 ; CHECK-FISL-LABEL: test13:
362 ; CHECK-FISL: # %bb.0: # %entry
363 ; CHECK-FISL-NEXT: xxland v2, v2, v3
364 ; CHECK-FISL-NEXT: blr
365 ;
366 ; CHECK-LE-LABEL: test13:
367 ; CHECK-LE: # %bb.0: # %entry
368 ; CHECK-LE-NEXT: xxland v2, v2, v3
369 ; CHECK-LE-NEXT: blr
370 entry:
371 %v = and <16 x i8> %a, %b
372 ret <16 x i8> %v
376 }
378 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
379 ; CHECK-LABEL: test14:
380 ; CHECK: # %bb.0: # %entry
381 ; CHECK-NEXT: xxlnor v2, v2, v3
382 ; CHECK-NEXT: blr
383 ;
384 ; CHECK-REG-LABEL: test14:
385 ; CHECK-REG: # %bb.0: # %entry
386 ; CHECK-REG-NEXT: xxlnor v2, v2, v3
387 ; CHECK-REG-NEXT: blr
388 ;
389 ; CHECK-FISL-LABEL: test14:
390 ; CHECK-FISL: # %bb.0: # %entry
391 ; CHECK-FISL-NEXT: xxlor vs0, v2, v3
392 ; CHECK-FISL-NEXT: xxlnor v2, v2, v3
393 ; CHECK-FISL-NEXT: blr
394 ;
395 ; CHECK-LE-LABEL: test14:
396 ; CHECK-LE: # %bb.0: # %entry
397 ; CHECK-LE-NEXT: xxlnor v2, v2, v3
398 ; CHECK-LE-NEXT: blr
399 entry:
400 %v = or <4 x i32> %a, %b
401 %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
402 ret <4 x i32> %w
406 }
408 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
409 ; CHECK-LABEL: test15:
410 ; CHECK: # %bb.0: # %entry
411 ; CHECK-NEXT: xxlnor v2, v2, v3
412 ; CHECK-NEXT: blr
413 ;
414 ; CHECK-REG-LABEL: test15:
415 ; CHECK-REG: # %bb.0: # %entry
416 ; CHECK-REG-NEXT: xxlnor v2, v2, v3
417 ; CHECK-REG-NEXT: blr
418 ;
419 ; CHECK-FISL-LABEL: test15:
420 ; CHECK-FISL: # %bb.0: # %entry
421 ; CHECK-FISL-NEXT: xxlor v4, v2, v3
422 ; CHECK-FISL-NEXT: xxlnor v2, v2, v3
423 ; CHECK-FISL-NEXT: blr
424 ;
425 ; CHECK-LE-LABEL: test15:
426 ; CHECK-LE: # %bb.0: # %entry
427 ; CHECK-LE-NEXT: xxlnor v2, v2, v3
428 ; CHECK-LE-NEXT: blr
429 entry:
430 %v = or <8 x i16> %a, %b
431 %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
432 ret <8 x i16> %w
436 }
438 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
439 ; CHECK-LABEL: test16:
440 ; CHECK: # %bb.0: # %entry
441 ; CHECK-NEXT: xxlnor v2, v2, v3
442 ; CHECK-NEXT: blr
443 ;
444 ; CHECK-REG-LABEL: test16:
445 ; CHECK-REG: # %bb.0: # %entry
446 ; CHECK-REG-NEXT: xxlnor v2, v2, v3
447 ; CHECK-REG-NEXT: blr
448 ;
449 ; CHECK-FISL-LABEL: test16:
450 ; CHECK-FISL: # %bb.0: # %entry
451 ; CHECK-FISL-NEXT: xxlor v4, v2, v3
452 ; CHECK-FISL-NEXT: xxlnor v2, v2, v3
453 ; CHECK-FISL-NEXT: blr
454 ;
455 ; CHECK-LE-LABEL: test16:
456 ; CHECK-LE: # %bb.0: # %entry
457 ; CHECK-LE-NEXT: xxlnor v2, v2, v3
458 ; CHECK-LE-NEXT: blr
459 entry:
460 %v = or <16 x i8> %a, %b
461 %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
462 ret <16 x i8> %w
466 }
468 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
469 ; CHECK-LABEL: test17:
470 ; CHECK: # %bb.0: # %entry
471 ; CHECK-NEXT: xxlandc v2, v2, v3
472 ; CHECK-NEXT: blr
473 ;
474 ; CHECK-REG-LABEL: test17:
475 ; CHECK-REG: # %bb.0: # %entry
476 ; CHECK-REG-NEXT: xxlandc v2, v2, v3
477 ; CHECK-REG-NEXT: blr
478 ;
479 ; CHECK-FISL-LABEL: test17:
480 ; CHECK-FISL: # %bb.0: # %entry
481 ; CHECK-FISL-NEXT: xxlnor vs0, v3, v3
482 ; CHECK-FISL-NEXT: xxland v2, v2, vs0
483 ; CHECK-FISL-NEXT: blr
484 ;
485 ; CHECK-LE-LABEL: test17:
486 ; CHECK-LE: # %bb.0: # %entry
487 ; CHECK-LE-NEXT: xxlandc v2, v2, v3
488 ; CHECK-LE-NEXT: blr
489 entry:
490 %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
491 %v = and <4 x i32> %a, %w
492 ret <4 x i32> %v
496 }
498 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
499 ; CHECK-LABEL: test18:
500 ; CHECK: # %bb.0: # %entry
501 ; CHECK-NEXT: xxlandc v2, v2, v3
502 ; CHECK-NEXT: blr
503 ;
504 ; CHECK-REG-LABEL: test18:
505 ; CHECK-REG: # %bb.0: # %entry
506 ; CHECK-REG-NEXT: xxlandc v2, v2, v3
507 ; CHECK-REG-NEXT: blr
508 ;
509 ; CHECK-FISL-LABEL: test18:
510 ; CHECK-FISL: # %bb.0: # %entry
511 ; CHECK-FISL-NEXT: xxlnor v4, v3, v3
512 ; CHECK-FISL-NEXT: xxlandc v2, v2, v3
513 ; CHECK-FISL-NEXT: blr
514 ;
515 ; CHECK-LE-LABEL: test18:
516 ; CHECK-LE: # %bb.0: # %entry
517 ; CHECK-LE-NEXT: xxlandc v2, v2, v3
518 ; CHECK-LE-NEXT: blr
519 entry:
520 %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
521 %v = and <8 x i16> %a, %w
522 ret <8 x i16> %v
526 }
528 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
529 ; CHECK-LABEL: test19:
530 ; CHECK: # %bb.0: # %entry
531 ; CHECK-NEXT: xxlandc v2, v2, v3
532 ; CHECK-NEXT: blr
533 ;
534 ; CHECK-REG-LABEL: test19:
535 ; CHECK-REG: # %bb.0: # %entry
536 ; CHECK-REG-NEXT: xxlandc v2, v2, v3
537 ; CHECK-REG-NEXT: blr
538 ;
539 ; CHECK-FISL-LABEL: test19:
540 ; CHECK-FISL: # %bb.0: # %entry
541 ; CHECK-FISL-NEXT: xxlnor v4, v3, v3
542 ; CHECK-FISL-NEXT: xxlandc v2, v2, v3
543 ; CHECK-FISL-NEXT: blr
544 ;
545 ; CHECK-LE-LABEL: test19:
546 ; CHECK-LE: # %bb.0: # %entry
547 ; CHECK-LE-NEXT: xxlandc v2, v2, v3
548 ; CHECK-LE-NEXT: blr
549 entry:
550 %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
551 %v = and <16 x i8> %a, %w
552 ret <16 x i8> %v
556 }
558 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
559 ; CHECK-LABEL: test20:
560 ; CHECK: # %bb.0: # %entry
561 ; CHECK-NEXT: vcmpequw v4, v4, v5
562 ; CHECK-NEXT: xxsel v2, v3, v2, v4
563 ; CHECK-NEXT: blr
564 ;
565 ; CHECK-REG-LABEL: test20:
566 ; CHECK-REG: # %bb.0: # %entry
567 ; CHECK-REG-NEXT: vcmpequw v4, v4, v5
568 ; CHECK-REG-NEXT: xxsel v2, v3, v2, v4
569 ; CHECK-REG-NEXT: blr
570 ;
571 ; CHECK-FISL-LABEL: test20:
572 ; CHECK-FISL: # %bb.0: # %entry
573 ; CHECK-FISL-NEXT: vcmpequw v4, v4, v5
574 ; CHECK-FISL-NEXT: xxsel v2, v3, v2, v4
575 ; CHECK-FISL-NEXT: blr
576 ;
577 ; CHECK-LE-LABEL: test20:
578 ; CHECK-LE: # %bb.0: # %entry
579 ; CHECK-LE-NEXT: vcmpequw v4, v4, v5
580 ; CHECK-LE-NEXT: xxsel v2, v3, v2, v4
581 ; CHECK-LE-NEXT: blr
582 entry:
583 %m = icmp eq <4 x i32> %c, %d
584 %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
585 ret <4 x i32> %v
589 }
591 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
592 ; CHECK-LABEL: test21:
593 ; CHECK: # %bb.0: # %entry
594 ; CHECK-NEXT: xvcmpeqsp vs0, v4, v5
595 ; CHECK-NEXT: xxsel v2, v3, v2, vs0
596 ; CHECK-NEXT: blr
597 ;
598 ; CHECK-REG-LABEL: test21:
599 ; CHECK-REG: # %bb.0: # %entry
600 ; CHECK-REG-NEXT: xvcmpeqsp vs0, v4, v5
601 ; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0
602 ; CHECK-REG-NEXT: blr
603 ;
604 ; CHECK-FISL-LABEL: test21:
605 ; CHECK-FISL: # %bb.0: # %entry
606 ; CHECK-FISL-NEXT: xvcmpeqsp vs0, v4, v5
607 ; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0
608 ; CHECK-FISL-NEXT: blr
609 ;
610 ; CHECK-LE-LABEL: test21:
611 ; CHECK-LE: # %bb.0: # %entry
612 ; CHECK-LE-NEXT: xvcmpeqsp vs0, v4, v5
613 ; CHECK-LE-NEXT: xxsel v2, v3, v2, vs0
614 ; CHECK-LE-NEXT: blr
615 entry:
616 %m = fcmp oeq <4 x float> %c, %d
617 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
618 ret <4 x float> %v
622 }
624 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
625 ; CHECK-LABEL: test22:
626 ; CHECK: # %bb.0: # %entry
627 ; CHECK-NEXT: xvcmpgtsp vs0, v5, v4
628 ; CHECK-NEXT: xvcmpgtsp vs1, v4, v5
629 ; CHECK-NEXT: xxlor vs0, vs1, vs0
630 ; CHECK-NEXT: xxsel v2, v2, v3, vs0
631 ; CHECK-NEXT: blr
632 ;
633 ; CHECK-REG-LABEL: test22:
634 ; CHECK-REG: # %bb.0: # %entry
635 ; CHECK-REG-NEXT: xvcmpgtsp vs0, v5, v4
636 ; CHECK-REG-NEXT: xvcmpgtsp vs1, v4, v5
637 ; CHECK-REG-NEXT: xxlor vs0, vs1, vs0
638 ; CHECK-REG-NEXT: xxsel v2, v2, v3, vs0
639 ; CHECK-REG-NEXT: blr
640 ;
641 ; CHECK-FISL-LABEL: test22:
642 ; CHECK-FISL: # %bb.0: # %entry
643 ; CHECK-FISL-NEXT: xvcmpgtsp vs1, v5, v4
644 ; CHECK-FISL-NEXT: xvcmpgtsp vs0, v4, v5
645 ; CHECK-FISL-NEXT: xxlor vs0, vs0, vs1
646 ; CHECK-FISL-NEXT: xxsel v2, v2, v3, vs0
647 ; CHECK-FISL-NEXT: blr
648 ;
649 ; CHECK-LE-LABEL: test22:
650 ; CHECK-LE: # %bb.0: # %entry
651 ; CHECK-LE-NEXT: xvcmpgtsp vs0, v5, v4
652 ; CHECK-LE-NEXT: xvcmpgtsp vs1, v4, v5
653 ; CHECK-LE-NEXT: xxlor vs0, vs1, vs0
654 ; CHECK-LE-NEXT: xxsel v2, v2, v3, vs0
655 ; CHECK-LE-NEXT: blr
656 entry:
657 %m = fcmp ueq <4 x float> %c, %d
658 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
659 ret <4 x float> %v
663 }
665 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
666 ; CHECK-LABEL: test23:
667 ; CHECK: # %bb.0: # %entry
668 ; CHECK-NEXT: vcmpequh v4, v4, v5
669 ; CHECK-NEXT: xxsel v2, v3, v2, v4
670 ; CHECK-NEXT: blr
671 ;
672 ; CHECK-REG-LABEL: test23:
673 ; CHECK-REG: # %bb.0: # %entry
674 ; CHECK-REG-NEXT: vcmpequh v4, v4, v5
675 ; CHECK-REG-NEXT: xxsel v2, v3, v2, v4
676 ; CHECK-REG-NEXT: blr
677 ;
678 ; CHECK-FISL-LABEL: test23:
679 ; CHECK-FISL: # %bb.0: # %entry
680 ; CHECK-FISL-NEXT: vcmpequh v4, v4, v5
681 ; CHECK-FISL-NEXT: xxlor vs0, v4, v4
682 ; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0
683 ; CHECK-FISL-NEXT: blr
684 ;
685 ; CHECK-LE-LABEL: test23:
686 ; CHECK-LE: # %bb.0: # %entry
687 ; CHECK-LE-NEXT: vcmpequh v4, v4, v5
688 ; CHECK-LE-NEXT: xxsel v2, v3, v2, v4
689 ; CHECK-LE-NEXT: blr
690 entry:
691 %m = icmp eq <8 x i16> %c, %d
692 %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
693 ret <8 x i16> %v
697 }
699 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
700 ; CHECK-LABEL: test24:
701 ; CHECK: # %bb.0: # %entry
702 ; CHECK-NEXT: vcmpequb v4, v4, v5
703 ; CHECK-NEXT: xxsel v2, v3, v2, v4
704 ; CHECK-NEXT: blr
705 ;
706 ; CHECK-REG-LABEL: test24:
707 ; CHECK-REG: # %bb.0: # %entry
708 ; CHECK-REG-NEXT: vcmpequb v4, v4, v5
709 ; CHECK-REG-NEXT: xxsel v2, v3, v2, v4
710 ; CHECK-REG-NEXT: blr
711 ;
712 ; CHECK-FISL-LABEL: test24:
713 ; CHECK-FISL: # %bb.0: # %entry
714 ; CHECK-FISL-NEXT: vcmpequb v4, v4, v5
715 ; CHECK-FISL-NEXT: xxlor vs0, v4, v4
716 ; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0
717 ; CHECK-FISL-NEXT: blr
718 ;
719 ; CHECK-LE-LABEL: test24:
720 ; CHECK-LE: # %bb.0: # %entry
721 ; CHECK-LE-NEXT: vcmpequb v4, v4, v5
722 ; CHECK-LE-NEXT: xxsel v2, v3, v2, v4
723 ; CHECK-LE-NEXT: blr
724 entry:
725 %m = icmp eq <16 x i8> %c, %d
726 %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
727 ret <16 x i8> %v
731 }
733 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
734 ; CHECK-LABEL: test25:
735 ; CHECK: # %bb.0: # %entry
736 ; CHECK-NEXT: xvcmpeqdp vs0, v4, v5
737 ; CHECK-NEXT: xxsel v2, v3, v2, vs0
738 ; CHECK-NEXT: blr
739 ;
740 ; CHECK-REG-LABEL: test25:
741 ; CHECK-REG: # %bb.0: # %entry
742 ; CHECK-REG-NEXT: xvcmpeqdp vs0, v4, v5
743 ; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0
744 ; CHECK-REG-NEXT: blr
745 ;
746 ; CHECK-FISL-LABEL: test25:
747 ; CHECK-FISL: # %bb.0: # %entry
748 ; CHECK-FISL-NEXT: xvcmpeqdp vs0, v4, v5
749 ; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0
750 ; CHECK-FISL-NEXT: blr
751 ;
752 ; CHECK-LE-LABEL: test25:
753 ; CHECK-LE: # %bb.0: # %entry
754 ; CHECK-LE-NEXT: xvcmpeqdp v4, v4, v5
755 ; CHECK-LE-NEXT: xxsel v2, v3, v2, v4
756 ; CHECK-LE-NEXT: blr
757 entry:
758 %m = fcmp oeq <2 x double> %c, %d
759 %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
760 ret <2 x double> %v
763 }
765 define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
766 ; CHECK-LABEL: test26:
767 ; CHECK: # %bb.0:
768 ; CHECK-NEXT: addi r3, r1, -32
769 ; CHECK-NEXT: addi r4, r1, -48
770 ; CHECK-NEXT: stxvd2x v3, 0, r3
771 ; CHECK-NEXT: stxvd2x v2, 0, r4
772 ; CHECK-NEXT: ld r3, -24(r1)
773 ; CHECK-NEXT: ld r4, -40(r1)
774 ; CHECK-NEXT: add r3, r4, r3
775 ; CHECK-NEXT: ld r4, -48(r1)
776 ; CHECK-NEXT: std r3, -8(r1)
777 ; CHECK-NEXT: ld r3, -32(r1)
778 ; CHECK-NEXT: add r3, r4, r3
779 ; CHECK-NEXT: std r3, -16(r1)
780 ; CHECK-NEXT: addi r3, r1, -16
781 ; CHECK-NEXT: lxvd2x v2, 0, r3
782 ; CHECK-NEXT: blr
783 ;
784 ; CHECK-REG-LABEL: test26:
785 ; CHECK-REG: # %bb.0:
786 ; CHECK-REG-NEXT: addi r3, r1, -32
787 ; CHECK-REG-NEXT: addi r4, r1, -48
788 ; CHECK-REG-NEXT: stxvd2x v3, 0, r3
789 ; CHECK-REG-NEXT: stxvd2x v2, 0, r4
790 ; CHECK-REG-NEXT: ld r3, -24(r1)
791 ; CHECK-REG-NEXT: ld r4, -40(r1)
792 ; CHECK-REG-NEXT: add r3, r4, r3
793 ; CHECK-REG-NEXT: ld r4, -48(r1)
794 ; CHECK-REG-NEXT: std r3, -8(r1)
795 ; CHECK-REG-NEXT: ld r3, -32(r1)
796 ; CHECK-REG-NEXT: add r3, r4, r3
797 ; CHECK-REG-NEXT: std r3, -16(r1)
798 ; CHECK-REG-NEXT: addi r3, r1, -16
799 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
800 ; CHECK-REG-NEXT: blr
801 ;
802 ; CHECK-FISL-LABEL: test26:
803 ; CHECK-FISL: # %bb.0:
804 ; CHECK-FISL-NEXT: addi r3, r1, -32
805 ; CHECK-FISL-NEXT: stxvd2x v3, 0, r3
806 ; CHECK-FISL-NEXT: addi r3, r1, -48
807 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
808 ; CHECK-FISL-NEXT: ld r4, -24(r1)
809 ; CHECK-FISL-NEXT: ld r3, -40(r1)
810 ; CHECK-FISL-NEXT: add r3, r3, r4
811 ; CHECK-FISL-NEXT: std r3, -8(r1)
812 ; CHECK-FISL-NEXT: ld r4, -32(r1)
813 ; CHECK-FISL-NEXT: ld r3, -48(r1)
814 ; CHECK-FISL-NEXT: add r3, r3, r4
815 ; CHECK-FISL-NEXT: std r3, -16(r1)
816 ; CHECK-FISL-NEXT: addi r3, r1, -16
817 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
818 ; CHECK-FISL-NEXT: blr
819 ;
820 ; CHECK-LE-LABEL: test26:
821 ; CHECK-LE: # %bb.0:
822 ; CHECK-LE-NEXT: vaddudm v2, v2, v3
823 ; CHECK-LE-NEXT: blr
824 %v = add <2 x i64> %a, %b
825 ret <2 x i64> %v
828 ; Make sure we use only two stores (one for each operand).
830 ; FIXME: The code quality here is not good; just make sure we do something for now.
832 }
834 define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
835 ; CHECK-LABEL: test27:
836 ; CHECK: # %bb.0:
837 ; CHECK-NEXT: xxland v2, v2, v3
838 ; CHECK-NEXT: blr
839 ;
840 ; CHECK-REG-LABEL: test27:
841 ; CHECK-REG: # %bb.0:
842 ; CHECK-REG-NEXT: xxland v2, v2, v3
843 ; CHECK-REG-NEXT: blr
844 ;
845 ; CHECK-FISL-LABEL: test27:
846 ; CHECK-FISL: # %bb.0:
847 ; CHECK-FISL-NEXT: xxland v2, v2, v3
848 ; CHECK-FISL-NEXT: blr
849 ;
850 ; CHECK-LE-LABEL: test27:
851 ; CHECK-LE: # %bb.0:
852 ; CHECK-LE-NEXT: xxland v2, v2, v3
853 ; CHECK-LE-NEXT: blr
854 %v = and <2 x i64> %a, %b
855 ret <2 x i64> %v
858 }
860 define <2 x double> @test28(<2 x double>* %a) {
861 ; CHECK-LABEL: test28:
862 ; CHECK: # %bb.0:
863 ; CHECK-NEXT: lxvd2x v2, 0, r3
864 ; CHECK-NEXT: blr
865 ;
866 ; CHECK-REG-LABEL: test28:
867 ; CHECK-REG: # %bb.0:
868 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
869 ; CHECK-REG-NEXT: blr
870 ;
871 ; CHECK-FISL-LABEL: test28:
872 ; CHECK-FISL: # %bb.0:
873 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
874 ; CHECK-FISL-NEXT: blr
875 ;
876 ; CHECK-LE-LABEL: test28:
877 ; CHECK-LE: # %bb.0:
878 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
879 ; CHECK-LE-NEXT: xxswapd v2, vs0
880 ; CHECK-LE-NEXT: blr
881 %v = load <2 x double>, <2 x double>* %a, align 16
882 ret <2 x double> %v
885 }
887 define void @test29(<2 x double>* %a, <2 x double> %b) {
888 ; CHECK-LABEL: test29:
889 ; CHECK: # %bb.0:
890 ; CHECK-NEXT: stxvd2x v2, 0, r3
891 ; CHECK-NEXT: blr
892 ;
893 ; CHECK-REG-LABEL: test29:
894 ; CHECK-REG: # %bb.0:
895 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
896 ; CHECK-REG-NEXT: blr
897 ;
898 ; CHECK-FISL-LABEL: test29:
899 ; CHECK-FISL: # %bb.0:
900 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
901 ; CHECK-FISL-NEXT: blr
902 ;
903 ; CHECK-LE-LABEL: test29:
904 ; CHECK-LE: # %bb.0:
905 ; CHECK-LE-NEXT: xxswapd vs0, v2
906 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
907 ; CHECK-LE-NEXT: blr
908 store <2 x double> %b, <2 x double>* %a, align 16
909 ret void
912 }
914 define <2 x double> @test28u(<2 x double>* %a) {
915 ; CHECK-LABEL: test28u:
916 ; CHECK: # %bb.0:
917 ; CHECK-NEXT: lxvd2x v2, 0, r3
918 ; CHECK-NEXT: blr
919 ;
920 ; CHECK-REG-LABEL: test28u:
921 ; CHECK-REG: # %bb.0:
922 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
923 ; CHECK-REG-NEXT: blr
924 ;
925 ; CHECK-FISL-LABEL: test28u:
926 ; CHECK-FISL: # %bb.0:
927 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
928 ; CHECK-FISL-NEXT: blr
929 ;
930 ; CHECK-LE-LABEL: test28u:
931 ; CHECK-LE: # %bb.0:
932 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
933 ; CHECK-LE-NEXT: xxswapd v2, vs0
934 ; CHECK-LE-NEXT: blr
935 %v = load <2 x double>, <2 x double>* %a, align 8
936 ret <2 x double> %v
939 }
941 define void @test29u(<2 x double>* %a, <2 x double> %b) {
942 ; CHECK-LABEL: test29u:
943 ; CHECK: # %bb.0:
944 ; CHECK-NEXT: stxvd2x v2, 0, r3
945 ; CHECK-NEXT: blr
946 ;
947 ; CHECK-REG-LABEL: test29u:
948 ; CHECK-REG: # %bb.0:
949 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
950 ; CHECK-REG-NEXT: blr
951 ;
952 ; CHECK-FISL-LABEL: test29u:
953 ; CHECK-FISL: # %bb.0:
954 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
955 ; CHECK-FISL-NEXT: blr
956 ;
957 ; CHECK-LE-LABEL: test29u:
958 ; CHECK-LE: # %bb.0:
959 ; CHECK-LE-NEXT: xxswapd vs0, v2
960 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
961 ; CHECK-LE-NEXT: blr
962 store <2 x double> %b, <2 x double>* %a, align 8
963 ret void
966 }
968 define <2 x i64> @test30(<2 x i64>* %a) {
969 ; CHECK-LABEL: test30:
970 ; CHECK: # %bb.0:
971 ; CHECK-NEXT: lxvd2x v2, 0, r3
972 ; CHECK-NEXT: blr
973 ;
974 ; CHECK-REG-LABEL: test30:
975 ; CHECK-REG: # %bb.0:
976 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
977 ; CHECK-REG-NEXT: blr
978 ;
979 ; CHECK-FISL-LABEL: test30:
980 ; CHECK-FISL: # %bb.0:
981 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
982 ; CHECK-FISL-NEXT: blr
983 ;
984 ; CHECK-LE-LABEL: test30:
985 ; CHECK-LE: # %bb.0:
986 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
987 ; CHECK-LE-NEXT: xxswapd v2, vs0
988 ; CHECK-LE-NEXT: blr
989 %v = load <2 x i64>, <2 x i64>* %a, align 16
990 ret <2 x i64> %v
994 }
996 define void @test31(<2 x i64>* %a, <2 x i64> %b) {
997 ; CHECK-LABEL: test31:
998 ; CHECK: # %bb.0:
999 ; CHECK-NEXT: stxvd2x v2, 0, r3
1000 ; CHECK-NEXT: blr
1001 ;
1002 ; CHECK-REG-LABEL: test31:
1003 ; CHECK-REG: # %bb.0:
1004 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
1005 ; CHECK-REG-NEXT: blr
1006 ;
1007 ; CHECK-FISL-LABEL: test31:
1008 ; CHECK-FISL: # %bb.0:
1009 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
1010 ; CHECK-FISL-NEXT: blr
1011 ;
1012 ; CHECK-LE-LABEL: test31:
1013 ; CHECK-LE: # %bb.0:
1014 ; CHECK-LE-NEXT: xxswapd vs0, v2
1015 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
1016 ; CHECK-LE-NEXT: blr
1017 store <2 x i64> %b, <2 x i64>* %a, align 16
1018 ret void
1021 }
1023 define <4 x float> @test32(<4 x float>* %a) {
1024 ; CHECK-LABEL: test32:
1025 ; CHECK: # %bb.0:
1026 ; CHECK-NEXT: lxvw4x v2, 0, r3
1027 ; CHECK-NEXT: blr
1028 ;
1029 ; CHECK-REG-LABEL: test32:
1030 ; CHECK-REG: # %bb.0:
1031 ; CHECK-REG-NEXT: lxvw4x v2, 0, r3
1032 ; CHECK-REG-NEXT: blr
1033 ;
1034 ; CHECK-FISL-LABEL: test32:
1035 ; CHECK-FISL: # %bb.0:
1036 ; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
1037 ; CHECK-FISL-NEXT: blr
1038 ;
1039 ; CHECK-LE-LABEL: test32:
1040 ; CHECK-LE: # %bb.0:
1041 ; CHECK-LE-NEXT: lvx v2, 0, r3
1042 ; CHECK-LE-NEXT: blr
1043 %v = load <4 x float>, <4 x float>* %a, align 16
1044 ret <4 x float> %v
1048 }
1050 define void @test33(<4 x float>* %a, <4 x float> %b) {
1051 ; CHECK-LABEL: test33:
1052 ; CHECK: # %bb.0:
1053 ; CHECK-NEXT: stxvw4x v2, 0, r3
1054 ; CHECK-NEXT: blr
1055 ;
1056 ; CHECK-REG-LABEL: test33:
1057 ; CHECK-REG: # %bb.0:
1058 ; CHECK-REG-NEXT: stxvw4x v2, 0, r3
1059 ; CHECK-REG-NEXT: blr
1060 ;
1061 ; CHECK-FISL-LABEL: test33:
1062 ; CHECK-FISL: # %bb.0:
1063 ; CHECK-FISL-NEXT: stxvw4x v2, 0, r3
1064 ; CHECK-FISL-NEXT: blr
1065 ;
1066 ; CHECK-LE-LABEL: test33:
1067 ; CHECK-LE: # %bb.0:
1068 ; CHECK-LE-NEXT: stvx v2, 0, r3
1069 ; CHECK-LE-NEXT: blr
1070 store <4 x float> %b, <4 x float>* %a, align 16
1071 ret void
1075 }
1077 define <4 x float> @test32u(<4 x float>* %a) {
1078 ; CHECK-LABEL: test32u:
1079 ; CHECK: # %bb.0:
1080 ; CHECK-NEXT: li r4, 15
1081 ; CHECK-NEXT: lvsl v3, 0, r3
1082 ; CHECK-NEXT: lvx v2, r3, r4
1083 ; CHECK-NEXT: lvx v4, 0, r3
1084 ; CHECK-NEXT: vperm v2, v4, v2, v3
1085 ; CHECK-NEXT: blr
1086 ;
1087 ; CHECK-REG-LABEL: test32u:
1088 ; CHECK-REG: # %bb.0:
1089 ; CHECK-REG-NEXT: li r4, 15
1090 ; CHECK-REG-NEXT: lvsl v3, 0, r3
1091 ; CHECK-REG-NEXT: lvx v2, r3, r4
1092 ; CHECK-REG-NEXT: lvx v4, 0, r3
1093 ; CHECK-REG-NEXT: vperm v2, v4, v2, v3
1094 ; CHECK-REG-NEXT: blr
1095 ;
1096 ; CHECK-FISL-LABEL: test32u:
1097 ; CHECK-FISL: # %bb.0:
1098 ; CHECK-FISL-NEXT: li r4, 15
1099 ; CHECK-FISL-NEXT: lvx v3, r3, r4
1100 ; CHECK-FISL-NEXT: lvsl v4, 0, r3
1101 ; CHECK-FISL-NEXT: lvx v2, 0, r3
1102 ; CHECK-FISL-NEXT: vperm v2, v2, v3, v4
1103 ; CHECK-FISL-NEXT: blr
1104 ;
1105 ; CHECK-LE-LABEL: test32u:
1106 ; CHECK-LE: # %bb.0:
1107 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
1108 ; CHECK-LE-NEXT: xxswapd v2, vs0
1109 ; CHECK-LE-NEXT: blr
1110 %v = load <4 x float>, <4 x float>* %a, align 8
1111 ret <4 x float> %v
1114 }
1116 define void @test33u(<4 x float>* %a, <4 x float> %b) {
1117 ; CHECK-LABEL: test33u:
1118 ; CHECK: # %bb.0:
1119 ; CHECK-NEXT: stxvw4x v2, 0, r3
1120 ; CHECK-NEXT: blr
1121 ;
1122 ; CHECK-REG-LABEL: test33u:
1123 ; CHECK-REG: # %bb.0:
1124 ; CHECK-REG-NEXT: stxvw4x v2, 0, r3
1125 ; CHECK-REG-NEXT: blr
1126 ;
1127 ; CHECK-FISL-LABEL: test33u:
1128 ; CHECK-FISL: # %bb.0:
1129 ; CHECK-FISL-NEXT: stxvw4x v2, 0, r3
1130 ; CHECK-FISL-NEXT: blr
1131 ;
1132 ; CHECK-LE-LABEL: test33u:
1133 ; CHECK-LE: # %bb.0:
1134 ; CHECK-LE-NEXT: xxswapd vs0, v2
1135 ; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
1136 ; CHECK-LE-NEXT: blr
1137 store <4 x float> %b, <4 x float>* %a, align 8
1138 ret void
1142 }
1144 define <4 x i32> @test34(<4 x i32>* %a) {
1145 ; CHECK-LABEL: test34:
1146 ; CHECK: # %bb.0:
1147 ; CHECK-NEXT: lxvw4x v2, 0, r3
1148 ; CHECK-NEXT: blr
1149 ;
1150 ; CHECK-REG-LABEL: test34:
1151 ; CHECK-REG: # %bb.0:
1152 ; CHECK-REG-NEXT: lxvw4x v2, 0, r3
1153 ; CHECK-REG-NEXT: blr
1154 ;
1155 ; CHECK-FISL-LABEL: test34:
1156 ; CHECK-FISL: # %bb.0:
1157 ; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
1158 ; CHECK-FISL-NEXT: blr
1159 ;
1160 ; CHECK-LE-LABEL: test34:
1161 ; CHECK-LE: # %bb.0:
1162 ; CHECK-LE-NEXT: lvx v2, 0, r3
1163 ; CHECK-LE-NEXT: blr
1164 %v = load <4 x i32>, <4 x i32>* %a, align 16
1165 ret <4 x i32> %v
1169 }
1171 define void @test35(<4 x i32>* %a, <4 x i32> %b) {
1172 ; CHECK-LABEL: test35:
1173 ; CHECK: # %bb.0:
1174 ; CHECK-NEXT: stxvw4x v2, 0, r3
1175 ; CHECK-NEXT: blr
1176 ;
1177 ; CHECK-REG-LABEL: test35:
1178 ; CHECK-REG: # %bb.0:
1179 ; CHECK-REG-NEXT: stxvw4x v2, 0, r3
1180 ; CHECK-REG-NEXT: blr
1181 ;
1182 ; CHECK-FISL-LABEL: test35:
1183 ; CHECK-FISL: # %bb.0:
1184 ; CHECK-FISL-NEXT: stxvw4x v2, 0, r3
1185 ; CHECK-FISL-NEXT: blr
1186 ;
1187 ; CHECK-LE-LABEL: test35:
1188 ; CHECK-LE: # %bb.0:
1189 ; CHECK-LE-NEXT: stvx v2, 0, r3
1190 ; CHECK-LE-NEXT: blr
1191 store <4 x i32> %b, <4 x i32>* %a, align 16
1192 ret void
1196 }
1198 define <2 x double> @test40(<2 x i64> %a) {
1199 ; CHECK-LABEL: test40:
1200 ; CHECK: # %bb.0:
1201 ; CHECK-NEXT: xvcvuxddp v2, v2
1202 ; CHECK-NEXT: blr
1203 ;
1204 ; CHECK-REG-LABEL: test40:
1205 ; CHECK-REG: # %bb.0:
1206 ; CHECK-REG-NEXT: xvcvuxddp v2, v2
1207 ; CHECK-REG-NEXT: blr
1208 ;
1209 ; CHECK-FISL-LABEL: test40:
1210 ; CHECK-FISL: # %bb.0:
1211 ; CHECK-FISL-NEXT: xvcvuxddp v2, v2
1212 ; CHECK-FISL-NEXT: blr
1213 ;
1214 ; CHECK-LE-LABEL: test40:
1215 ; CHECK-LE: # %bb.0:
1216 ; CHECK-LE-NEXT: xvcvuxddp v2, v2
1217 ; CHECK-LE-NEXT: blr
1218 %v = uitofp <2 x i64> %a to <2 x double>
1219 ret <2 x double> %v
1222 }
1224 define <2 x double> @test41(<2 x i64> %a) {
1225 ; CHECK-LABEL: test41:
1226 ; CHECK: # %bb.0:
1227 ; CHECK-NEXT: xvcvsxddp v2, v2
1228 ; CHECK-NEXT: blr
1229 ;
1230 ; CHECK-REG-LABEL: test41:
1231 ; CHECK-REG: # %bb.0:
1232 ; CHECK-REG-NEXT: xvcvsxddp v2, v2
1233 ; CHECK-REG-NEXT: blr
1234 ;
1235 ; CHECK-FISL-LABEL: test41:
1236 ; CHECK-FISL: # %bb.0:
1237 ; CHECK-FISL-NEXT: xvcvsxddp v2, v2
1238 ; CHECK-FISL-NEXT: blr
1239 ;
1240 ; CHECK-LE-LABEL: test41:
1241 ; CHECK-LE: # %bb.0:
1242 ; CHECK-LE-NEXT: xvcvsxddp v2, v2
1243 ; CHECK-LE-NEXT: blr
1244 %v = sitofp <2 x i64> %a to <2 x double>
1245 ret <2 x double> %v
1248 }
1250 define <2 x i64> @test42(<2 x double> %a) {
1251 ; CHECK-LABEL: test42:
1252 ; CHECK: # %bb.0:
1253 ; CHECK-NEXT: xvcvdpuxds v2, v2
1254 ; CHECK-NEXT: blr
1255 ;
1256 ; CHECK-REG-LABEL: test42:
1257 ; CHECK-REG: # %bb.0:
1258 ; CHECK-REG-NEXT: xvcvdpuxds v2, v2
1259 ; CHECK-REG-NEXT: blr
1260 ;
1261 ; CHECK-FISL-LABEL: test42:
1262 ; CHECK-FISL: # %bb.0:
1263 ; CHECK-FISL-NEXT: xvcvdpuxds v2, v2
1264 ; CHECK-FISL-NEXT: blr
1265 ;
1266 ; CHECK-LE-LABEL: test42:
1267 ; CHECK-LE: # %bb.0:
1268 ; CHECK-LE-NEXT: xvcvdpuxds v2, v2
1269 ; CHECK-LE-NEXT: blr
1270 %v = fptoui <2 x double> %a to <2 x i64>
1271 ret <2 x i64> %v
1274 }
1276 define <2 x i64> @test43(<2 x double> %a) {
1277 ; CHECK-LABEL: test43:
1278 ; CHECK: # %bb.0:
1279 ; CHECK-NEXT: xvcvdpsxds v2, v2
1280 ; CHECK-NEXT: blr
1281 ;
1282 ; CHECK-REG-LABEL: test43:
1283 ; CHECK-REG: # %bb.0:
1284 ; CHECK-REG-NEXT: xvcvdpsxds v2, v2
1285 ; CHECK-REG-NEXT: blr
1286 ;
1287 ; CHECK-FISL-LABEL: test43:
1288 ; CHECK-FISL: # %bb.0:
1289 ; CHECK-FISL-NEXT: xvcvdpsxds v2, v2
1290 ; CHECK-FISL-NEXT: blr
1291 ;
1292 ; CHECK-LE-LABEL: test43:
1293 ; CHECK-LE: # %bb.0:
1294 ; CHECK-LE-NEXT: xvcvdpsxds v2, v2
1295 ; CHECK-LE-NEXT: blr
1296 %v = fptosi <2 x double> %a to <2 x i64>
1297 ret <2 x i64> %v
1300 }
1302 define <2 x float> @test44(<2 x i64> %a) {
1303 ; CHECK-LABEL: test44:
1304 ; CHECK: # %bb.0:
1305 ; CHECK-NEXT: addi r3, r1, -16
1306 ; CHECK-NEXT: addi r4, r1, -64
1307 ; CHECK-NEXT: stxvd2x v2, 0, r3
1308 ; CHECK-NEXT: ld r3, -8(r1)
1309 ; CHECK-NEXT: std r3, -24(r1)
1310 ; CHECK-NEXT: ld r3, -16(r1)
1311 ; CHECK-NEXT: lfd f0, -24(r1)
1312 ; CHECK-NEXT: std r3, -32(r1)
1313 ; CHECK-NEXT: addi r3, r1, -48
1314 ; CHECK-NEXT: fcfidus f0, f0
1315 ; CHECK-NEXT: stfs f0, -48(r1)
1316 ; CHECK-NEXT: lfd f0, -32(r1)
1317 ; CHECK-NEXT: fcfidus f0, f0
1318 ; CHECK-NEXT: stfs f0, -64(r1)
1319 ; CHECK-NEXT: lxvw4x v2, 0, r3
1320 ; CHECK-NEXT: lxvw4x v3, 0, r4
1321 ; CHECK-NEXT: vmrghw v2, v3, v2
1322 ; CHECK-NEXT: blr
1323 ;
1324 ; CHECK-REG-LABEL: test44:
1325 ; CHECK-REG: # %bb.0:
1326 ; CHECK-REG-NEXT: addi r3, r1, -16
1327 ; CHECK-REG-NEXT: addi r4, r1, -64
1328 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
1329 ; CHECK-REG-NEXT: ld r3, -8(r1)
1330 ; CHECK-REG-NEXT: std r3, -24(r1)
1331 ; CHECK-REG-NEXT: ld r3, -16(r1)
1332 ; CHECK-REG-NEXT: lfd f0, -24(r1)
1333 ; CHECK-REG-NEXT: std r3, -32(r1)
1334 ; CHECK-REG-NEXT: addi r3, r1, -48
1335 ; CHECK-REG-NEXT: fcfidus f0, f0
1336 ; CHECK-REG-NEXT: stfs f0, -48(r1)
1337 ; CHECK-REG-NEXT: lfd f0, -32(r1)
1338 ; CHECK-REG-NEXT: fcfidus f0, f0
1339 ; CHECK-REG-NEXT: stfs f0, -64(r1)
1340 ; CHECK-REG-NEXT: lxvw4x v2, 0, r3
1341 ; CHECK-REG-NEXT: lxvw4x v3, 0, r4
1342 ; CHECK-REG-NEXT: vmrghw v2, v3, v2
1343 ; CHECK-REG-NEXT: blr
1344 ;
1345 ; CHECK-FISL-LABEL: test44:
1346 ; CHECK-FISL: # %bb.0:
1347 ; CHECK-FISL-NEXT: addi r3, r1, -16
1348 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
1349 ; CHECK-FISL-NEXT: ld r3, -8(r1)
1350 ; CHECK-FISL-NEXT: std r3, -24(r1)
1351 ; CHECK-FISL-NEXT: ld r3, -16(r1)
1352 ; CHECK-FISL-NEXT: std r3, -32(r1)
1353 ; CHECK-FISL-NEXT: lfd f0, -24(r1)
1354 ; CHECK-FISL-NEXT: fcfidus f0, f0
1355 ; CHECK-FISL-NEXT: stfs f0, -48(r1)
1356 ; CHECK-FISL-NEXT: lfd f0, -32(r1)
1357 ; CHECK-FISL-NEXT: fcfidus f0, f0
1358 ; CHECK-FISL-NEXT: stfs f0, -64(r1)
1359 ; CHECK-FISL-NEXT: addi r3, r1, -48
1360 ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3
1361 ; CHECK-FISL-NEXT: addi r3, r1, -64
1362 ; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
1363 ; CHECK-FISL-NEXT: vmrghw v2, v2, v3
1364 ; CHECK-FISL-NEXT: blr
1365 ;
1366 ; CHECK-LE-LABEL: test44:
1367 ; CHECK-LE: # %bb.0:
1368 ; CHECK-LE-NEXT: xxswapd vs0, v2
1369 ; CHECK-LE-NEXT: xscvuxdsp f1, v2
1370 ; CHECK-LE-NEXT: xscvuxdsp f0, f0
1371 ; CHECK-LE-NEXT: xscvdpspn v3, f1
1372 ; CHECK-LE-NEXT: xscvdpspn v2, f0
1373 ; CHECK-LE-NEXT: vmrghw v2, v3, v2
1374 ; CHECK-LE-NEXT: blr
1375 %v = uitofp <2 x i64> %a to <2 x float>
1376 ret <2 x float> %v
1378 ; FIXME: The code quality here looks pretty bad.
1379 }
1381 define <2 x float> @test45(<2 x i64> %a) {
1382 ; CHECK-LABEL: test45:
1383 ; CHECK: # %bb.0:
1384 ; CHECK-NEXT: addi r3, r1, -16
1385 ; CHECK-NEXT: addi r4, r1, -64
1386 ; CHECK-NEXT: stxvd2x v2, 0, r3
1387 ; CHECK-NEXT: ld r3, -8(r1)
1388 ; CHECK-NEXT: std r3, -24(r1)
1389 ; CHECK-NEXT: ld r3, -16(r1)
1390 ; CHECK-NEXT: lfd f0, -24(r1)
1391 ; CHECK-NEXT: std r3, -32(r1)
1392 ; CHECK-NEXT: addi r3, r1, -48
1393 ; CHECK-NEXT: fcfids f0, f0
1394 ; CHECK-NEXT: stfs f0, -48(r1)
1395 ; CHECK-NEXT: lfd f0, -32(r1)
1396 ; CHECK-NEXT: fcfids f0, f0
1397 ; CHECK-NEXT: stfs f0, -64(r1)
1398 ; CHECK-NEXT: lxvw4x v2, 0, r3
1399 ; CHECK-NEXT: lxvw4x v3, 0, r4
1400 ; CHECK-NEXT: vmrghw v2, v3, v2
1401 ; CHECK-NEXT: blr
1402 ;
1403 ; CHECK-REG-LABEL: test45:
1404 ; CHECK-REG: # %bb.0:
1405 ; CHECK-REG-NEXT: addi r3, r1, -16
1406 ; CHECK-REG-NEXT: addi r4, r1, -64
1407 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
1408 ; CHECK-REG-NEXT: ld r3, -8(r1)
1409 ; CHECK-REG-NEXT: std r3, -24(r1)
1410 ; CHECK-REG-NEXT: ld r3, -16(r1)
1411 ; CHECK-REG-NEXT: lfd f0, -24(r1)
1412 ; CHECK-REG-NEXT: std r3, -32(r1)
1413 ; CHECK-REG-NEXT: addi r3, r1, -48
1414 ; CHECK-REG-NEXT: fcfids f0, f0
1415 ; CHECK-REG-NEXT: stfs f0, -48(r1)
1416 ; CHECK-REG-NEXT: lfd f0, -32(r1)
1417 ; CHECK-REG-NEXT: fcfids f0, f0
1418 ; CHECK-REG-NEXT: stfs f0, -64(r1)
1419 ; CHECK-REG-NEXT: lxvw4x v2, 0, r3
1420 ; CHECK-REG-NEXT: lxvw4x v3, 0, r4
1421 ; CHECK-REG-NEXT: vmrghw v2, v3, v2
1422 ; CHECK-REG-NEXT: blr
1423 ;
1424 ; CHECK-FISL-LABEL: test45:
1425 ; CHECK-FISL: # %bb.0:
1426 ; CHECK-FISL-NEXT: addi r3, r1, -16
1427 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
1428 ; CHECK-FISL-NEXT: ld r3, -8(r1)
1429 ; CHECK-FISL-NEXT: std r3, -24(r1)
1430 ; CHECK-FISL-NEXT: ld r3, -16(r1)
1431 ; CHECK-FISL-NEXT: std r3, -32(r1)
1432 ; CHECK-FISL-NEXT: lfd f0, -24(r1)
1433 ; CHECK-FISL-NEXT: fcfids f0, f0
1434 ; CHECK-FISL-NEXT: stfs f0, -48(r1)
1435 ; CHECK-FISL-NEXT: lfd f0, -32(r1)
1436 ; CHECK-FISL-NEXT: fcfids f0, f0
1437 ; CHECK-FISL-NEXT: stfs f0, -64(r1)
1438 ; CHECK-FISL-NEXT: addi r3, r1, -48
1439 ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3
1440 ; CHECK-FISL-NEXT: addi r3, r1, -64
1441 ; CHECK-FISL-NEXT: lxvw4x v2, 0, r3
1442 ; CHECK-FISL-NEXT: vmrghw v2, v2, v3
1443 ; CHECK-FISL-NEXT: blr
1444 ;
1445 ; CHECK-LE-LABEL: test45:
1446 ; CHECK-LE: # %bb.0:
1447 ; CHECK-LE-NEXT: xxswapd vs0, v2
1448 ; CHECK-LE-NEXT: xscvsxdsp f1, v2
1449 ; CHECK-LE-NEXT: xscvsxdsp f0, f0
1450 ; CHECK-LE-NEXT: xscvdpspn v3, f1
1451 ; CHECK-LE-NEXT: xscvdpspn v2, f0
1452 ; CHECK-LE-NEXT: vmrghw v2, v3, v2
1453 ; CHECK-LE-NEXT: blr
1454 %v = sitofp <2 x i64> %a to <2 x float>
1455 ret <2 x float> %v
1457 ; FIXME: The code quality here looks pretty bad.
1458 }
1460 define <2 x i64> @test46(<2 x float> %a) {
1461 ; CHECK-LABEL: test46:
1462 ; CHECK: # %bb.0:
1463 ; CHECK-NEXT: addi r3, r1, -48
1464 ; CHECK-NEXT: stxvw4x v2, 0, r3
1465 ; CHECK-NEXT: lfs f0, -44(r1)
1466 ; CHECK-NEXT: xscvdpuxds f0, f0
1467 ; CHECK-NEXT: stfd f0, -32(r1)
1468 ; CHECK-NEXT: lfs f0, -48(r1)
1469 ; CHECK-NEXT: ld r3, -32(r1)
1470 ; CHECK-NEXT: xscvdpuxds f0, f0
1471 ; CHECK-NEXT: std r3, -8(r1)
1472 ; CHECK-NEXT: stfd f0, -24(r1)
1473 ; CHECK-NEXT: ld r3, -24(r1)
1474 ; CHECK-NEXT: std r3, -16(r1)
1475 ; CHECK-NEXT: addi r3, r1, -16
1476 ; CHECK-NEXT: lxvd2x v2, 0, r3
1477 ; CHECK-NEXT: blr
1478 ;
1479 ; CHECK-REG-LABEL: test46:
1480 ; CHECK-REG: # %bb.0:
1481 ; CHECK-REG-NEXT: addi r3, r1, -48
1482 ; CHECK-REG-NEXT: stxvw4x v2, 0, r3
1483 ; CHECK-REG-NEXT: lfs f0, -44(r1)
1484 ; CHECK-REG-NEXT: xscvdpuxds f0, f0
1485 ; CHECK-REG-NEXT: stfd f0, -32(r1)
1486 ; CHECK-REG-NEXT: lfs f0, -48(r1)
1487 ; CHECK-REG-NEXT: ld r3, -32(r1)
1488 ; CHECK-REG-NEXT: xscvdpuxds f0, f0
1489 ; CHECK-REG-NEXT: std r3, -8(r1)
1490 ; CHECK-REG-NEXT: stfd f0, -24(r1)
1491 ; CHECK-REG-NEXT: ld r3, -24(r1)
1492 ; CHECK-REG-NEXT: std r3, -16(r1)
1493 ; CHECK-REG-NEXT: addi r3, r1, -16
1494 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
1495 ; CHECK-REG-NEXT: blr
1496 ;
1497 ; CHECK-FISL-LABEL: test46:
1498 ; CHECK-FISL: # %bb.0:
1499 ; CHECK-FISL-NEXT: addi r3, r1, -48
1500 ; CHECK-FISL-NEXT: stxvw4x v2, 0, r3
1501 ; CHECK-FISL-NEXT: lfs f0, -44(r1)
1502 ; CHECK-FISL-NEXT: xscvdpuxds f0, f0
1503 ; CHECK-FISL-NEXT: stfd f0, -32(r1)
1504 ; CHECK-FISL-NEXT: lfs f0, -48(r1)
1505 ; CHECK-FISL-NEXT: xscvdpuxds f0, f0
1506 ; CHECK-FISL-NEXT: stfd f0, -24(r1)
1507 ; CHECK-FISL-NEXT: ld r3, -32(r1)
1508 ; CHECK-FISL-NEXT: std r3, -8(r1)
1509 ; CHECK-FISL-NEXT: ld r3, -24(r1)
1510 ; CHECK-FISL-NEXT: std r3, -16(r1)
1511 ; CHECK-FISL-NEXT: addi r3, r1, -16
1512 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
1513 ; CHECK-FISL-NEXT: blr
1514 ;
1515 ; CHECK-LE-LABEL: test46:
1516 ; CHECK-LE: # %bb.0:
1517 ; CHECK-LE-NEXT: xxmrglw vs0, v2, v2
1518 ; CHECK-LE-NEXT: xvcvspdp vs0, vs0
1519 ; CHECK-LE-NEXT: xvcvdpuxds v2, vs0
1520 ; CHECK-LE-NEXT: blr
1521 %v = fptoui <2 x float> %a to <2 x i64>
1522 ret <2 x i64> %v
1524 ; FIXME: The code quality here looks pretty bad.
1525 }
1527 define <2 x i64> @test47(<2 x float> %a) {
1528 ; CHECK-LABEL: test47:
1529 ; CHECK: # %bb.0:
1530 ; CHECK-NEXT: addi r3, r1, -48
1531 ; CHECK-NEXT: stxvw4x v2, 0, r3
1532 ; CHECK-NEXT: lfs f0, -44(r1)
1533 ; CHECK-NEXT: xscvdpsxds f0, f0
1534 ; CHECK-NEXT: stfd f0, -32(r1)
1535 ; CHECK-NEXT: lfs f0, -48(r1)
1536 ; CHECK-NEXT: ld r3, -32(r1)
1537 ; CHECK-NEXT: xscvdpsxds f0, f0
1538 ; CHECK-NEXT: std r3, -8(r1)
1539 ; CHECK-NEXT: stfd f0, -24(r1)
1540 ; CHECK-NEXT: ld r3, -24(r1)
1541 ; CHECK-NEXT: std r3, -16(r1)
1542 ; CHECK-NEXT: addi r3, r1, -16
1543 ; CHECK-NEXT: lxvd2x v2, 0, r3
1544 ; CHECK-NEXT: blr
1545 ;
1546 ; CHECK-REG-LABEL: test47:
1547 ; CHECK-REG: # %bb.0:
1548 ; CHECK-REG-NEXT: addi r3, r1, -48
1549 ; CHECK-REG-NEXT: stxvw4x v2, 0, r3
1550 ; CHECK-REG-NEXT: lfs f0, -44(r1)
1551 ; CHECK-REG-NEXT: xscvdpsxds f0, f0
1552 ; CHECK-REG-NEXT: stfd f0, -32(r1)
1553 ; CHECK-REG-NEXT: lfs f0, -48(r1)
1554 ; CHECK-REG-NEXT: ld r3, -32(r1)
1555 ; CHECK-REG-NEXT: xscvdpsxds f0, f0
1556 ; CHECK-REG-NEXT: std r3, -8(r1)
1557 ; CHECK-REG-NEXT: stfd f0, -24(r1)
1558 ; CHECK-REG-NEXT: ld r3, -24(r1)
1559 ; CHECK-REG-NEXT: std r3, -16(r1)
1560 ; CHECK-REG-NEXT: addi r3, r1, -16
1561 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
1562 ; CHECK-REG-NEXT: blr
1563 ;
1564 ; CHECK-FISL-LABEL: test47:
1565 ; CHECK-FISL: # %bb.0:
1566 ; CHECK-FISL-NEXT: addi r3, r1, -48
1567 ; CHECK-FISL-NEXT: stxvw4x v2, 0, r3
1568 ; CHECK-FISL-NEXT: lfs f0, -44(r1)
1569 ; CHECK-FISL-NEXT: xscvdpsxds f0, f0
1570 ; CHECK-FISL-NEXT: stfd f0, -32(r1)
1571 ; CHECK-FISL-NEXT: lfs f0, -48(r1)
1572 ; CHECK-FISL-NEXT: xscvdpsxds f0, f0
1573 ; CHECK-FISL-NEXT: stfd f0, -24(r1)
1574 ; CHECK-FISL-NEXT: ld r3, -32(r1)
1575 ; CHECK-FISL-NEXT: std r3, -8(r1)
1576 ; CHECK-FISL-NEXT: ld r3, -24(r1)
1577 ; CHECK-FISL-NEXT: std r3, -16(r1)
1578 ; CHECK-FISL-NEXT: addi r3, r1, -16
1579 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
1580 ; CHECK-FISL-NEXT: blr
1581 ;
1582 ; CHECK-LE-LABEL: test47:
1583 ; CHECK-LE: # %bb.0:
1584 ; CHECK-LE-NEXT: xxmrglw vs0, v2, v2
1585 ; CHECK-LE-NEXT: xvcvspdp vs0, vs0
1586 ; CHECK-LE-NEXT: xvcvdpsxds v2, vs0
1587 ; CHECK-LE-NEXT: blr
1588 %v = fptosi <2 x float> %a to <2 x i64>
1589 ret <2 x i64> %v
1591 ; FIXME: The code quality here looks pretty bad.
1592 }
1594 define <2 x double> @test50(double* %a) {
1595 ; CHECK-LABEL: test50:
1596 ; CHECK: # %bb.0:
1597 ; CHECK-NEXT: lxvdsx v2, 0, r3
1598 ; CHECK-NEXT: blr
1599 ;
1600 ; CHECK-REG-LABEL: test50:
1601 ; CHECK-REG: # %bb.0:
1602 ; CHECK-REG-NEXT: lxvdsx v2, 0, r3
1603 ; CHECK-REG-NEXT: blr
1604 ;
1605 ; CHECK-FISL-LABEL: test50:
1606 ; CHECK-FISL: # %bb.0:
1607 ; CHECK-FISL-NEXT: lxvdsx v2, 0, r3
1608 ; CHECK-FISL-NEXT: blr
1609 ;
1610 ; CHECK-LE-LABEL: test50:
1611 ; CHECK-LE: # %bb.0:
1612 ; CHECK-LE-NEXT: lxvdsx v2, 0, r3
1613 ; CHECK-LE-NEXT: blr
1614 %v = load double, double* %a, align 8
1615 %w = insertelement <2 x double> undef, double %v, i32 0
1616 %x = insertelement <2 x double> %w, double %v, i32 1
1617 ret <2 x double> %x
1620 }
1622 define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
1623 ; CHECK-LABEL: test51:
1624 ; CHECK: # %bb.0:
1625 ; CHECK-NEXT: xxspltd v2, v2, 0
1626 ; CHECK-NEXT: blr
1627 ;
1628 ; CHECK-REG-LABEL: test51:
1629 ; CHECK-REG: # %bb.0:
1630 ; CHECK-REG-NEXT: xxspltd v2, v2, 0
1631 ; CHECK-REG-NEXT: blr
1632 ;
1633 ; CHECK-FISL-LABEL: test51:
1634 ; CHECK-FISL: # %bb.0:
1635 ; CHECK-FISL-NEXT: xxspltd v2, v2, 0
1636 ; CHECK-FISL-NEXT: blr
1637 ;
1638 ; CHECK-LE-LABEL: test51:
1639 ; CHECK-LE: # %bb.0:
1640 ; CHECK-LE-NEXT: xxspltd v2, v2, 1
1641 ; CHECK-LE-NEXT: blr
1642 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
1643 ret <2 x double> %v
1646 }
1648 define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
1649 ; CHECK-LABEL: test52:
1650 ; CHECK: # %bb.0:
1651 ; CHECK-NEXT: xxmrghd v2, v2, v3
1652 ; CHECK-NEXT: blr
1653 ;
1654 ; CHECK-REG-LABEL: test52:
1655 ; CHECK-REG: # %bb.0:
1656 ; CHECK-REG-NEXT: xxmrghd v2, v2, v3
1657 ; CHECK-REG-NEXT: blr
1658 ;
1659 ; CHECK-FISL-LABEL: test52:
1660 ; CHECK-FISL: # %bb.0:
1661 ; CHECK-FISL-NEXT: xxmrghd v2, v2, v3
1662 ; CHECK-FISL-NEXT: blr
1663 ;
1664 ; CHECK-LE-LABEL: test52:
1665 ; CHECK-LE: # %bb.0:
1666 ; CHECK-LE-NEXT: xxmrgld v2, v3, v2
1667 ; CHECK-LE-NEXT: blr
1668 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
1669 ret <2 x double> %v
1672 }
1674 define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
1675 ; CHECK-LABEL: test53:
1676 ; CHECK: # %bb.0:
1677 ; CHECK-NEXT: xxmrghd v2, v3, v2
1678 ; CHECK-NEXT: blr
1679 ;
1680 ; CHECK-REG-LABEL: test53:
1681 ; CHECK-REG: # %bb.0:
1682 ; CHECK-REG-NEXT: xxmrghd v2, v3, v2
1683 ; CHECK-REG-NEXT: blr
1684 ;
1685 ; CHECK-FISL-LABEL: test53:
1686 ; CHECK-FISL: # %bb.0:
1687 ; CHECK-FISL-NEXT: xxmrghd v2, v3, v2
1688 ; CHECK-FISL-NEXT: blr
1689 ;
1690 ; CHECK-LE-LABEL: test53:
1691 ; CHECK-LE: # %bb.0:
1692 ; CHECK-LE-NEXT: xxmrgld v2, v2, v3
1693 ; CHECK-LE-NEXT: blr
1694 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
1695 ret <2 x double> %v
1698 }
1700 define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
1701 ; CHECK-LABEL: test54:
1702 ; CHECK: # %bb.0:
1703 ; CHECK-NEXT: xxpermdi v2, v2, v3, 2
1704 ; CHECK-NEXT: blr
1705 ;
1706 ; CHECK-REG-LABEL: test54:
1707 ; CHECK-REG: # %bb.0:
1708 ; CHECK-REG-NEXT: xxpermdi v2, v2, v3, 2
1709 ; CHECK-REG-NEXT: blr
1710 ;
1711 ; CHECK-FISL-LABEL: test54:
1712 ; CHECK-FISL: # %bb.0:
1713 ; CHECK-FISL-NEXT: xxpermdi v2, v2, v3, 2
1714 ; CHECK-FISL-NEXT: blr
1715 ;
1716 ; CHECK-LE-LABEL: test54:
1717 ; CHECK-LE: # %bb.0:
1718 ; CHECK-LE-NEXT: xxpermdi v2, v3, v2, 2
1719 ; CHECK-LE-NEXT: blr
1720 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
1721 ret <2 x double> %v
1724 }
1726 define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
1727 ; CHECK-LABEL: test55:
1728 ; CHECK: # %bb.0:
1729 ; CHECK-NEXT: xxmrgld v2, v2, v3
1730 ; CHECK-NEXT: blr
1731 ;
1732 ; CHECK-REG-LABEL: test55:
1733 ; CHECK-REG: # %bb.0:
1734 ; CHECK-REG-NEXT: xxmrgld v2, v2, v3
1735 ; CHECK-REG-NEXT: blr
1736 ;
1737 ; CHECK-FISL-LABEL: test55:
1738 ; CHECK-FISL: # %bb.0:
1739 ; CHECK-FISL-NEXT: xxmrgld v2, v2, v3
1740 ; CHECK-FISL-NEXT: blr
1741 ;
1742 ; CHECK-LE-LABEL: test55:
1743 ; CHECK-LE: # %bb.0:
1744 ; CHECK-LE-NEXT: xxmrghd v2, v3, v2
1745 ; CHECK-LE-NEXT: blr
1746 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
1747 ret <2 x double> %v
1750 }
1752 define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
1753 ; CHECK-LABEL: test56:
1754 ; CHECK: # %bb.0:
1755 ; CHECK-NEXT: xxmrgld v2, v2, v3
1756 ; CHECK-NEXT: blr
1757 ;
1758 ; CHECK-REG-LABEL: test56:
1759 ; CHECK-REG: # %bb.0:
1760 ; CHECK-REG-NEXT: xxmrgld v2, v2, v3
1761 ; CHECK-REG-NEXT: blr
1762 ;
1763 ; CHECK-FISL-LABEL: test56:
1764 ; CHECK-FISL: # %bb.0:
1765 ; CHECK-FISL-NEXT: xxmrgld v2, v2, v3
1766 ; CHECK-FISL-NEXT: blr
1767 ;
1768 ; CHECK-LE-LABEL: test56:
1769 ; CHECK-LE: # %bb.0:
1770 ; CHECK-LE-NEXT: xxmrghd v2, v3, v2
1771 ; CHECK-LE-NEXT: blr
1772 %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
1773 ret <2 x i64> %v
1776 }
1778 define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
1779 ; CHECK-LABEL: test60:
1780 ; CHECK: # %bb.0:
1781 ; CHECK-NEXT: addi r3, r1, -32
1782 ; CHECK-NEXT: addi r4, r1, -48
1783 ; CHECK-NEXT: stxvd2x v3, 0, r3
1784 ; CHECK-NEXT: stxvd2x v2, 0, r4
1785 ; CHECK-NEXT: lwz r3, -20(r1)
1786 ; CHECK-NEXT: ld r4, -40(r1)
1787 ; CHECK-NEXT: sld r3, r4, r3
1788 ; CHECK-NEXT: ld r4, -48(r1)
1789 ; CHECK-NEXT: std r3, -8(r1)
1790 ; CHECK-NEXT: lwz r3, -28(r1)
1791 ; CHECK-NEXT: sld r3, r4, r3
1792 ; CHECK-NEXT: std r3, -16(r1)
1793 ; CHECK-NEXT: addi r3, r1, -16
1794 ; CHECK-NEXT: lxvd2x v2, 0, r3
1795 ; CHECK-NEXT: blr
1796 ;
1797 ; CHECK-REG-LABEL: test60:
1798 ; CHECK-REG: # %bb.0:
1799 ; CHECK-REG-NEXT: addi r3, r1, -32
1800 ; CHECK-REG-NEXT: addi r4, r1, -48
1801 ; CHECK-REG-NEXT: stxvd2x v3, 0, r3
1802 ; CHECK-REG-NEXT: stxvd2x v2, 0, r4
1803 ; CHECK-REG-NEXT: lwz r3, -20(r1)
1804 ; CHECK-REG-NEXT: ld r4, -40(r1)
1805 ; CHECK-REG-NEXT: sld r3, r4, r3
1806 ; CHECK-REG-NEXT: ld r4, -48(r1)
1807 ; CHECK-REG-NEXT: std r3, -8(r1)
1808 ; CHECK-REG-NEXT: lwz r3, -28(r1)
1809 ; CHECK-REG-NEXT: sld r3, r4, r3
1810 ; CHECK-REG-NEXT: std r3, -16(r1)
1811 ; CHECK-REG-NEXT: addi r3, r1, -16
1812 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
1813 ; CHECK-REG-NEXT: blr
1814 ;
1815 ; CHECK-FISL-LABEL: test60:
1816 ; CHECK-FISL: # %bb.0:
1817 ; CHECK-FISL-NEXT: addi r3, r1, -32
1818 ; CHECK-FISL-NEXT: stxvd2x v3, 0, r3
1819 ; CHECK-FISL-NEXT: addi r3, r1, -48
1820 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
1821 ; CHECK-FISL-NEXT: lwz r4, -20(r1)
1822 ; CHECK-FISL-NEXT: ld r3, -40(r1)
1823 ; CHECK-FISL-NEXT: sld r3, r3, r4
1824 ; CHECK-FISL-NEXT: std r3, -8(r1)
1825 ; CHECK-FISL-NEXT: lwz r4, -28(r1)
1826 ; CHECK-FISL-NEXT: ld r3, -48(r1)
1827 ; CHECK-FISL-NEXT: sld r3, r3, r4
1828 ; CHECK-FISL-NEXT: std r3, -16(r1)
1829 ; CHECK-FISL-NEXT: addi r3, r1, -16
1830 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
1831 ; CHECK-FISL-NEXT: blr
1832 ;
1833 ; CHECK-LE-LABEL: test60:
1834 ; CHECK-LE: # %bb.0:
1835 ; CHECK-LE-NEXT: vsld v2, v2, v3
1836 ; CHECK-LE-NEXT: blr
1837 %v = shl <2 x i64> %a, %b
1838 ret <2 x i64> %v
1840 ; This should scalarize, and the current code quality is not good.
1841 }
1843 define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
1844 ; CHECK-LABEL: test61:
1845 ; CHECK: # %bb.0:
1846 ; CHECK-NEXT: addi r3, r1, -32
1847 ; CHECK-NEXT: addi r4, r1, -48
1848 ; CHECK-NEXT: stxvd2x v3, 0, r3
1849 ; CHECK-NEXT: stxvd2x v2, 0, r4
1850 ; CHECK-NEXT: lwz r3, -20(r1)
1851 ; CHECK-NEXT: ld r4, -40(r1)
1852 ; CHECK-NEXT: srd r3, r4, r3
1853 ; CHECK-NEXT: ld r4, -48(r1)
1854 ; CHECK-NEXT: std r3, -8(r1)
1855 ; CHECK-NEXT: lwz r3, -28(r1)
1856 ; CHECK-NEXT: srd r3, r4, r3
1857 ; CHECK-NEXT: std r3, -16(r1)
1858 ; CHECK-NEXT: addi r3, r1, -16
1859 ; CHECK-NEXT: lxvd2x v2, 0, r3
1860 ; CHECK-NEXT: blr
1861 ;
1862 ; CHECK-REG-LABEL: test61:
1863 ; CHECK-REG: # %bb.0:
1864 ; CHECK-REG-NEXT: addi r3, r1, -32
1865 ; CHECK-REG-NEXT: addi r4, r1, -48
1866 ; CHECK-REG-NEXT: stxvd2x v3, 0, r3
1867 ; CHECK-REG-NEXT: stxvd2x v2, 0, r4
1868 ; CHECK-REG-NEXT: lwz r3, -20(r1)
1869 ; CHECK-REG-NEXT: ld r4, -40(r1)
1870 ; CHECK-REG-NEXT: srd r3, r4, r3
1871 ; CHECK-REG-NEXT: ld r4, -48(r1)
1872 ; CHECK-REG-NEXT: std r3, -8(r1)
1873 ; CHECK-REG-NEXT: lwz r3, -28(r1)
1874 ; CHECK-REG-NEXT: srd r3, r4, r3
1875 ; CHECK-REG-NEXT: std r3, -16(r1)
1876 ; CHECK-REG-NEXT: addi r3, r1, -16
1877 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
1878 ; CHECK-REG-NEXT: blr
1879 ;
1880 ; CHECK-FISL-LABEL: test61:
1881 ; CHECK-FISL: # %bb.0:
1882 ; CHECK-FISL-NEXT: addi r3, r1, -32
1883 ; CHECK-FISL-NEXT: stxvd2x v3, 0, r3
1884 ; CHECK-FISL-NEXT: addi r3, r1, -48
1885 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
1886 ; CHECK-FISL-NEXT: lwz r4, -20(r1)
1887 ; CHECK-FISL-NEXT: ld r3, -40(r1)
1888 ; CHECK-FISL-NEXT: srd r3, r3, r4
1889 ; CHECK-FISL-NEXT: std r3, -8(r1)
1890 ; CHECK-FISL-NEXT: lwz r4, -28(r1)
1891 ; CHECK-FISL-NEXT: ld r3, -48(r1)
1892 ; CHECK-FISL-NEXT: srd r3, r3, r4
1893 ; CHECK-FISL-NEXT: std r3, -16(r1)
1894 ; CHECK-FISL-NEXT: addi r3, r1, -16
1895 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
1896 ; CHECK-FISL-NEXT: blr
1897 ;
1898 ; CHECK-LE-LABEL: test61:
1899 ; CHECK-LE: # %bb.0:
1900 ; CHECK-LE-NEXT: vsrd v2, v2, v3
1901 ; CHECK-LE-NEXT: blr
1902 %v = lshr <2 x i64> %a, %b
1903 ret <2 x i64> %v
1905 ; This should scalarize, and the current code quality is not good.
1906 }
1908 define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
1909 ; CHECK-LABEL: test62:
1910 ; CHECK: # %bb.0:
1911 ; CHECK-NEXT: addi r3, r1, -32
1912 ; CHECK-NEXT: addi r4, r1, -48
1913 ; CHECK-NEXT: stxvd2x v3, 0, r3
1914 ; CHECK-NEXT: stxvd2x v2, 0, r4
1915 ; CHECK-NEXT: lwz r3, -20(r1)
1916 ; CHECK-NEXT: ld r4, -40(r1)
1917 ; CHECK-NEXT: srad r3, r4, r3
1918 ; CHECK-NEXT: ld r4, -48(r1)
1919 ; CHECK-NEXT: std r3, -8(r1)
1920 ; CHECK-NEXT: lwz r3, -28(r1)
1921 ; CHECK-NEXT: srad r3, r4, r3
1922 ; CHECK-NEXT: std r3, -16(r1)
1923 ; CHECK-NEXT: addi r3, r1, -16
1924 ; CHECK-NEXT: lxvd2x v2, 0, r3
1925 ; CHECK-NEXT: blr
1926 ;
1927 ; CHECK-REG-LABEL: test62:
1928 ; CHECK-REG: # %bb.0:
1929 ; CHECK-REG-NEXT: addi r3, r1, -32
1930 ; CHECK-REG-NEXT: addi r4, r1, -48
1931 ; CHECK-REG-NEXT: stxvd2x v3, 0, r3
1932 ; CHECK-REG-NEXT: stxvd2x v2, 0, r4
1933 ; CHECK-REG-NEXT: lwz r3, -20(r1)
1934 ; CHECK-REG-NEXT: ld r4, -40(r1)
1935 ; CHECK-REG-NEXT: srad r3, r4, r3
1936 ; CHECK-REG-NEXT: ld r4, -48(r1)
1937 ; CHECK-REG-NEXT: std r3, -8(r1)
1938 ; CHECK-REG-NEXT: lwz r3, -28(r1)
1939 ; CHECK-REG-NEXT: srad r3, r4, r3
1940 ; CHECK-REG-NEXT: std r3, -16(r1)
1941 ; CHECK-REG-NEXT: addi r3, r1, -16
1942 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
1943 ; CHECK-REG-NEXT: blr
1944 ;
1945 ; CHECK-FISL-LABEL: test62:
1946 ; CHECK-FISL: # %bb.0:
1947 ; CHECK-FISL-NEXT: addi r3, r1, -32
1948 ; CHECK-FISL-NEXT: stxvd2x v3, 0, r3
1949 ; CHECK-FISL-NEXT: addi r3, r1, -48
1950 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
1951 ; CHECK-FISL-NEXT: lwz r4, -20(r1)
1952 ; CHECK-FISL-NEXT: ld r3, -40(r1)
1953 ; CHECK-FISL-NEXT: srad r3, r3, r4
1954 ; CHECK-FISL-NEXT: std r3, -8(r1)
1955 ; CHECK-FISL-NEXT: lwz r4, -28(r1)
1956 ; CHECK-FISL-NEXT: ld r3, -48(r1)
1957 ; CHECK-FISL-NEXT: srad r3, r3, r4
1958 ; CHECK-FISL-NEXT: std r3, -16(r1)
1959 ; CHECK-FISL-NEXT: addi r3, r1, -16
1960 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
1961 ; CHECK-FISL-NEXT: blr
1962 ;
1963 ; CHECK-LE-LABEL: test62:
1964 ; CHECK-LE: # %bb.0:
1965 ; CHECK-LE-NEXT: vsrad v2, v2, v3
1966 ; CHECK-LE-NEXT: blr
1967 %v = ashr <2 x i64> %a, %b
1968 ret <2 x i64> %v
1970 ; This should scalarize, and the current code quality is not good.
1971 }
1973 define double @test63(<2 x double> %a) {
1974 ; CHECK-LABEL: test63:
1975 ; CHECK: # %bb.0:
1976 ; CHECK-NEXT: xxlor f1, v2, v2
1977 ; CHECK-NEXT: blr
1978 ;
1979 ; CHECK-REG-LABEL: test63:
1980 ; CHECK-REG: # %bb.0:
1981 ; CHECK-REG-NEXT: xxlor f1, v2, v2
1982 ; CHECK-REG-NEXT: blr
1983 ;
1984 ; CHECK-FISL-LABEL: test63:
1985 ; CHECK-FISL: # %bb.0:
1986 ; CHECK-FISL-NEXT: xxlor f1, v2, v2
1987 ; CHECK-FISL-NEXT: blr
1988 ;
1989 ; CHECK-LE-LABEL: test63:
1990 ; CHECK-LE: # %bb.0:
1991 ; CHECK-LE-NEXT: xxswapd vs1, v2
1992 ; CHECK-LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1
1993 ; CHECK-LE-NEXT: blr
1994 %v = extractelement <2 x double> %a, i32 0
1995 ret double %v
1999 }
2001 define double @test64(<2 x double> %a) {
2002 ; CHECK-LABEL: test64:
2003 ; CHECK: # %bb.0:
2004 ; CHECK-NEXT: xxswapd vs1, v2
2005 ; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
2006 ; CHECK-NEXT: blr
2007 ;
2008 ; CHECK-REG-LABEL: test64:
2009 ; CHECK-REG: # %bb.0:
2010 ; CHECK-REG-NEXT: xxswapd vs1, v2
2011 ; CHECK-REG-NEXT: # kill: def $f1 killed $f1 killed $vsl1
2012 ; CHECK-REG-NEXT: blr
2013 ;
2014 ; CHECK-FISL-LABEL: test64:
2015 ; CHECK-FISL: # %bb.0:
2016 ; CHECK-FISL-NEXT: xxswapd vs0, v2
2017 ; CHECK-FISL-NEXT: fmr f1, f0
2018 ; CHECK-FISL-NEXT: blr
2019 ;
2020 ; CHECK-LE-LABEL: test64:
2021 ; CHECK-LE: # %bb.0:
2022 ; CHECK-LE-NEXT: xxlor f1, v2, v2
2023 ; CHECK-LE-NEXT: blr
2024 %v = extractelement <2 x double> %a, i32 1
2025 ret double %v
2029 }
2031 define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
2032 ; CHECK-LABEL: test65:
2033 ; CHECK: # %bb.0:
2034 ; CHECK-NEXT: vcmpequw v2, v2, v3
2035 ; CHECK-NEXT: blr
2036 ;
2037 ; CHECK-REG-LABEL: test65:
2038 ; CHECK-REG: # %bb.0:
2039 ; CHECK-REG-NEXT: vcmpequw v2, v2, v3
2040 ; CHECK-REG-NEXT: blr
2041 ;
2042 ; CHECK-FISL-LABEL: test65:
2043 ; CHECK-FISL: # %bb.0:
2044 ; CHECK-FISL-NEXT: vcmpequw v2, v2, v3
2045 ; CHECK-FISL-NEXT: blr
2046 ;
2047 ; CHECK-LE-LABEL: test65:
2048 ; CHECK-LE: # %bb.0:
2049 ; CHECK-LE-NEXT: vcmpequd v2, v2, v3
2050 ; CHECK-LE-NEXT: blr
2051 %w = icmp eq <2 x i64> %a, %b
2052 ret <2 x i1> %w
2056 }
2058 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
2059 ; CHECK-LABEL: test66:
2060 ; CHECK: # %bb.0:
2061 ; CHECK-NEXT: vcmpequw v2, v2, v3
2062 ; CHECK-NEXT: xxlnor v2, v2, v2
2063 ; CHECK-NEXT: blr
2064 ;
2065 ; CHECK-REG-LABEL: test66:
2066 ; CHECK-REG: # %bb.0:
2067 ; CHECK-REG-NEXT: vcmpequw v2, v2, v3
2068 ; CHECK-REG-NEXT: xxlnor v2, v2, v2
2069 ; CHECK-REG-NEXT: blr
2070 ;
2071 ; CHECK-FISL-LABEL: test66:
2072 ; CHECK-FISL: # %bb.0:
2073 ; CHECK-FISL-NEXT: vcmpequw v2, v2, v3
2074 ; CHECK-FISL-NEXT: xxlnor v2, v2, v2
2075 ; CHECK-FISL-NEXT: blr
2076 ;
2077 ; CHECK-LE-LABEL: test66:
2078 ; CHECK-LE: # %bb.0:
2079 ; CHECK-LE-NEXT: vcmpequd v2, v2, v3
2080 ; CHECK-LE-NEXT: xxlnor v2, v2, v2
2081 ; CHECK-LE-NEXT: blr
2082 %w = icmp ne <2 x i64> %a, %b
2083 ret <2 x i1> %w
2087 }
2089 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
2090 ; CHECK-LABEL: test67:
2091 ; CHECK: # %bb.0:
2092 ; CHECK-NEXT: addi r3, r1, -32
2093 ; CHECK-NEXT: addi r4, r1, -48
2094 ; CHECK-NEXT: stxvd2x v3, 0, r3
2095 ; CHECK-NEXT: stxvd2x v2, 0, r4
2096 ; CHECK-NEXT: ld r3, -24(r1)
2097 ; CHECK-NEXT: ld r4, -40(r1)
2098 ; CHECK-NEXT: ld r6, -48(r1)
2099 ; CHECK-NEXT: cmpld r4, r3
2100 ; CHECK-NEXT: li r3, 0
2101 ; CHECK-NEXT: li r4, -1
2102 ; CHECK-NEXT: isellt r5, r4, r3
2103 ; CHECK-NEXT: std r5, -8(r1)
2104 ; CHECK-NEXT: ld r5, -32(r1)
2105 ; CHECK-NEXT: cmpld r6, r5
2106 ; CHECK-NEXT: isellt r3, r4, r3
2107 ; CHECK-NEXT: std r3, -16(r1)
2108 ; CHECK-NEXT: addi r3, r1, -16
2109 ; CHECK-NEXT: lxvd2x v2, 0, r3
2110 ; CHECK-NEXT: blr
2111 ;
2112 ; CHECK-REG-LABEL: test67:
2113 ; CHECK-REG: # %bb.0:
2114 ; CHECK-REG-NEXT: addi r3, r1, -32
2115 ; CHECK-REG-NEXT: addi r4, r1, -48
2116 ; CHECK-REG-NEXT: stxvd2x v3, 0, r3
2117 ; CHECK-REG-NEXT: stxvd2x v2, 0, r4
2118 ; CHECK-REG-NEXT: ld r3, -24(r1)
2119 ; CHECK-REG-NEXT: ld r4, -40(r1)
2120 ; CHECK-REG-NEXT: ld r6, -48(r1)
2121 ; CHECK-REG-NEXT: cmpld r4, r3
2122 ; CHECK-REG-NEXT: li r3, 0
2123 ; CHECK-REG-NEXT: li r4, -1
2124 ; CHECK-REG-NEXT: isellt r5, r4, r3
2125 ; CHECK-REG-NEXT: std r5, -8(r1)
2126 ; CHECK-REG-NEXT: ld r5, -32(r1)
2127 ; CHECK-REG-NEXT: cmpld r6, r5
2128 ; CHECK-REG-NEXT: isellt r3, r4, r3
2129 ; CHECK-REG-NEXT: std r3, -16(r1)
2130 ; CHECK-REG-NEXT: addi r3, r1, -16
2131 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
2132 ; CHECK-REG-NEXT: blr
2133 ;
2134 ; CHECK-FISL-LABEL: test67:
2135 ; CHECK-FISL: # %bb.0:
2136 ; CHECK-FISL-NEXT: addi r3, r1, -32
2137 ; CHECK-FISL-NEXT: stxvd2x v3, 0, r3
2138 ; CHECK-FISL-NEXT: addi r3, r1, -48
2139 ; CHECK-FISL-NEXT: stxvd2x v2, 0, r3
2140 ; CHECK-FISL-NEXT: ld r4, -24(r1)
2141 ; CHECK-FISL-NEXT: ld r3, -40(r1)
2142 ; CHECK-FISL-NEXT: cmpld r3, r4
2143 ; CHECK-FISL-NEXT: li r4, 0
2144 ; CHECK-FISL-NEXT: li r3, -1
2145 ; CHECK-FISL-NEXT: isellt r5, r3, r4
2146 ; CHECK-FISL-NEXT: std r5, -8(r1)
2147 ; CHECK-FISL-NEXT: ld r6, -32(r1)
2148 ; CHECK-FISL-NEXT: ld r5, -48(r1)
2149 ; CHECK-FISL-NEXT: cmpld r5, r6
2150 ; CHECK-FISL-NEXT: isellt r3, r3, r4
2151 ; CHECK-FISL-NEXT: std r3, -16(r1)
2152 ; CHECK-FISL-NEXT: addi r3, r1, -16
2153 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
2154 ; CHECK-FISL-NEXT: blr
2155 ;
2156 ; CHECK-LE-LABEL: test67:
2157 ; CHECK-LE: # %bb.0:
2158 ; CHECK-LE-NEXT: vcmpgtud v2, v3, v2
2159 ; CHECK-LE-NEXT: blr
2160 %w = icmp ult <2 x i64> %a, %b
2161 ret <2 x i1> %w
2163 ; This should scalarize, and the current code quality is not good.
2165 }
2167 define <2 x double> @test68(<2 x i32> %a) {
2168 ; CHECK-LABEL: test68:
2169 ; CHECK: # %bb.0:
2170 ; CHECK-NEXT: xxmrghw vs0, v2, v2
2171 ; CHECK-NEXT: xvcvsxwdp v2, vs0
2172 ; CHECK-NEXT: blr
2173 ;
2174 ; CHECK-REG-LABEL: test68:
2175 ; CHECK-REG: # %bb.0:
2176 ; CHECK-REG-NEXT: xxmrghw vs0, v2, v2
2177 ; CHECK-REG-NEXT: xvcvsxwdp v2, vs0
2178 ; CHECK-REG-NEXT: blr
2179 ;
2180 ; CHECK-FISL-LABEL: test68:
2181 ; CHECK-FISL: # %bb.0:
2182 ; CHECK-FISL-NEXT: xxmrghw vs0, v2, v2
2183 ; CHECK-FISL-NEXT: xvcvsxwdp v2, vs0
2184 ; CHECK-FISL-NEXT: blr
2185 ;
2186 ; CHECK-LE-LABEL: test68:
2187 ; CHECK-LE: # %bb.0:
2188 ; CHECK-LE-NEXT: xxmrglw v2, v2, v2
2189 ; CHECK-LE-NEXT: xvcvsxwdp v2, v2
2190 ; CHECK-LE-NEXT: blr
2191 %w = sitofp <2 x i32> %a to <2 x double>
2192 ret <2 x double> %w
2195 }
2197 ; This gets scalarized so the code isn't great
2198 define <2 x double> @test69(<2 x i16> %a) {
2199 ; CHECK-LABEL: test69:
2200 ; CHECK: # %bb.0:
2201 ; CHECK-NEXT: addis r3, r2, .LCPI63_0@toc@ha
2202 ; CHECK-NEXT: addi r3, r3, .LCPI63_0@toc@l
2203 ; CHECK-NEXT: lxvw4x v3, 0, r3
2204 ; CHECK-NEXT: addi r3, r1, -32
2205 ; CHECK-NEXT: vperm v2, v2, v2, v3
2206 ; CHECK-NEXT: stxvd2x v2, 0, r3
2207 ; CHECK-NEXT: lha r3, -18(r1)
2208 ; CHECK-NEXT: std r3, -8(r1)
2209 ; CHECK-NEXT: lha r3, -26(r1)
2210 ; CHECK-NEXT: std r3, -16(r1)
2211 ; CHECK-NEXT: addi r3, r1, -16
2212 ; CHECK-NEXT: lxvd2x v2, 0, r3
2213 ; CHECK-NEXT: xvcvsxddp v2, v2
2214 ; CHECK-NEXT: blr
2215 ;
2216 ; CHECK-REG-LABEL: test69:
2217 ; CHECK-REG: # %bb.0:
2218 ; CHECK-REG-NEXT: addis r3, r2, .LCPI63_0@toc@ha
2219 ; CHECK-REG-NEXT: addi r3, r3, .LCPI63_0@toc@l
2220 ; CHECK-REG-NEXT: lxvw4x v3, 0, r3
2221 ; CHECK-REG-NEXT: addi r3, r1, -32
2222 ; CHECK-REG-NEXT: vperm v2, v2, v2, v3
2223 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
2224 ; CHECK-REG-NEXT: lha r3, -18(r1)
2225 ; CHECK-REG-NEXT: std r3, -8(r1)
2226 ; CHECK-REG-NEXT: lha r3, -26(r1)
2227 ; CHECK-REG-NEXT: std r3, -16(r1)
2228 ; CHECK-REG-NEXT: addi r3, r1, -16
2229 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
2230 ; CHECK-REG-NEXT: xvcvsxddp v2, v2
2231 ; CHECK-REG-NEXT: blr
2232 ;
2233 ; CHECK-FISL-LABEL: test69:
2234 ; CHECK-FISL: # %bb.0:
2235 ; CHECK-FISL-NEXT: addis r3, r2, .LCPI63_0@toc@ha
2236 ; CHECK-FISL-NEXT: addi r3, r3, .LCPI63_0@toc@l
2237 ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3
2238 ; CHECK-FISL-NEXT: vperm v2, v2, v2, v3
2239 ; CHECK-FISL-NEXT: xxlor vs0, v2, v2
2240 ; CHECK-FISL-NEXT: addi r3, r1, -32
2241 ; CHECK-FISL-NEXT: stxvd2x vs0, 0, r3
2242 ; CHECK-FISL-NEXT: lha r3, -18(r1)
2243 ; CHECK-FISL-NEXT: std r3, -8(r1)
2244 ; CHECK-FISL-NEXT: lha r3, -26(r1)
2245 ; CHECK-FISL-NEXT: std r3, -16(r1)
2246 ; CHECK-FISL-NEXT: addi r3, r1, -16
2247 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
2248 ; CHECK-FISL-NEXT: xvcvsxddp v2, v2
2249 ; CHECK-FISL-NEXT: blr
2250 ;
2251 ; CHECK-LE-LABEL: test69:
2252 ; CHECK-LE: # %bb.0:
2253 ; CHECK-LE-NEXT: addis r3, r2, .LCPI63_0@toc@ha
2254 ; CHECK-LE-NEXT: addi r3, r3, .LCPI63_0@toc@l
2255 ; CHECK-LE-NEXT: lvx v3, 0, r3
2256 ; CHECK-LE-NEXT: addis r3, r2, .LCPI63_1@toc@ha
2257 ; CHECK-LE-NEXT: addi r3, r3, .LCPI63_1@toc@l
2258 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
2259 ; CHECK-LE-NEXT: vperm v2, v2, v2, v3
2260 ; CHECK-LE-NEXT: xxswapd v3, vs0
2261 ; CHECK-LE-NEXT: vsld v2, v2, v3
2262 ; CHECK-LE-NEXT: vsrad v2, v2, v3
2263 ; CHECK-LE-NEXT: xvcvsxddp v2, v2
2264 ; CHECK-LE-NEXT: blr
2265 %w = sitofp <2 x i16> %a to <2 x double>
2266 ret <2 x double> %w
2269 }
2271 ; This gets scalarized so the code isn't great
2272 define <2 x double> @test70(<2 x i8> %a) {
2273 ; CHECK-LABEL: test70:
2274 ; CHECK: # %bb.0:
2275 ; CHECK-NEXT: addis r3, r2, .LCPI64_0@toc@ha
2276 ; CHECK-NEXT: addi r3, r3, .LCPI64_0@toc@l
2277 ; CHECK-NEXT: lxvw4x v3, 0, r3
2278 ; CHECK-NEXT: addi r3, r1, -32
2279 ; CHECK-NEXT: vperm v2, v2, v2, v3
2280 ; CHECK-NEXT: stxvd2x v2, 0, r3
2281 ; CHECK-NEXT: ld r3, -24(r1)
2282 ; CHECK-NEXT: extsb r3, r3
2283 ; CHECK-NEXT: std r3, -8(r1)
2284 ; CHECK-NEXT: ld r3, -32(r1)
2285 ; CHECK-NEXT: extsb r3, r3
2286 ; CHECK-NEXT: std r3, -16(r1)
2287 ; CHECK-NEXT: addi r3, r1, -16
2288 ; CHECK-NEXT: lxvd2x v2, 0, r3
2289 ; CHECK-NEXT: xvcvsxddp v2, v2
2290 ; CHECK-NEXT: blr
2291 ;
2292 ; CHECK-REG-LABEL: test70:
2293 ; CHECK-REG: # %bb.0:
2294 ; CHECK-REG-NEXT: addis r3, r2, .LCPI64_0@toc@ha
2295 ; CHECK-REG-NEXT: addi r3, r3, .LCPI64_0@toc@l
2296 ; CHECK-REG-NEXT: lxvw4x v3, 0, r3
2297 ; CHECK-REG-NEXT: addi r3, r1, -32
2298 ; CHECK-REG-NEXT: vperm v2, v2, v2, v3
2299 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
2300 ; CHECK-REG-NEXT: ld r3, -24(r1)
2301 ; CHECK-REG-NEXT: extsb r3, r3
2302 ; CHECK-REG-NEXT: std r3, -8(r1)
2303 ; CHECK-REG-NEXT: ld r3, -32(r1)
2304 ; CHECK-REG-NEXT: extsb r3, r3
2305 ; CHECK-REG-NEXT: std r3, -16(r1)
2306 ; CHECK-REG-NEXT: addi r3, r1, -16
2307 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
2308 ; CHECK-REG-NEXT: xvcvsxddp v2, v2
2309 ; CHECK-REG-NEXT: blr
2310 ;
2311 ; CHECK-FISL-LABEL: test70:
2312 ; CHECK-FISL: # %bb.0:
2313 ; CHECK-FISL-NEXT: addis r3, r2, .LCPI64_0@toc@ha
2314 ; CHECK-FISL-NEXT: addi r3, r3, .LCPI64_0@toc@l
2315 ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3
2316 ; CHECK-FISL-NEXT: vperm v2, v2, v2, v3
2317 ; CHECK-FISL-NEXT: xxlor vs0, v2, v2
2318 ; CHECK-FISL-NEXT: addi r3, r1, -32
2319 ; CHECK-FISL-NEXT: stxvd2x vs0, 0, r3
2320 ; CHECK-FISL-NEXT: ld r3, -24(r1)
2321 ; CHECK-FISL-NEXT: extsb r3, r3
2322 ; CHECK-FISL-NEXT: std r3, -8(r1)
2323 ; CHECK-FISL-NEXT: ld r3, -32(r1)
2324 ; CHECK-FISL-NEXT: extsb r3, r3
2325 ; CHECK-FISL-NEXT: std r3, -16(r1)
2326 ; CHECK-FISL-NEXT: addi r3, r1, -16
2327 ; CHECK-FISL-NEXT: lxvd2x v2, 0, r3
2328 ; CHECK-FISL-NEXT: xvcvsxddp v2, v2
2329 ; CHECK-FISL-NEXT: blr
2330 ;
2331 ; CHECK-LE-LABEL: test70:
2332 ; CHECK-LE: # %bb.0:
2333 ; CHECK-LE-NEXT: addis r3, r2, .LCPI64_0@toc@ha
2334 ; CHECK-LE-NEXT: addi r3, r3, .LCPI64_0@toc@l
2335 ; CHECK-LE-NEXT: lvx v3, 0, r3
2336 ; CHECK-LE-NEXT: addis r3, r2, .LCPI64_1@toc@ha
2337 ; CHECK-LE-NEXT: addi r3, r3, .LCPI64_1@toc@l
2338 ; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
2339 ; CHECK-LE-NEXT: vperm v2, v2, v2, v3
2340 ; CHECK-LE-NEXT: xxswapd v3, vs0
2341 ; CHECK-LE-NEXT: vsld v2, v2, v3
2342 ; CHECK-LE-NEXT: vsrad v2, v2, v3
2343 ; CHECK-LE-NEXT: xvcvsxddp v2, v2
2344 ; CHECK-LE-NEXT: blr
2345 %w = sitofp <2 x i8> %a to <2 x double>
2346 ret <2 x double> %w
2349 }
2351 ; This gets scalarized so the code isn't great
2352 define <2 x i32> @test80(i32 %v) {
2353 ; CHECK-LABEL: test80:
2354 ; CHECK: # %bb.0:
2355 ; CHECK-NEXT: addi r4, r1, -16
2356 ; CHECK-NEXT: stw r3, -16(r1)
2357 ; CHECK-NEXT: addis r3, r2, .LCPI65_0@toc@ha
2358 ; CHECK-NEXT: lxvw4x vs0, 0, r4
2359 ; CHECK-NEXT: addi r3, r3, .LCPI65_0@toc@l
2360 ; CHECK-NEXT: lxvw4x v3, 0, r3
2361 ; CHECK-NEXT: xxspltw v2, vs0, 0
2362 ; CHECK-NEXT: vadduwm v2, v2, v3
2363 ; CHECK-NEXT: blr
2364 ;
2365 ; CHECK-REG-LABEL: test80:
2366 ; CHECK-REG: # %bb.0:
2367 ; CHECK-REG-NEXT: addi r4, r1, -16
2368 ; CHECK-REG-NEXT: stw r3, -16(r1)
2369 ; CHECK-REG-NEXT: addis r3, r2, .LCPI65_0@toc@ha
2370 ; CHECK-REG-NEXT: lxvw4x vs0, 0, r4
2371 ; CHECK-REG-NEXT: addi r3, r3, .LCPI65_0@toc@l
2372 ; CHECK-REG-NEXT: lxvw4x v3, 0, r3
2373 ; CHECK-REG-NEXT: xxspltw v2, vs0, 0
2374 ; CHECK-REG-NEXT: vadduwm v2, v2, v3
2375 ; CHECK-REG-NEXT: blr
2376 ;
2377 ; CHECK-FISL-LABEL: test80:
2378 ; CHECK-FISL: # %bb.0:
2379 ; CHECK-FISL-NEXT: # kill: def $r3 killed $r3 killed $x3
2380 ; CHECK-FISL-NEXT: stw r3, -16(r1)
2381 ; CHECK-FISL-NEXT: addi r3, r1, -16
2382 ; CHECK-FISL-NEXT: lxvw4x vs0, 0, r3
2383 ; CHECK-FISL-NEXT: xxspltw v2, vs0, 0
2384 ; CHECK-FISL-NEXT: addis r3, r2, .LCPI65_0@toc@ha
2385 ; CHECK-FISL-NEXT: addi r3, r3, .LCPI65_0@toc@l
2386 ; CHECK-FISL-NEXT: lxvw4x v3, 0, r3
2387 ; CHECK-FISL-NEXT: vadduwm v2, v2, v3
2388 ; CHECK-FISL-NEXT: blr
2389 ;
2390 ; CHECK-LE-LABEL: test80:
2391 ; CHECK-LE: # %bb.0:
2392 ; CHECK-LE-NEXT: mtfprwz f0, r3
2393 ; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha
2394 ; CHECK-LE-NEXT: addi r3, r4, .LCPI65_0@toc@l
2395 ; CHECK-LE-NEXT: xxspltw v2, vs0, 1
2396 ; CHECK-LE-NEXT: lvx v3, 0, r3
2397 ; CHECK-LE-NEXT: vadduwm v2, v2, v3
2398 ; CHECK-LE-NEXT: blr
2399 %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
2400 %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
2401 %i = add <2 x i32> %b2, <i32 2, i32 3>
2402 ret <2 x i32> %i
2406 }
2408 define <2 x double> @test81(<4 x float> %b) {
2409 ; CHECK-LABEL: test81:
2410 ; CHECK: # %bb.0:
2411 ; CHECK-NEXT: blr
2412 ;
2413 ; CHECK-REG-LABEL: test81:
2414 ; CHECK-REG: # %bb.0:
2415 ; CHECK-REG-NEXT: blr
2416 ;
2417 ; CHECK-FISL-LABEL: test81:
2418 ; CHECK-FISL: # %bb.0:
2419 ; CHECK-FISL-NEXT: blr
2420 ;
2421 ; CHECK-LE-LABEL: test81:
2422 ; CHECK-LE: # %bb.0:
2423 ; CHECK-LE-NEXT: blr
2424 %w = bitcast <4 x float> %b to <2 x double>
2425 ret <2 x double> %w
2428 }
2430 define double @test82(double %a, double %b, double %c, double %d) {
2431 ; CHECK-LABEL: test82:
2432 ; CHECK: # %bb.0: # %entry
2433 ; CHECK-NEXT: xscmpudp cr0, f3, f4
2434 ; CHECK-NEXT: beqlr cr0
2435 ; CHECK-NEXT: # %bb.1: # %entry
2436 ; CHECK-NEXT: fmr f1, f2
2437 ; CHECK-NEXT: blr
2438 ;
2439 ; CHECK-REG-LABEL: test82:
2440 ; CHECK-REG: # %bb.0: # %entry
2441 ; CHECK-REG-NEXT: xscmpudp cr0, f3, f4
2442 ; CHECK-REG-NEXT: beqlr cr0
2443 ; CHECK-REG-NEXT: # %bb.1: # %entry
2444 ; CHECK-REG-NEXT: fmr f1, f2
2445 ; CHECK-REG-NEXT: blr
2446 ;
2447 ; CHECK-FISL-LABEL: test82:
2448 ; CHECK-FISL: # %bb.0: # %entry
2449 ; CHECK-FISL-NEXT: stfd f2, -16(r1) # 8-byte Folded Spill
2450 ; CHECK-FISL-NEXT: fmr f2, f1
2451 ; CHECK-FISL-NEXT: xscmpudp cr0, f3, f4
2452 ; CHECK-FISL-NEXT: stfd f2, -8(r1) # 8-byte Folded Spill
2453 ; CHECK-FISL-NEXT: beq cr0, .LBB67_2
2454 ; CHECK-FISL-NEXT: # %bb.1: # %entry
2455 ; CHECK-FISL-NEXT: lfd f0, -16(r1) # 8-byte Folded Reload
2456 ; CHECK-FISL-NEXT: stfd f0, -8(r1) # 8-byte Folded Spill
2457 ; CHECK-FISL-NEXT: .LBB67_2: # %entry
2458 ; CHECK-FISL-NEXT: lfd f1, -8(r1) # 8-byte Folded Reload
2459 ; CHECK-FISL-NEXT: blr
2460 ;
2461 ; CHECK-LE-LABEL: test82:
2462 ; CHECK-LE: # %bb.0: # %entry
2463 ; CHECK-LE-NEXT: xscmpudp cr0, f3, f4
2464 ; CHECK-LE-NEXT: beqlr cr0
2465 ; CHECK-LE-NEXT: # %bb.1: # %entry
2466 ; CHECK-LE-NEXT: fmr f1, f2
2467 ; CHECK-LE-NEXT: blr
2468 entry:
2469 %m = fcmp oeq double %c, %d
2470 %v = select i1 %m, double %a, double %b
2471 ret double %v
2475 }