1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -filetype=obj < %s \
3 ; RUN: -o /dev/null 2>&1
4 ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs \
5 ; RUN: -filetype=obj < %s -o /dev/null 2>&1
6 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
7 ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \
10 define void @relax_bcc(i1 %a) nounwind {
11 ; CHECK-LABEL: relax_bcc:
13 ; CHECK-NEXT: andi a0, a0, 1
14 ; CHECK-NEXT: bnez a0, .LBB0_1
15 ; CHECK-NEXT: j .LBB0_2
16 ; CHECK-NEXT: .LBB0_1: # %iftrue
18 ; CHECK-NEXT: .zero 4096
20 ; CHECK-NEXT: .LBB0_2: # %tail
22 br i1 %a, label %iftrue, label %tail
25 call void asm sideeffect ".space 4096", ""()
32 define i32 @relax_jal(i1 %a) nounwind {
33 ; CHECK-LABEL: relax_jal:
35 ; CHECK-NEXT: andi a0, a0, 1
36 ; CHECK-NEXT: bnez a0, .LBB1_1
37 ; CHECK-NEXT: # %bb.3:
38 ; CHECK-NEXT: jump .LBB1_2, a0
39 ; CHECK-NEXT: .LBB1_1: # %iftrue
43 ; CHECK-NEXT: .zero 1048576
45 ; CHECK-NEXT: addi a0, zero, 1
47 ; CHECK-NEXT: .LBB1_2: # %jmp
50 ; CHECK-NEXT: addi a0, zero, 1
52 br i1 %a, label %iftrue, label %jmp
55 call void asm sideeffect "", ""()
59 call void asm sideeffect "", ""()
63 call void asm sideeffect ".space 1048576", ""()