| blob | fc09c12992f41fe962fec99b3aef47596a578001 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
3 ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh -verify-machineinstrs \
5 ; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
6 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
7 ; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh -verify-machineinstrs \
9 ; RUN: -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
11 define i16 @fcvt_si_h(half %a) nounwind {
12 ; RV32IZFH-LABEL: fcvt_si_h:
13 ; RV32IZFH: # %bb.0:
14 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
15 ; RV32IZFH-NEXT: ret
16 ;
17 ; RV32IDZFH-LABEL: fcvt_si_h:
18 ; RV32IDZFH: # %bb.0:
19 ; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
20 ; RV32IDZFH-NEXT: ret
21 ;
22 ; RV64IZFH-LABEL: fcvt_si_h:
23 ; RV64IZFH: # %bb.0:
24 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
25 ; RV64IZFH-NEXT: ret
26 ;
27 ; RV64IDZFH-LABEL: fcvt_si_h:
28 ; RV64IDZFH: # %bb.0:
29 ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
30 ; RV64IDZFH-NEXT: ret
31 %1 = fptosi half %a to i16
32 ret i16 %1
33 }
35 define i16 @fcvt_si_h_sat(half %a) nounwind {
36 ; RV32IZFH-LABEL: fcvt_si_h_sat:
37 ; RV32IZFH: # %bb.0: # %start
38 ; RV32IZFH-NEXT: fcvt.s.h ft0, fa0
39 ; RV32IZFH-NEXT: feq.s a0, ft0, ft0
40 ; RV32IZFH-NEXT: bnez a0, .LBB1_2
41 ; RV32IZFH-NEXT: # %bb.1: # %start
42 ; RV32IZFH-NEXT: mv a0, zero
43 ; RV32IZFH-NEXT: ret
44 ; RV32IZFH-NEXT: .LBB1_2:
45 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
46 ; RV32IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
47 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1)
48 ; RV32IZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
49 ; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1
50 ; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2
51 ; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
52 ; RV32IZFH-NEXT: ret
53 ;
54 ; RV32IDZFH-LABEL: fcvt_si_h_sat:
55 ; RV32IDZFH: # %bb.0: # %start
56 ; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
57 ; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
58 ; RV32IDZFH-NEXT: bnez a0, .LBB1_2
59 ; RV32IDZFH-NEXT: # %bb.1: # %start
60 ; RV32IDZFH-NEXT: mv a0, zero
61 ; RV32IDZFH-NEXT: ret
62 ; RV32IDZFH-NEXT: .LBB1_2:
63 ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
64 ; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
65 ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
66 ; RV32IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
67 ; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
68 ; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
69 ; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
70 ; RV32IDZFH-NEXT: ret
71 ;
72 ; RV64IZFH-LABEL: fcvt_si_h_sat:
73 ; RV64IZFH: # %bb.0: # %start
74 ; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
75 ; RV64IZFH-NEXT: feq.s a0, ft0, ft0
76 ; RV64IZFH-NEXT: bnez a0, .LBB1_2
77 ; RV64IZFH-NEXT: # %bb.1: # %start
78 ; RV64IZFH-NEXT: mv a0, zero
79 ; RV64IZFH-NEXT: ret
80 ; RV64IZFH-NEXT: .LBB1_2:
81 ; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
82 ; RV64IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
83 ; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_1)
84 ; RV64IZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
85 ; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1
86 ; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2
87 ; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
88 ; RV64IZFH-NEXT: ret
89 ;
90 ; RV64IDZFH-LABEL: fcvt_si_h_sat:
91 ; RV64IDZFH: # %bb.0: # %start
92 ; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
93 ; RV64IDZFH-NEXT: feq.s a0, ft0, ft0
94 ; RV64IDZFH-NEXT: bnez a0, .LBB1_2
95 ; RV64IDZFH-NEXT: # %bb.1: # %start
96 ; RV64IDZFH-NEXT: mv a0, zero
97 ; RV64IDZFH-NEXT: ret
98 ; RV64IDZFH-NEXT: .LBB1_2:
99 ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
100 ; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
101 ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
102 ; RV64IDZFH-NEXT: flw ft2, %lo(.LCPI1_1)(a0)
103 ; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1
104 ; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
105 ; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
106 ; RV64IDZFH-NEXT: ret
107 start:
108 %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
109 ret i16 %0
110 }
111 declare i16 @llvm.fptosi.sat.i16.f16(half)
113 define i16 @fcvt_ui_h(half %a) nounwind {
114 ; RV32IZFH-LABEL: fcvt_ui_h:
115 ; RV32IZFH: # %bb.0:
116 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
117 ; RV32IZFH-NEXT: ret
118 ;
119 ; RV32IDZFH-LABEL: fcvt_ui_h:
120 ; RV32IDZFH: # %bb.0:
121 ; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
122 ; RV32IDZFH-NEXT: ret
123 ;
124 ; RV64IZFH-LABEL: fcvt_ui_h:
125 ; RV64IZFH: # %bb.0:
126 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
127 ; RV64IZFH-NEXT: ret
128 ;
129 ; RV64IDZFH-LABEL: fcvt_ui_h:
130 ; RV64IDZFH: # %bb.0:
131 ; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
132 ; RV64IDZFH-NEXT: ret
133 %1 = fptoui half %a to i16
134 ret i16 %1
135 }
137 ; Test where the fptoui has multiple uses, one of which causes a sext to be
138 ; inserted on RV64.
139 ; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
140 define i32 @fcvt_ui_h_multiple_use(half %x, i32* %y) {
141 ; RV32IZFH-LABEL: fcvt_ui_h_multiple_use:
142 ; RV32IZFH: # %bb.0:
143 ; RV32IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
144 ; RV32IZFH-NEXT: addi a0, zero, 1
145 ; RV32IZFH-NEXT: beqz a1, .LBB3_2
146 ; RV32IZFH-NEXT: # %bb.1:
147 ; RV32IZFH-NEXT: mv a0, a1
148 ; RV32IZFH-NEXT: .LBB3_2:
149 ; RV32IZFH-NEXT: ret
150 ;
151 ; RV32IDZFH-LABEL: fcvt_ui_h_multiple_use:
152 ; RV32IDZFH: # %bb.0:
153 ; RV32IDZFH-NEXT: fcvt.wu.h a1, fa0, rtz
154 ; RV32IDZFH-NEXT: addi a0, zero, 1
155 ; RV32IDZFH-NEXT: beqz a1, .LBB3_2
156 ; RV32IDZFH-NEXT: # %bb.1:
157 ; RV32IDZFH-NEXT: mv a0, a1
158 ; RV32IDZFH-NEXT: .LBB3_2:
159 ; RV32IDZFH-NEXT: ret
160 ;
161 ; RV64IZFH-LABEL: fcvt_ui_h_multiple_use:
162 ; RV64IZFH: # %bb.0:
163 ; RV64IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
164 ; RV64IZFH-NEXT: addi a0, zero, 1
165 ; RV64IZFH-NEXT: beqz a1, .LBB3_2
166 ; RV64IZFH-NEXT: # %bb.1:
167 ; RV64IZFH-NEXT: mv a0, a1
168 ; RV64IZFH-NEXT: .LBB3_2:
169 ; RV64IZFH-NEXT: ret
170 ;
171 ; RV64IDZFH-LABEL: fcvt_ui_h_multiple_use:
172 ; RV64IDZFH: # %bb.0:
173 ; RV64IDZFH-NEXT: fcvt.wu.h a1, fa0, rtz
174 ; RV64IDZFH-NEXT: addi a0, zero, 1
175 ; RV64IDZFH-NEXT: beqz a1, .LBB3_2
176 ; RV64IDZFH-NEXT: # %bb.1:
177 ; RV64IDZFH-NEXT: mv a0, a1
178 ; RV64IDZFH-NEXT: .LBB3_2:
179 ; RV64IDZFH-NEXT: ret
180 %a = fptoui half %x to i32
181 %b = icmp eq i32 %a, 0
182 %c = select i1 %b, i32 1, i32 %a
183 ret i32 %c
184 }
186 define i16 @fcvt_ui_h_sat(half %a) nounwind {
187 ; RV32IZFH-LABEL: fcvt_ui_h_sat:
188 ; RV32IZFH: # %bb.0: # %start
189 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI4_0)
190 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
191 ; RV32IZFH-NEXT: fcvt.s.h ft1, fa0
192 ; RV32IZFH-NEXT: fmv.w.x ft2, zero
193 ; RV32IZFH-NEXT: fmax.s ft1, ft1, ft2
194 ; RV32IZFH-NEXT: fmin.s ft0, ft1, ft0
195 ; RV32IZFH-NEXT: fcvt.wu.s a0, ft0, rtz
196 ; RV32IZFH-NEXT: ret
197 ;
198 ; RV32IDZFH-LABEL: fcvt_ui_h_sat:
199 ; RV32IDZFH: # %bb.0: # %start
200 ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI4_0)
201 ; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
202 ; RV32IDZFH-NEXT: fcvt.s.h ft1, fa0
203 ; RV32IDZFH-NEXT: fmv.w.x ft2, zero
204 ; RV32IDZFH-NEXT: fmax.s ft1, ft1, ft2
205 ; RV32IDZFH-NEXT: fmin.s ft0, ft1, ft0
206 ; RV32IDZFH-NEXT: fcvt.wu.s a0, ft0, rtz
207 ; RV32IDZFH-NEXT: ret
208 ;
209 ; RV64IZFH-LABEL: fcvt_ui_h_sat:
210 ; RV64IZFH: # %bb.0: # %start
211 ; RV64IZFH-NEXT: lui a0, %hi(.LCPI4_0)
212 ; RV64IZFH-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
213 ; RV64IZFH-NEXT: fcvt.s.h ft1, fa0
214 ; RV64IZFH-NEXT: fmv.w.x ft2, zero
215 ; RV64IZFH-NEXT: fmax.s ft1, ft1, ft2
216 ; RV64IZFH-NEXT: fmin.s ft0, ft1, ft0
217 ; RV64IZFH-NEXT: fcvt.lu.s a0, ft0, rtz
218 ; RV64IZFH-NEXT: ret
219 ;
220 ; RV64IDZFH-LABEL: fcvt_ui_h_sat:
221 ; RV64IDZFH: # %bb.0: # %start
222 ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI4_0)
223 ; RV64IDZFH-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
224 ; RV64IDZFH-NEXT: fcvt.s.h ft1, fa0
225 ; RV64IDZFH-NEXT: fmv.w.x ft2, zero
226 ; RV64IDZFH-NEXT: fmax.s ft1, ft1, ft2
227 ; RV64IDZFH-NEXT: fmin.s ft0, ft1, ft0
228 ; RV64IDZFH-NEXT: fcvt.lu.s a0, ft0, rtz
229 ; RV64IDZFH-NEXT: ret
230 start:
231 %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
232 ret i16 %0
233 }
234 declare i16 @llvm.fptoui.sat.i16.f16(half)
236 define i32 @fcvt_w_h(half %a) nounwind {
237 ; RV32IZFH-LABEL: fcvt_w_h:
238 ; RV32IZFH: # %bb.0:
239 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
240 ; RV32IZFH-NEXT: ret
241 ;
242 ; RV32IDZFH-LABEL: fcvt_w_h:
243 ; RV32IDZFH: # %bb.0:
244 ; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
245 ; RV32IDZFH-NEXT: ret
246 ;
247 ; RV64IZFH-LABEL: fcvt_w_h:
248 ; RV64IZFH: # %bb.0:
249 ; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
250 ; RV64IZFH-NEXT: ret
251 ;
252 ; RV64IDZFH-LABEL: fcvt_w_h:
253 ; RV64IDZFH: # %bb.0:
254 ; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
255 ; RV64IDZFH-NEXT: ret
256 %1 = fptosi half %a to i32
257 ret i32 %1
258 }
260 define i32 @fcvt_w_h_sat(half %a) nounwind {
261 ; RV32IZFH-LABEL: fcvt_w_h_sat:
262 ; RV32IZFH: # %bb.0: # %start
263 ; RV32IZFH-NEXT: feq.h a0, fa0, fa0
264 ; RV32IZFH-NEXT: bnez a0, .LBB6_2
265 ; RV32IZFH-NEXT: # %bb.1: # %start
266 ; RV32IZFH-NEXT: mv a0, zero
267 ; RV32IZFH-NEXT: ret
268 ; RV32IZFH-NEXT: .LBB6_2:
269 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
270 ; RV32IZFH-NEXT: ret
271 ;
272 ; RV32IDZFH-LABEL: fcvt_w_h_sat:
273 ; RV32IDZFH: # %bb.0: # %start
274 ; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
275 ; RV32IDZFH-NEXT: bnez a0, .LBB6_2
276 ; RV32IDZFH-NEXT: # %bb.1: # %start
277 ; RV32IDZFH-NEXT: mv a0, zero
278 ; RV32IDZFH-NEXT: ret
279 ; RV32IDZFH-NEXT: .LBB6_2:
280 ; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
281 ; RV32IDZFH-NEXT: ret
282 ;
283 ; RV64IZFH-LABEL: fcvt_w_h_sat:
284 ; RV64IZFH: # %bb.0: # %start
285 ; RV64IZFH-NEXT: feq.h a0, fa0, fa0
286 ; RV64IZFH-NEXT: bnez a0, .LBB6_2
287 ; RV64IZFH-NEXT: # %bb.1: # %start
288 ; RV64IZFH-NEXT: mv a0, zero
289 ; RV64IZFH-NEXT: ret
290 ; RV64IZFH-NEXT: .LBB6_2:
291 ; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
292 ; RV64IZFH-NEXT: ret
293 ;
294 ; RV64IDZFH-LABEL: fcvt_w_h_sat:
295 ; RV64IDZFH: # %bb.0: # %start
296 ; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
297 ; RV64IDZFH-NEXT: bnez a0, .LBB6_2
298 ; RV64IDZFH-NEXT: # %bb.1: # %start
299 ; RV64IDZFH-NEXT: mv a0, zero
300 ; RV64IDZFH-NEXT: ret
301 ; RV64IDZFH-NEXT: .LBB6_2:
302 ; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
303 ; RV64IDZFH-NEXT: ret
304 start:
305 %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
306 ret i32 %0
307 }
308 declare i32 @llvm.fptosi.sat.i32.f16(half)
310 define i32 @fcvt_wu_h(half %a) nounwind {
311 ; RV32IZFH-LABEL: fcvt_wu_h:
312 ; RV32IZFH: # %bb.0:
313 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
314 ; RV32IZFH-NEXT: ret
315 ;
316 ; RV32IDZFH-LABEL: fcvt_wu_h:
317 ; RV32IDZFH: # %bb.0:
318 ; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
319 ; RV32IDZFH-NEXT: ret
320 ;
321 ; RV64IZFH-LABEL: fcvt_wu_h:
322 ; RV64IZFH: # %bb.0:
323 ; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
324 ; RV64IZFH-NEXT: ret
325 ;
326 ; RV64IDZFH-LABEL: fcvt_wu_h:
327 ; RV64IDZFH: # %bb.0:
328 ; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
329 ; RV64IDZFH-NEXT: ret
330 %1 = fptoui half %a to i32
331 ret i32 %1
332 }
334 define i32 @fcvt_wu_h_sat(half %a) nounwind {
335 ; RV32IZFH-LABEL: fcvt_wu_h_sat:
336 ; RV32IZFH: # %bb.0: # %start
337 ; RV32IZFH-NEXT: feq.h a0, fa0, fa0
338 ; RV32IZFH-NEXT: bnez a0, .LBB8_2
339 ; RV32IZFH-NEXT: # %bb.1: # %start
340 ; RV32IZFH-NEXT: mv a0, zero
341 ; RV32IZFH-NEXT: ret
342 ; RV32IZFH-NEXT: .LBB8_2:
343 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
344 ; RV32IZFH-NEXT: ret
345 ;
346 ; RV32IDZFH-LABEL: fcvt_wu_h_sat:
347 ; RV32IDZFH: # %bb.0: # %start
348 ; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
349 ; RV32IDZFH-NEXT: bnez a0, .LBB8_2
350 ; RV32IDZFH-NEXT: # %bb.1: # %start
351 ; RV32IDZFH-NEXT: mv a0, zero
352 ; RV32IDZFH-NEXT: ret
353 ; RV32IDZFH-NEXT: .LBB8_2:
354 ; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
355 ; RV32IDZFH-NEXT: ret
356 ;
357 ; RV64IZFH-LABEL: fcvt_wu_h_sat:
358 ; RV64IZFH: # %bb.0: # %start
359 ; RV64IZFH-NEXT: feq.h a0, fa0, fa0
360 ; RV64IZFH-NEXT: bnez a0, .LBB8_2
361 ; RV64IZFH-NEXT: # %bb.1: # %start
362 ; RV64IZFH-NEXT: mv a0, zero
363 ; RV64IZFH-NEXT: ret
364 ; RV64IZFH-NEXT: .LBB8_2:
365 ; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
366 ; RV64IZFH-NEXT: ret
367 ;
368 ; RV64IDZFH-LABEL: fcvt_wu_h_sat:
369 ; RV64IDZFH: # %bb.0: # %start
370 ; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
371 ; RV64IDZFH-NEXT: bnez a0, .LBB8_2
372 ; RV64IDZFH-NEXT: # %bb.1: # %start
373 ; RV64IDZFH-NEXT: mv a0, zero
374 ; RV64IDZFH-NEXT: ret
375 ; RV64IDZFH-NEXT: .LBB8_2:
376 ; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
377 ; RV64IDZFH-NEXT: ret
378 start:
379 %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
380 ret i32 %0
381 }
382 declare i32 @llvm.fptoui.sat.i32.f16(half)
384 define i64 @fcvt_l_h(half %a) nounwind {
385 ; RV32IZFH-LABEL: fcvt_l_h:
386 ; RV32IZFH: # %bb.0:
387 ; RV32IZFH-NEXT: addi sp, sp, -16
388 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
389 ; RV32IZFH-NEXT: call __fixhfdi@plt
390 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
391 ; RV32IZFH-NEXT: addi sp, sp, 16
392 ; RV32IZFH-NEXT: ret
393 ;
394 ; RV32IDZFH-LABEL: fcvt_l_h:
395 ; RV32IDZFH: # %bb.0:
396 ; RV32IDZFH-NEXT: addi sp, sp, -16
397 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
398 ; RV32IDZFH-NEXT: call __fixhfdi@plt
399 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
400 ; RV32IDZFH-NEXT: addi sp, sp, 16
401 ; RV32IDZFH-NEXT: ret
402 ;
403 ; RV64IZFH-LABEL: fcvt_l_h:
404 ; RV64IZFH: # %bb.0:
405 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
406 ; RV64IZFH-NEXT: ret
407 ;
408 ; RV64IDZFH-LABEL: fcvt_l_h:
409 ; RV64IDZFH: # %bb.0:
410 ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
411 ; RV64IDZFH-NEXT: ret
412 %1 = fptosi half %a to i64
413 ret i64 %1
414 }
416 define i64 @fcvt_l_h_sat(half %a) nounwind {
417 ; RV32IZFH-LABEL: fcvt_l_h_sat:
418 ; RV32IZFH: # %bb.0: # %start
419 ; RV32IZFH-NEXT: addi sp, sp, -16
420 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
421 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
422 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
423 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_0)
424 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
425 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
426 ; RV32IZFH-NEXT: fle.s s0, ft0, fs0
427 ; RV32IZFH-NEXT: fmv.s fa0, fs0
428 ; RV32IZFH-NEXT: call __fixsfdi@plt
429 ; RV32IZFH-NEXT: mv a2, a0
430 ; RV32IZFH-NEXT: bnez s0, .LBB10_2
431 ; RV32IZFH-NEXT: # %bb.1: # %start
432 ; RV32IZFH-NEXT: mv a2, zero
433 ; RV32IZFH-NEXT: .LBB10_2: # %start
434 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_1)
435 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI10_1)(a0)
436 ; RV32IZFH-NEXT: flt.s a3, ft0, fs0
437 ; RV32IZFH-NEXT: addi a0, zero, -1
438 ; RV32IZFH-NEXT: beqz a3, .LBB10_9
439 ; RV32IZFH-NEXT: # %bb.3: # %start
440 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
441 ; RV32IZFH-NEXT: beqz a2, .LBB10_10
442 ; RV32IZFH-NEXT: .LBB10_4: # %start
443 ; RV32IZFH-NEXT: lui a4, 524288
444 ; RV32IZFH-NEXT: beqz s0, .LBB10_11
445 ; RV32IZFH-NEXT: .LBB10_5: # %start
446 ; RV32IZFH-NEXT: bnez a3, .LBB10_12
447 ; RV32IZFH-NEXT: .LBB10_6: # %start
448 ; RV32IZFH-NEXT: bnez a2, .LBB10_8
449 ; RV32IZFH-NEXT: .LBB10_7: # %start
450 ; RV32IZFH-NEXT: mv a1, zero
451 ; RV32IZFH-NEXT: .LBB10_8: # %start
452 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
453 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
454 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
455 ; RV32IZFH-NEXT: addi sp, sp, 16
456 ; RV32IZFH-NEXT: ret
457 ; RV32IZFH-NEXT: .LBB10_9: # %start
458 ; RV32IZFH-NEXT: mv a0, a2
459 ; RV32IZFH-NEXT: feq.s a2, fs0, fs0
460 ; RV32IZFH-NEXT: bnez a2, .LBB10_4
461 ; RV32IZFH-NEXT: .LBB10_10: # %start
462 ; RV32IZFH-NEXT: mv a0, zero
463 ; RV32IZFH-NEXT: lui a4, 524288
464 ; RV32IZFH-NEXT: bnez s0, .LBB10_5
465 ; RV32IZFH-NEXT: .LBB10_11: # %start
466 ; RV32IZFH-NEXT: lui a1, 524288
467 ; RV32IZFH-NEXT: beqz a3, .LBB10_6
468 ; RV32IZFH-NEXT: .LBB10_12:
469 ; RV32IZFH-NEXT: addi a1, a4, -1
470 ; RV32IZFH-NEXT: beqz a2, .LBB10_7
471 ; RV32IZFH-NEXT: j .LBB10_8
472 ;
473 ; RV32IDZFH-LABEL: fcvt_l_h_sat:
474 ; RV32IDZFH: # %bb.0: # %start
475 ; RV32IDZFH-NEXT: addi sp, sp, -16
476 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
477 ; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
478 ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
479 ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_0)
480 ; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
481 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
482 ; RV32IDZFH-NEXT: fle.s s0, ft0, fs0
483 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
484 ; RV32IDZFH-NEXT: call __fixsfdi@plt
485 ; RV32IDZFH-NEXT: mv a2, a0
486 ; RV32IDZFH-NEXT: bnez s0, .LBB10_2
487 ; RV32IDZFH-NEXT: # %bb.1: # %start
488 ; RV32IDZFH-NEXT: mv a2, zero
489 ; RV32IDZFH-NEXT: .LBB10_2: # %start
490 ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_1)
491 ; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI10_1)(a0)
492 ; RV32IDZFH-NEXT: flt.s a3, ft0, fs0
493 ; RV32IDZFH-NEXT: addi a0, zero, -1
494 ; RV32IDZFH-NEXT: beqz a3, .LBB10_9
495 ; RV32IDZFH-NEXT: # %bb.3: # %start
496 ; RV32IDZFH-NEXT: feq.s a2, fs0, fs0
497 ; RV32IDZFH-NEXT: beqz a2, .LBB10_10
498 ; RV32IDZFH-NEXT: .LBB10_4: # %start
499 ; RV32IDZFH-NEXT: lui a4, 524288
500 ; RV32IDZFH-NEXT: beqz s0, .LBB10_11
501 ; RV32IDZFH-NEXT: .LBB10_5: # %start
502 ; RV32IDZFH-NEXT: bnez a3, .LBB10_12
503 ; RV32IDZFH-NEXT: .LBB10_6: # %start
504 ; RV32IDZFH-NEXT: bnez a2, .LBB10_8
505 ; RV32IDZFH-NEXT: .LBB10_7: # %start
506 ; RV32IDZFH-NEXT: mv a1, zero
507 ; RV32IDZFH-NEXT: .LBB10_8: # %start
508 ; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
509 ; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
510 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
511 ; RV32IDZFH-NEXT: addi sp, sp, 16
512 ; RV32IDZFH-NEXT: ret
513 ; RV32IDZFH-NEXT: .LBB10_9: # %start
514 ; RV32IDZFH-NEXT: mv a0, a2
515 ; RV32IDZFH-NEXT: feq.s a2, fs0, fs0
516 ; RV32IDZFH-NEXT: bnez a2, .LBB10_4
517 ; RV32IDZFH-NEXT: .LBB10_10: # %start
518 ; RV32IDZFH-NEXT: mv a0, zero
519 ; RV32IDZFH-NEXT: lui a4, 524288
520 ; RV32IDZFH-NEXT: bnez s0, .LBB10_5
521 ; RV32IDZFH-NEXT: .LBB10_11: # %start
522 ; RV32IDZFH-NEXT: lui a1, 524288
523 ; RV32IDZFH-NEXT: beqz a3, .LBB10_6
524 ; RV32IDZFH-NEXT: .LBB10_12:
525 ; RV32IDZFH-NEXT: addi a1, a4, -1
526 ; RV32IDZFH-NEXT: beqz a2, .LBB10_7
527 ; RV32IDZFH-NEXT: j .LBB10_8
528 ;
529 ; RV64IZFH-LABEL: fcvt_l_h_sat:
530 ; RV64IZFH: # %bb.0: # %start
531 ; RV64IZFH-NEXT: feq.h a0, fa0, fa0
532 ; RV64IZFH-NEXT: bnez a0, .LBB10_2
533 ; RV64IZFH-NEXT: # %bb.1: # %start
534 ; RV64IZFH-NEXT: mv a0, zero
535 ; RV64IZFH-NEXT: ret
536 ; RV64IZFH-NEXT: .LBB10_2:
537 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
538 ; RV64IZFH-NEXT: ret
539 ;
540 ; RV64IDZFH-LABEL: fcvt_l_h_sat:
541 ; RV64IDZFH: # %bb.0: # %start
542 ; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
543 ; RV64IDZFH-NEXT: bnez a0, .LBB10_2
544 ; RV64IDZFH-NEXT: # %bb.1: # %start
545 ; RV64IDZFH-NEXT: mv a0, zero
546 ; RV64IDZFH-NEXT: ret
547 ; RV64IDZFH-NEXT: .LBB10_2:
548 ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
549 ; RV64IDZFH-NEXT: ret
550 start:
551 %0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a)
552 ret i64 %0
553 }
554 declare i64 @llvm.fptosi.sat.i64.f16(half)
556 define i64 @fcvt_lu_h(half %a) nounwind {
557 ; RV32IZFH-LABEL: fcvt_lu_h:
558 ; RV32IZFH: # %bb.0:
559 ; RV32IZFH-NEXT: addi sp, sp, -16
560 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
561 ; RV32IZFH-NEXT: call __fixunshfdi@plt
562 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
563 ; RV32IZFH-NEXT: addi sp, sp, 16
564 ; RV32IZFH-NEXT: ret
565 ;
566 ; RV32IDZFH-LABEL: fcvt_lu_h:
567 ; RV32IDZFH: # %bb.0:
568 ; RV32IDZFH-NEXT: addi sp, sp, -16
569 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
570 ; RV32IDZFH-NEXT: call __fixunshfdi@plt
571 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
572 ; RV32IDZFH-NEXT: addi sp, sp, 16
573 ; RV32IDZFH-NEXT: ret
574 ;
575 ; RV64IZFH-LABEL: fcvt_lu_h:
576 ; RV64IZFH: # %bb.0:
577 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
578 ; RV64IZFH-NEXT: ret
579 ;
580 ; RV64IDZFH-LABEL: fcvt_lu_h:
581 ; RV64IDZFH: # %bb.0:
582 ; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
583 ; RV64IDZFH-NEXT: ret
584 %1 = fptoui half %a to i64
585 ret i64 %1
586 }
588 define i64 @fcvt_lu_h_sat(half %a) nounwind {
589 ; RV32IZFH-LABEL: fcvt_lu_h_sat:
590 ; RV32IZFH: # %bb.0: # %start
591 ; RV32IZFH-NEXT: addi sp, sp, -16
592 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
593 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
594 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
595 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
596 ; RV32IZFH-NEXT: fmv.w.x ft0, zero
597 ; RV32IZFH-NEXT: fle.s s0, ft0, fs0
598 ; RV32IZFH-NEXT: fmv.s fa0, fs0
599 ; RV32IZFH-NEXT: call __fixunssfdi@plt
600 ; RV32IZFH-NEXT: mv a3, a0
601 ; RV32IZFH-NEXT: bnez s0, .LBB12_2
602 ; RV32IZFH-NEXT: # %bb.1: # %start
603 ; RV32IZFH-NEXT: mv a3, zero
604 ; RV32IZFH-NEXT: .LBB12_2: # %start
605 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI12_0)
606 ; RV32IZFH-NEXT: flw ft0, %lo(.LCPI12_0)(a0)
607 ; RV32IZFH-NEXT: flt.s a4, ft0, fs0
608 ; RV32IZFH-NEXT: addi a2, zero, -1
609 ; RV32IZFH-NEXT: addi a0, zero, -1
610 ; RV32IZFH-NEXT: beqz a4, .LBB12_7
611 ; RV32IZFH-NEXT: # %bb.3: # %start
612 ; RV32IZFH-NEXT: beqz s0, .LBB12_8
613 ; RV32IZFH-NEXT: .LBB12_4: # %start
614 ; RV32IZFH-NEXT: bnez a4, .LBB12_6
615 ; RV32IZFH-NEXT: .LBB12_5: # %start
616 ; RV32IZFH-NEXT: mv a2, a1
617 ; RV32IZFH-NEXT: .LBB12_6: # %start
618 ; RV32IZFH-NEXT: mv a1, a2
619 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
620 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
621 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
622 ; RV32IZFH-NEXT: addi sp, sp, 16
623 ; RV32IZFH-NEXT: ret
624 ; RV32IZFH-NEXT: .LBB12_7: # %start
625 ; RV32IZFH-NEXT: mv a0, a3
626 ; RV32IZFH-NEXT: bnez s0, .LBB12_4
627 ; RV32IZFH-NEXT: .LBB12_8: # %start
628 ; RV32IZFH-NEXT: mv a1, zero
629 ; RV32IZFH-NEXT: beqz a4, .LBB12_5
630 ; RV32IZFH-NEXT: j .LBB12_6
631 ;
632 ; RV32IDZFH-LABEL: fcvt_lu_h_sat:
633 ; RV32IDZFH: # %bb.0: # %start
634 ; RV32IDZFH-NEXT: addi sp, sp, -16
635 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
636 ; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
637 ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
638 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
639 ; RV32IDZFH-NEXT: fmv.w.x ft0, zero
640 ; RV32IDZFH-NEXT: fle.s s0, ft0, fs0
641 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
642 ; RV32IDZFH-NEXT: call __fixunssfdi@plt
643 ; RV32IDZFH-NEXT: mv a3, a0
644 ; RV32IDZFH-NEXT: bnez s0, .LBB12_2
645 ; RV32IDZFH-NEXT: # %bb.1: # %start
646 ; RV32IDZFH-NEXT: mv a3, zero
647 ; RV32IDZFH-NEXT: .LBB12_2: # %start
648 ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI12_0)
649 ; RV32IDZFH-NEXT: flw ft0, %lo(.LCPI12_0)(a0)
650 ; RV32IDZFH-NEXT: flt.s a4, ft0, fs0
651 ; RV32IDZFH-NEXT: addi a2, zero, -1
652 ; RV32IDZFH-NEXT: addi a0, zero, -1
653 ; RV32IDZFH-NEXT: beqz a4, .LBB12_7
654 ; RV32IDZFH-NEXT: # %bb.3: # %start
655 ; RV32IDZFH-NEXT: beqz s0, .LBB12_8
656 ; RV32IDZFH-NEXT: .LBB12_4: # %start
657 ; RV32IDZFH-NEXT: bnez a4, .LBB12_6
658 ; RV32IDZFH-NEXT: .LBB12_5: # %start
659 ; RV32IDZFH-NEXT: mv a2, a1
660 ; RV32IDZFH-NEXT: .LBB12_6: # %start
661 ; RV32IDZFH-NEXT: mv a1, a2
662 ; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
663 ; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
664 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
665 ; RV32IDZFH-NEXT: addi sp, sp, 16
666 ; RV32IDZFH-NEXT: ret
667 ; RV32IDZFH-NEXT: .LBB12_7: # %start
668 ; RV32IDZFH-NEXT: mv a0, a3
669 ; RV32IDZFH-NEXT: bnez s0, .LBB12_4
670 ; RV32IDZFH-NEXT: .LBB12_8: # %start
671 ; RV32IDZFH-NEXT: mv a1, zero
672 ; RV32IDZFH-NEXT: beqz a4, .LBB12_5
673 ; RV32IDZFH-NEXT: j .LBB12_6
674 ;
675 ; RV64IZFH-LABEL: fcvt_lu_h_sat:
676 ; RV64IZFH: # %bb.0: # %start
677 ; RV64IZFH-NEXT: feq.h a0, fa0, fa0
678 ; RV64IZFH-NEXT: bnez a0, .LBB12_2
679 ; RV64IZFH-NEXT: # %bb.1: # %start
680 ; RV64IZFH-NEXT: mv a0, zero
681 ; RV64IZFH-NEXT: ret
682 ; RV64IZFH-NEXT: .LBB12_2:
683 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
684 ; RV64IZFH-NEXT: ret
685 ;
686 ; RV64IDZFH-LABEL: fcvt_lu_h_sat:
687 ; RV64IDZFH: # %bb.0: # %start
688 ; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
689 ; RV64IDZFH-NEXT: bnez a0, .LBB12_2
690 ; RV64IDZFH-NEXT: # %bb.1: # %start
691 ; RV64IDZFH-NEXT: mv a0, zero
692 ; RV64IDZFH-NEXT: ret
693 ; RV64IDZFH-NEXT: .LBB12_2:
694 ; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
695 ; RV64IDZFH-NEXT: ret
696 start:
697 %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)
698 ret i64 %0
699 }
700 declare i64 @llvm.fptoui.sat.i64.f16(half)
702 define half @fcvt_h_si(i16 %a) nounwind {
703 ; RV32IZFH-LABEL: fcvt_h_si:
704 ; RV32IZFH: # %bb.0:
705 ; RV32IZFH-NEXT: slli a0, a0, 16
706 ; RV32IZFH-NEXT: srai a0, a0, 16
707 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
708 ; RV32IZFH-NEXT: ret
709 ;
710 ; RV32IDZFH-LABEL: fcvt_h_si:
711 ; RV32IDZFH: # %bb.0:
712 ; RV32IDZFH-NEXT: slli a0, a0, 16
713 ; RV32IDZFH-NEXT: srai a0, a0, 16
714 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
715 ; RV32IDZFH-NEXT: ret
716 ;
717 ; RV64IZFH-LABEL: fcvt_h_si:
718 ; RV64IZFH: # %bb.0:
719 ; RV64IZFH-NEXT: slli a0, a0, 48
720 ; RV64IZFH-NEXT: srai a0, a0, 48
721 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
722 ; RV64IZFH-NEXT: ret
723 ;
724 ; RV64IDZFH-LABEL: fcvt_h_si:
725 ; RV64IDZFH: # %bb.0:
726 ; RV64IDZFH-NEXT: slli a0, a0, 48
727 ; RV64IDZFH-NEXT: srai a0, a0, 48
728 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
729 ; RV64IDZFH-NEXT: ret
730 %1 = sitofp i16 %a to half
731 ret half %1
732 }
734 define half @fcvt_h_si_signext(i16 signext %a) nounwind {
735 ; RV32IZFH-LABEL: fcvt_h_si_signext:
736 ; RV32IZFH: # %bb.0:
737 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
738 ; RV32IZFH-NEXT: ret
739 ;
740 ; RV32IDZFH-LABEL: fcvt_h_si_signext:
741 ; RV32IDZFH: # %bb.0:
742 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
743 ; RV32IDZFH-NEXT: ret
744 ;
745 ; RV64IZFH-LABEL: fcvt_h_si_signext:
746 ; RV64IZFH: # %bb.0:
747 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
748 ; RV64IZFH-NEXT: ret
749 ;
750 ; RV64IDZFH-LABEL: fcvt_h_si_signext:
751 ; RV64IDZFH: # %bb.0:
752 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
753 ; RV64IDZFH-NEXT: ret
754 %1 = sitofp i16 %a to half
755 ret half %1
756 }
758 define half @fcvt_h_ui(i16 %a) nounwind {
759 ; RV32IZFH-LABEL: fcvt_h_ui:
760 ; RV32IZFH: # %bb.0:
761 ; RV32IZFH-NEXT: lui a1, 16
762 ; RV32IZFH-NEXT: addi a1, a1, -1
763 ; RV32IZFH-NEXT: and a0, a0, a1
764 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
765 ; RV32IZFH-NEXT: ret
766 ;
767 ; RV32IDZFH-LABEL: fcvt_h_ui:
768 ; RV32IDZFH: # %bb.0:
769 ; RV32IDZFH-NEXT: lui a1, 16
770 ; RV32IDZFH-NEXT: addi a1, a1, -1
771 ; RV32IDZFH-NEXT: and a0, a0, a1
772 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
773 ; RV32IDZFH-NEXT: ret
774 ;
775 ; RV64IZFH-LABEL: fcvt_h_ui:
776 ; RV64IZFH: # %bb.0:
777 ; RV64IZFH-NEXT: lui a1, 16
778 ; RV64IZFH-NEXT: addiw a1, a1, -1
779 ; RV64IZFH-NEXT: and a0, a0, a1
780 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
781 ; RV64IZFH-NEXT: ret
782 ;
783 ; RV64IDZFH-LABEL: fcvt_h_ui:
784 ; RV64IDZFH: # %bb.0:
785 ; RV64IDZFH-NEXT: lui a1, 16
786 ; RV64IDZFH-NEXT: addiw a1, a1, -1
787 ; RV64IDZFH-NEXT: and a0, a0, a1
788 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
789 ; RV64IDZFH-NEXT: ret
790 %1 = uitofp i16 %a to half
791 ret half %1
792 }
794 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
795 ; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
796 ; RV32IZFH: # %bb.0:
797 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
798 ; RV32IZFH-NEXT: ret
799 ;
800 ; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
801 ; RV32IDZFH: # %bb.0:
802 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
803 ; RV32IDZFH-NEXT: ret
804 ;
805 ; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
806 ; RV64IZFH: # %bb.0:
807 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
808 ; RV64IZFH-NEXT: ret
809 ;
810 ; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
811 ; RV64IDZFH: # %bb.0:
812 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
813 ; RV64IDZFH-NEXT: ret
814 %1 = uitofp i16 %a to half
815 ret half %1
816 }
818 define half @fcvt_h_w(i32 %a) nounwind {
819 ; RV32IZFH-LABEL: fcvt_h_w:
820 ; RV32IZFH: # %bb.0:
821 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
822 ; RV32IZFH-NEXT: ret
823 ;
824 ; RV32IDZFH-LABEL: fcvt_h_w:
825 ; RV32IDZFH: # %bb.0:
826 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
827 ; RV32IDZFH-NEXT: ret
828 ;
829 ; RV64IZFH-LABEL: fcvt_h_w:
830 ; RV64IZFH: # %bb.0:
831 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
832 ; RV64IZFH-NEXT: ret
833 ;
834 ; RV64IDZFH-LABEL: fcvt_h_w:
835 ; RV64IDZFH: # %bb.0:
836 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
837 ; RV64IDZFH-NEXT: ret
838 %1 = sitofp i32 %a to half
839 ret half %1
840 }
842 define half @fcvt_h_w_load(i32* %p) nounwind {
843 ; RV32IZFH-LABEL: fcvt_h_w_load:
844 ; RV32IZFH: # %bb.0:
845 ; RV32IZFH-NEXT: lw a0, 0(a0)
846 ; RV32IZFH-NEXT: fcvt.h.w fa0, a0
847 ; RV32IZFH-NEXT: ret
848 ;
849 ; RV32IDZFH-LABEL: fcvt_h_w_load:
850 ; RV32IDZFH: # %bb.0:
851 ; RV32IDZFH-NEXT: lw a0, 0(a0)
852 ; RV32IDZFH-NEXT: fcvt.h.w fa0, a0
853 ; RV32IDZFH-NEXT: ret
854 ;
855 ; RV64IZFH-LABEL: fcvt_h_w_load:
856 ; RV64IZFH: # %bb.0:
857 ; RV64IZFH-NEXT: lw a0, 0(a0)
858 ; RV64IZFH-NEXT: fcvt.h.w fa0, a0
859 ; RV64IZFH-NEXT: ret
860 ;
861 ; RV64IDZFH-LABEL: fcvt_h_w_load:
862 ; RV64IDZFH: # %bb.0:
863 ; RV64IDZFH-NEXT: lw a0, 0(a0)
864 ; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
865 ; RV64IDZFH-NEXT: ret
866 %a = load i32, i32* %p
867 %1 = sitofp i32 %a to half
868 ret half %1
869 }
871 define half @fcvt_h_wu(i32 %a) nounwind {
872 ; RV32IZFH-LABEL: fcvt_h_wu:
873 ; RV32IZFH: # %bb.0:
874 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
875 ; RV32IZFH-NEXT: ret
876 ;
877 ; RV32IDZFH-LABEL: fcvt_h_wu:
878 ; RV32IDZFH: # %bb.0:
879 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
880 ; RV32IDZFH-NEXT: ret
881 ;
882 ; RV64IZFH-LABEL: fcvt_h_wu:
883 ; RV64IZFH: # %bb.0:
884 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
885 ; RV64IZFH-NEXT: ret
886 ;
887 ; RV64IDZFH-LABEL: fcvt_h_wu:
888 ; RV64IDZFH: # %bb.0:
889 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
890 ; RV64IDZFH-NEXT: ret
891 %1 = uitofp i32 %a to half
892 ret half %1
893 }
895 define half @fcvt_h_wu_load(i32* %p) nounwind {
896 ; RV32IZFH-LABEL: fcvt_h_wu_load:
897 ; RV32IZFH: # %bb.0:
898 ; RV32IZFH-NEXT: lw a0, 0(a0)
899 ; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
900 ; RV32IZFH-NEXT: ret
901 ;
902 ; RV32IDZFH-LABEL: fcvt_h_wu_load:
903 ; RV32IDZFH: # %bb.0:
904 ; RV32IDZFH-NEXT: lw a0, 0(a0)
905 ; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0
906 ; RV32IDZFH-NEXT: ret
907 ;
908 ; RV64IZFH-LABEL: fcvt_h_wu_load:
909 ; RV64IZFH: # %bb.0:
910 ; RV64IZFH-NEXT: lwu a0, 0(a0)
911 ; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
912 ; RV64IZFH-NEXT: ret
913 ;
914 ; RV64IDZFH-LABEL: fcvt_h_wu_load:
915 ; RV64IDZFH: # %bb.0:
916 ; RV64IDZFH-NEXT: lwu a0, 0(a0)
917 ; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
918 ; RV64IDZFH-NEXT: ret
919 %a = load i32, i32* %p
920 %1 = uitofp i32 %a to half
921 ret half %1
922 }
924 define half @fcvt_h_l(i64 %a) nounwind {
925 ; RV32IZFH-LABEL: fcvt_h_l:
926 ; RV32IZFH: # %bb.0:
927 ; RV32IZFH-NEXT: addi sp, sp, -16
928 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
929 ; RV32IZFH-NEXT: call __floatdihf@plt
930 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
931 ; RV32IZFH-NEXT: addi sp, sp, 16
932 ; RV32IZFH-NEXT: ret
933 ;
934 ; RV32IDZFH-LABEL: fcvt_h_l:
935 ; RV32IDZFH: # %bb.0:
936 ; RV32IDZFH-NEXT: addi sp, sp, -16
937 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
938 ; RV32IDZFH-NEXT: call __floatdihf@plt
939 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
940 ; RV32IDZFH-NEXT: addi sp, sp, 16
941 ; RV32IDZFH-NEXT: ret
942 ;
943 ; RV64IZFH-LABEL: fcvt_h_l:
944 ; RV64IZFH: # %bb.0:
945 ; RV64IZFH-NEXT: fcvt.h.l fa0, a0
946 ; RV64IZFH-NEXT: ret
947 ;
948 ; RV64IDZFH-LABEL: fcvt_h_l:
949 ; RV64IDZFH: # %bb.0:
950 ; RV64IDZFH-NEXT: fcvt.h.l fa0, a0
951 ; RV64IDZFH-NEXT: ret
952 %1 = sitofp i64 %a to half
953 ret half %1
954 }
956 define half @fcvt_h_lu(i64 %a) nounwind {
957 ; RV32IZFH-LABEL: fcvt_h_lu:
958 ; RV32IZFH: # %bb.0:
959 ; RV32IZFH-NEXT: addi sp, sp, -16
960 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
961 ; RV32IZFH-NEXT: call __floatundihf@plt
962 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
963 ; RV32IZFH-NEXT: addi sp, sp, 16
964 ; RV32IZFH-NEXT: ret
965 ;
966 ; RV32IDZFH-LABEL: fcvt_h_lu:
967 ; RV32IDZFH: # %bb.0:
968 ; RV32IDZFH-NEXT: addi sp, sp, -16
969 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
970 ; RV32IDZFH-NEXT: call __floatundihf@plt
971 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
972 ; RV32IDZFH-NEXT: addi sp, sp, 16
973 ; RV32IDZFH-NEXT: ret
974 ;
975 ; RV64IZFH-LABEL: fcvt_h_lu:
976 ; RV64IZFH: # %bb.0:
977 ; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
978 ; RV64IZFH-NEXT: ret
979 ;
980 ; RV64IDZFH-LABEL: fcvt_h_lu:
981 ; RV64IDZFH: # %bb.0:
982 ; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0
983 ; RV64IDZFH-NEXT: ret
984 %1 = uitofp i64 %a to half
985 ret half %1
986 }
988 define half @fcvt_h_s(float %a) nounwind {
989 ; RV32IZFH-LABEL: fcvt_h_s:
990 ; RV32IZFH: # %bb.0:
991 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
992 ; RV32IZFH-NEXT: ret
993 ;
994 ; RV32IDZFH-LABEL: fcvt_h_s:
995 ; RV32IDZFH: # %bb.0:
996 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
997 ; RV32IDZFH-NEXT: ret
998 ;
999 ; RV64IZFH-LABEL: fcvt_h_s:
1000 ; RV64IZFH: # %bb.0:
1001 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1002 ; RV64IZFH-NEXT: ret
1003 ;
1004 ; RV64IDZFH-LABEL: fcvt_h_s:
1005 ; RV64IDZFH: # %bb.0:
1006 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1007 ; RV64IDZFH-NEXT: ret
1008 %1 = fptrunc float %a to half
1009 ret half %1
1010 }
1012 define float @fcvt_s_h(half %a) nounwind {
1013 ; RV32IZFH-LABEL: fcvt_s_h:
1014 ; RV32IZFH: # %bb.0:
1015 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1016 ; RV32IZFH-NEXT: ret
1017 ;
1018 ; RV32IDZFH-LABEL: fcvt_s_h:
1019 ; RV32IDZFH: # %bb.0:
1020 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1021 ; RV32IDZFH-NEXT: ret
1022 ;
1023 ; RV64IZFH-LABEL: fcvt_s_h:
1024 ; RV64IZFH: # %bb.0:
1025 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1026 ; RV64IZFH-NEXT: ret
1027 ;
1028 ; RV64IDZFH-LABEL: fcvt_s_h:
1029 ; RV64IDZFH: # %bb.0:
1030 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1031 ; RV64IDZFH-NEXT: ret
1032 %1 = fpext half %a to float
1033 ret float %1
1034 }
1036 define half @fcvt_h_d(double %a) nounwind {
1037 ; RV32IZFH-LABEL: fcvt_h_d:
1038 ; RV32IZFH: # %bb.0:
1039 ; RV32IZFH-NEXT: addi sp, sp, -16
1040 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1041 ; RV32IZFH-NEXT: call __truncdfhf2@plt
1042 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1043 ; RV32IZFH-NEXT: addi sp, sp, 16
1044 ; RV32IZFH-NEXT: ret
1045 ;
1046 ; RV32IDZFH-LABEL: fcvt_h_d:
1047 ; RV32IDZFH: # %bb.0:
1048 ; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0
1049 ; RV32IDZFH-NEXT: ret
1050 ;
1051 ; RV64IZFH-LABEL: fcvt_h_d:
1052 ; RV64IZFH: # %bb.0:
1053 ; RV64IZFH-NEXT: addi sp, sp, -16
1054 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1055 ; RV64IZFH-NEXT: call __truncdfhf2@plt
1056 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1057 ; RV64IZFH-NEXT: addi sp, sp, 16
1058 ; RV64IZFH-NEXT: ret
1059 ;
1060 ; RV64IDZFH-LABEL: fcvt_h_d:
1061 ; RV64IDZFH: # %bb.0:
1062 ; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0
1063 ; RV64IDZFH-NEXT: ret
1064 %1 = fptrunc double %a to half
1065 ret half %1
1066 }
1068 define double @fcvt_d_h(half %a) nounwind {
1069 ; RV32IZFH-LABEL: fcvt_d_h:
1070 ; RV32IZFH: # %bb.0:
1071 ; RV32IZFH-NEXT: addi sp, sp, -16
1072 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1073 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1074 ; RV32IZFH-NEXT: call __extendsfdf2@plt
1075 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1076 ; RV32IZFH-NEXT: addi sp, sp, 16
1077 ; RV32IZFH-NEXT: ret
1078 ;
1079 ; RV32IDZFH-LABEL: fcvt_d_h:
1080 ; RV32IDZFH: # %bb.0:
1081 ; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0
1082 ; RV32IDZFH-NEXT: ret
1083 ;
1084 ; RV64IZFH-LABEL: fcvt_d_h:
1085 ; RV64IZFH: # %bb.0:
1086 ; RV64IZFH-NEXT: addi sp, sp, -16
1087 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1088 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1089 ; RV64IZFH-NEXT: call __extendsfdf2@plt
1090 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1091 ; RV64IZFH-NEXT: addi sp, sp, 16
1092 ; RV64IZFH-NEXT: ret
1093 ;
1094 ; RV64IDZFH-LABEL: fcvt_d_h:
1095 ; RV64IDZFH: # %bb.0:
1096 ; RV64IDZFH-NEXT: fcvt.d.h fa0, fa0
1097 ; RV64IDZFH-NEXT: ret
1098 %1 = fpext half %a to double
1099 ret double %1
1100 }
1102 define half @bitcast_h_i16(i16 %a) nounwind {
1103 ; RV32IZFH-LABEL: bitcast_h_i16:
1104 ; RV32IZFH: # %bb.0:
1105 ; RV32IZFH-NEXT: fmv.h.x fa0, a0
1106 ; RV32IZFH-NEXT: ret
1107 ;
1108 ; RV32IDZFH-LABEL: bitcast_h_i16:
1109 ; RV32IDZFH: # %bb.0:
1110 ; RV32IDZFH-NEXT: fmv.h.x fa0, a0
1111 ; RV32IDZFH-NEXT: ret
1112 ;
1113 ; RV64IZFH-LABEL: bitcast_h_i16:
1114 ; RV64IZFH: # %bb.0:
1115 ; RV64IZFH-NEXT: fmv.h.x fa0, a0
1116 ; RV64IZFH-NEXT: ret
1117 ;
1118 ; RV64IDZFH-LABEL: bitcast_h_i16:
1119 ; RV64IDZFH: # %bb.0:
1120 ; RV64IDZFH-NEXT: fmv.h.x fa0, a0
1121 ; RV64IDZFH-NEXT: ret
1122 %1 = bitcast i16 %a to half
1123 ret half %1
1124 }
1126 define i16 @bitcast_i16_h(half %a) nounwind {
1127 ; RV32IZFH-LABEL: bitcast_i16_h:
1128 ; RV32IZFH: # %bb.0:
1129 ; RV32IZFH-NEXT: fmv.x.h a0, fa0
1130 ; RV32IZFH-NEXT: ret
1131 ;
1132 ; RV32IDZFH-LABEL: bitcast_i16_h:
1133 ; RV32IDZFH: # %bb.0:
1134 ; RV32IDZFH-NEXT: fmv.x.h a0, fa0
1135 ; RV32IDZFH-NEXT: ret
1136 ;
1137 ; RV64IZFH-LABEL: bitcast_i16_h:
1138 ; RV64IZFH: # %bb.0:
1139 ; RV64IZFH-NEXT: fmv.x.h a0, fa0
1140 ; RV64IZFH-NEXT: ret
1141 ;
1142 ; RV64IDZFH-LABEL: bitcast_i16_h:
1143 ; RV64IDZFH: # %bb.0:
1144 ; RV64IDZFH-NEXT: fmv.x.h a0, fa0
1145 ; RV64IDZFH-NEXT: ret
1146 %1 = bitcast half %a to i16
1147 ret i16 %1
1148 }