1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV32I-SMALL
4 ; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM
6 ; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
7 ; RUN: | FileCheck %s -check-prefix=RV64I-SMALL
8 ; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
9 ; RUN: | FileCheck %s -check-prefix=RV64I-MEDIUM
11 define void @below_threshold(i32 %in, i32* %out) nounwind {
12 ; RV32I-SMALL-LABEL: below_threshold:
13 ; RV32I-SMALL: # %bb.0: # %entry
14 ; RV32I-SMALL-NEXT: addi a2, zero, 2
15 ; RV32I-SMALL-NEXT: blt a2, a0, .LBB0_4
16 ; RV32I-SMALL-NEXT: # %bb.1: # %entry
17 ; RV32I-SMALL-NEXT: addi a2, zero, 1
18 ; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_7
19 ; RV32I-SMALL-NEXT: # %bb.2: # %entry
20 ; RV32I-SMALL-NEXT: addi a2, zero, 2
21 ; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
22 ; RV32I-SMALL-NEXT: # %bb.3: # %bb2
23 ; RV32I-SMALL-NEXT: addi a0, zero, 3
24 ; RV32I-SMALL-NEXT: j .LBB0_9
25 ; RV32I-SMALL-NEXT: .LBB0_4: # %entry
26 ; RV32I-SMALL-NEXT: addi a2, zero, 3
27 ; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_8
28 ; RV32I-SMALL-NEXT: # %bb.5: # %entry
29 ; RV32I-SMALL-NEXT: addi a2, zero, 4
30 ; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
31 ; RV32I-SMALL-NEXT: # %bb.6: # %bb4
32 ; RV32I-SMALL-NEXT: addi a0, zero, 1
33 ; RV32I-SMALL-NEXT: j .LBB0_9
34 ; RV32I-SMALL-NEXT: .LBB0_7: # %bb1
35 ; RV32I-SMALL-NEXT: addi a0, zero, 4
36 ; RV32I-SMALL-NEXT: j .LBB0_9
37 ; RV32I-SMALL-NEXT: .LBB0_8: # %bb3
38 ; RV32I-SMALL-NEXT: addi a0, zero, 2
39 ; RV32I-SMALL-NEXT: .LBB0_9: # %exit
40 ; RV32I-SMALL-NEXT: sw a0, 0(a1)
41 ; RV32I-SMALL-NEXT: .LBB0_10: # %exit
42 ; RV32I-SMALL-NEXT: ret
44 ; RV32I-MEDIUM-LABEL: below_threshold:
45 ; RV32I-MEDIUM: # %bb.0: # %entry
46 ; RV32I-MEDIUM-NEXT: addi a2, zero, 2
47 ; RV32I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
48 ; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
49 ; RV32I-MEDIUM-NEXT: addi a2, zero, 1
50 ; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
51 ; RV32I-MEDIUM-NEXT: # %bb.2: # %entry
52 ; RV32I-MEDIUM-NEXT: addi a2, zero, 2
53 ; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
54 ; RV32I-MEDIUM-NEXT: # %bb.3: # %bb2
55 ; RV32I-MEDIUM-NEXT: addi a0, zero, 3
56 ; RV32I-MEDIUM-NEXT: j .LBB0_9
57 ; RV32I-MEDIUM-NEXT: .LBB0_4: # %entry
58 ; RV32I-MEDIUM-NEXT: addi a2, zero, 3
59 ; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
60 ; RV32I-MEDIUM-NEXT: # %bb.5: # %entry
61 ; RV32I-MEDIUM-NEXT: addi a2, zero, 4
62 ; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
63 ; RV32I-MEDIUM-NEXT: # %bb.6: # %bb4
64 ; RV32I-MEDIUM-NEXT: addi a0, zero, 1
65 ; RV32I-MEDIUM-NEXT: j .LBB0_9
66 ; RV32I-MEDIUM-NEXT: .LBB0_7: # %bb1
67 ; RV32I-MEDIUM-NEXT: addi a0, zero, 4
68 ; RV32I-MEDIUM-NEXT: j .LBB0_9
69 ; RV32I-MEDIUM-NEXT: .LBB0_8: # %bb3
70 ; RV32I-MEDIUM-NEXT: addi a0, zero, 2
71 ; RV32I-MEDIUM-NEXT: .LBB0_9: # %exit
72 ; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
73 ; RV32I-MEDIUM-NEXT: .LBB0_10: # %exit
74 ; RV32I-MEDIUM-NEXT: ret
76 ; RV64I-SMALL-LABEL: below_threshold:
77 ; RV64I-SMALL: # %bb.0: # %entry
78 ; RV64I-SMALL-NEXT: sext.w a0, a0
79 ; RV64I-SMALL-NEXT: addi a2, zero, 2
80 ; RV64I-SMALL-NEXT: blt a2, a0, .LBB0_4
81 ; RV64I-SMALL-NEXT: # %bb.1: # %entry
82 ; RV64I-SMALL-NEXT: addi a2, zero, 1
83 ; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_7
84 ; RV64I-SMALL-NEXT: # %bb.2: # %entry
85 ; RV64I-SMALL-NEXT: addi a2, zero, 2
86 ; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
87 ; RV64I-SMALL-NEXT: # %bb.3: # %bb2
88 ; RV64I-SMALL-NEXT: addi a0, zero, 3
89 ; RV64I-SMALL-NEXT: j .LBB0_9
90 ; RV64I-SMALL-NEXT: .LBB0_4: # %entry
91 ; RV64I-SMALL-NEXT: addi a2, zero, 3
92 ; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_8
93 ; RV64I-SMALL-NEXT: # %bb.5: # %entry
94 ; RV64I-SMALL-NEXT: addi a2, zero, 4
95 ; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
96 ; RV64I-SMALL-NEXT: # %bb.6: # %bb4
97 ; RV64I-SMALL-NEXT: addi a0, zero, 1
98 ; RV64I-SMALL-NEXT: j .LBB0_9
99 ; RV64I-SMALL-NEXT: .LBB0_7: # %bb1
100 ; RV64I-SMALL-NEXT: addi a0, zero, 4
101 ; RV64I-SMALL-NEXT: j .LBB0_9
102 ; RV64I-SMALL-NEXT: .LBB0_8: # %bb3
103 ; RV64I-SMALL-NEXT: addi a0, zero, 2
104 ; RV64I-SMALL-NEXT: .LBB0_9: # %exit
105 ; RV64I-SMALL-NEXT: sw a0, 0(a1)
106 ; RV64I-SMALL-NEXT: .LBB0_10: # %exit
107 ; RV64I-SMALL-NEXT: ret
109 ; RV64I-MEDIUM-LABEL: below_threshold:
110 ; RV64I-MEDIUM: # %bb.0: # %entry
111 ; RV64I-MEDIUM-NEXT: sext.w a0, a0
112 ; RV64I-MEDIUM-NEXT: addi a2, zero, 2
113 ; RV64I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
114 ; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
115 ; RV64I-MEDIUM-NEXT: addi a2, zero, 1
116 ; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
117 ; RV64I-MEDIUM-NEXT: # %bb.2: # %entry
118 ; RV64I-MEDIUM-NEXT: addi a2, zero, 2
119 ; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
120 ; RV64I-MEDIUM-NEXT: # %bb.3: # %bb2
121 ; RV64I-MEDIUM-NEXT: addi a0, zero, 3
122 ; RV64I-MEDIUM-NEXT: j .LBB0_9
123 ; RV64I-MEDIUM-NEXT: .LBB0_4: # %entry
124 ; RV64I-MEDIUM-NEXT: addi a2, zero, 3
125 ; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
126 ; RV64I-MEDIUM-NEXT: # %bb.5: # %entry
127 ; RV64I-MEDIUM-NEXT: addi a2, zero, 4
128 ; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
129 ; RV64I-MEDIUM-NEXT: # %bb.6: # %bb4
130 ; RV64I-MEDIUM-NEXT: addi a0, zero, 1
131 ; RV64I-MEDIUM-NEXT: j .LBB0_9
132 ; RV64I-MEDIUM-NEXT: .LBB0_7: # %bb1
133 ; RV64I-MEDIUM-NEXT: addi a0, zero, 4
134 ; RV64I-MEDIUM-NEXT: j .LBB0_9
135 ; RV64I-MEDIUM-NEXT: .LBB0_8: # %bb3
136 ; RV64I-MEDIUM-NEXT: addi a0, zero, 2
137 ; RV64I-MEDIUM-NEXT: .LBB0_9: # %exit
138 ; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
139 ; RV64I-MEDIUM-NEXT: .LBB0_10: # %exit
140 ; RV64I-MEDIUM-NEXT: ret
142 switch i32 %in, label %exit [
149 store i32 4, i32* %out
152 store i32 3, i32* %out
155 store i32 2, i32* %out
158 store i32 1, i32* %out
164 define void @above_threshold(i32 %in, i32* %out) nounwind {
165 ; RV32I-SMALL-LABEL: above_threshold:
166 ; RV32I-SMALL: # %bb.0: # %entry
167 ; RV32I-SMALL-NEXT: addi a0, a0, -1
168 ; RV32I-SMALL-NEXT: addi a2, zero, 5
169 ; RV32I-SMALL-NEXT: bltu a2, a0, .LBB1_9
170 ; RV32I-SMALL-NEXT: # %bb.1: # %entry
171 ; RV32I-SMALL-NEXT: slli a0, a0, 2
172 ; RV32I-SMALL-NEXT: lui a2, %hi(.LJTI1_0)
173 ; RV32I-SMALL-NEXT: addi a2, a2, %lo(.LJTI1_0)
174 ; RV32I-SMALL-NEXT: add a0, a0, a2
175 ; RV32I-SMALL-NEXT: lw a0, 0(a0)
176 ; RV32I-SMALL-NEXT: jr a0
177 ; RV32I-SMALL-NEXT: .LBB1_2: # %bb1
178 ; RV32I-SMALL-NEXT: addi a0, zero, 4
179 ; RV32I-SMALL-NEXT: j .LBB1_8
180 ; RV32I-SMALL-NEXT: .LBB1_3: # %bb2
181 ; RV32I-SMALL-NEXT: addi a0, zero, 3
182 ; RV32I-SMALL-NEXT: j .LBB1_8
183 ; RV32I-SMALL-NEXT: .LBB1_4: # %bb3
184 ; RV32I-SMALL-NEXT: addi a0, zero, 2
185 ; RV32I-SMALL-NEXT: j .LBB1_8
186 ; RV32I-SMALL-NEXT: .LBB1_5: # %bb4
187 ; RV32I-SMALL-NEXT: addi a0, zero, 1
188 ; RV32I-SMALL-NEXT: j .LBB1_8
189 ; RV32I-SMALL-NEXT: .LBB1_6: # %bb5
190 ; RV32I-SMALL-NEXT: addi a0, zero, 100
191 ; RV32I-SMALL-NEXT: j .LBB1_8
192 ; RV32I-SMALL-NEXT: .LBB1_7: # %bb6
193 ; RV32I-SMALL-NEXT: addi a0, zero, 200
194 ; RV32I-SMALL-NEXT: .LBB1_8: # %exit
195 ; RV32I-SMALL-NEXT: sw a0, 0(a1)
196 ; RV32I-SMALL-NEXT: .LBB1_9: # %exit
197 ; RV32I-SMALL-NEXT: ret
199 ; RV32I-MEDIUM-LABEL: above_threshold:
200 ; RV32I-MEDIUM: # %bb.0: # %entry
201 ; RV32I-MEDIUM-NEXT: addi a0, a0, -1
202 ; RV32I-MEDIUM-NEXT: addi a2, zero, 5
203 ; RV32I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
204 ; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
205 ; RV32I-MEDIUM-NEXT: slli a0, a0, 2
206 ; RV32I-MEDIUM-NEXT: .LBB1_10: # %entry
207 ; RV32I-MEDIUM-NEXT: # Label of block must be emitted
208 ; RV32I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI1_0)
209 ; RV32I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.LBB1_10)
210 ; RV32I-MEDIUM-NEXT: add a0, a0, a2
211 ; RV32I-MEDIUM-NEXT: lw a0, 0(a0)
212 ; RV32I-MEDIUM-NEXT: jr a0
213 ; RV32I-MEDIUM-NEXT: .LBB1_2: # %bb1
214 ; RV32I-MEDIUM-NEXT: addi a0, zero, 4
215 ; RV32I-MEDIUM-NEXT: j .LBB1_8
216 ; RV32I-MEDIUM-NEXT: .LBB1_3: # %bb2
217 ; RV32I-MEDIUM-NEXT: addi a0, zero, 3
218 ; RV32I-MEDIUM-NEXT: j .LBB1_8
219 ; RV32I-MEDIUM-NEXT: .LBB1_4: # %bb3
220 ; RV32I-MEDIUM-NEXT: addi a0, zero, 2
221 ; RV32I-MEDIUM-NEXT: j .LBB1_8
222 ; RV32I-MEDIUM-NEXT: .LBB1_5: # %bb4
223 ; RV32I-MEDIUM-NEXT: addi a0, zero, 1
224 ; RV32I-MEDIUM-NEXT: j .LBB1_8
225 ; RV32I-MEDIUM-NEXT: .LBB1_6: # %bb5
226 ; RV32I-MEDIUM-NEXT: addi a0, zero, 100
227 ; RV32I-MEDIUM-NEXT: j .LBB1_8
228 ; RV32I-MEDIUM-NEXT: .LBB1_7: # %bb6
229 ; RV32I-MEDIUM-NEXT: addi a0, zero, 200
230 ; RV32I-MEDIUM-NEXT: .LBB1_8: # %exit
231 ; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
232 ; RV32I-MEDIUM-NEXT: .LBB1_9: # %exit
233 ; RV32I-MEDIUM-NEXT: ret
235 ; RV64I-SMALL-LABEL: above_threshold:
236 ; RV64I-SMALL: # %bb.0: # %entry
237 ; RV64I-SMALL-NEXT: sext.w a0, a0
238 ; RV64I-SMALL-NEXT: addi a0, a0, -1
239 ; RV64I-SMALL-NEXT: addi a2, zero, 5
240 ; RV64I-SMALL-NEXT: bltu a2, a0, .LBB1_9
241 ; RV64I-SMALL-NEXT: # %bb.1: # %entry
242 ; RV64I-SMALL-NEXT: slli a0, a0, 3
243 ; RV64I-SMALL-NEXT: lui a2, %hi(.LJTI1_0)
244 ; RV64I-SMALL-NEXT: addi a2, a2, %lo(.LJTI1_0)
245 ; RV64I-SMALL-NEXT: add a0, a0, a2
246 ; RV64I-SMALL-NEXT: ld a0, 0(a0)
247 ; RV64I-SMALL-NEXT: jr a0
248 ; RV64I-SMALL-NEXT: .LBB1_2: # %bb1
249 ; RV64I-SMALL-NEXT: addi a0, zero, 4
250 ; RV64I-SMALL-NEXT: j .LBB1_8
251 ; RV64I-SMALL-NEXT: .LBB1_3: # %bb2
252 ; RV64I-SMALL-NEXT: addi a0, zero, 3
253 ; RV64I-SMALL-NEXT: j .LBB1_8
254 ; RV64I-SMALL-NEXT: .LBB1_4: # %bb3
255 ; RV64I-SMALL-NEXT: addi a0, zero, 2
256 ; RV64I-SMALL-NEXT: j .LBB1_8
257 ; RV64I-SMALL-NEXT: .LBB1_5: # %bb4
258 ; RV64I-SMALL-NEXT: addi a0, zero, 1
259 ; RV64I-SMALL-NEXT: j .LBB1_8
260 ; RV64I-SMALL-NEXT: .LBB1_6: # %bb5
261 ; RV64I-SMALL-NEXT: addi a0, zero, 100
262 ; RV64I-SMALL-NEXT: j .LBB1_8
263 ; RV64I-SMALL-NEXT: .LBB1_7: # %bb6
264 ; RV64I-SMALL-NEXT: addi a0, zero, 200
265 ; RV64I-SMALL-NEXT: .LBB1_8: # %exit
266 ; RV64I-SMALL-NEXT: sw a0, 0(a1)
267 ; RV64I-SMALL-NEXT: .LBB1_9: # %exit
268 ; RV64I-SMALL-NEXT: ret
270 ; RV64I-MEDIUM-LABEL: above_threshold:
271 ; RV64I-MEDIUM: # %bb.0: # %entry
272 ; RV64I-MEDIUM-NEXT: sext.w a0, a0
273 ; RV64I-MEDIUM-NEXT: addi a0, a0, -1
274 ; RV64I-MEDIUM-NEXT: addi a2, zero, 5
275 ; RV64I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
276 ; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
277 ; RV64I-MEDIUM-NEXT: slli a0, a0, 3
278 ; RV64I-MEDIUM-NEXT: .LBB1_10: # %entry
279 ; RV64I-MEDIUM-NEXT: # Label of block must be emitted
280 ; RV64I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI1_0)
281 ; RV64I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.LBB1_10)
282 ; RV64I-MEDIUM-NEXT: add a0, a0, a2
283 ; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
284 ; RV64I-MEDIUM-NEXT: jr a0
285 ; RV64I-MEDIUM-NEXT: .LBB1_2: # %bb1
286 ; RV64I-MEDIUM-NEXT: addi a0, zero, 4
287 ; RV64I-MEDIUM-NEXT: j .LBB1_8
288 ; RV64I-MEDIUM-NEXT: .LBB1_3: # %bb2
289 ; RV64I-MEDIUM-NEXT: addi a0, zero, 3
290 ; RV64I-MEDIUM-NEXT: j .LBB1_8
291 ; RV64I-MEDIUM-NEXT: .LBB1_4: # %bb3
292 ; RV64I-MEDIUM-NEXT: addi a0, zero, 2
293 ; RV64I-MEDIUM-NEXT: j .LBB1_8
294 ; RV64I-MEDIUM-NEXT: .LBB1_5: # %bb4
295 ; RV64I-MEDIUM-NEXT: addi a0, zero, 1
296 ; RV64I-MEDIUM-NEXT: j .LBB1_8
297 ; RV64I-MEDIUM-NEXT: .LBB1_6: # %bb5
298 ; RV64I-MEDIUM-NEXT: addi a0, zero, 100
299 ; RV64I-MEDIUM-NEXT: j .LBB1_8
300 ; RV64I-MEDIUM-NEXT: .LBB1_7: # %bb6
301 ; RV64I-MEDIUM-NEXT: addi a0, zero, 200
302 ; RV64I-MEDIUM-NEXT: .LBB1_8: # %exit
303 ; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
304 ; RV64I-MEDIUM-NEXT: .LBB1_9: # %exit
305 ; RV64I-MEDIUM-NEXT: ret
307 switch i32 %in, label %exit [
316 store i32 4, i32* %out
319 store i32 3, i32* %out
322 store i32 2, i32* %out
325 store i32 1, i32* %out
328 store i32 100, i32* %out
331 store i32 200, i32* %out