| blob | e30edbd5a388af98edbe46793ca30c5f3e4c62fd |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV32I
4 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefix=RV32B
6 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
7 ; RUN: | FileCheck %s -check-prefix=RV32ZBB
8 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp -verify-machineinstrs < %s \
9 ; RUN: | FileCheck %s -check-prefix=RV32ZBP
11 define i32 @andn_i32(i32 %a, i32 %b) nounwind {
12 ; RV32I-LABEL: andn_i32:
13 ; RV32I: # %bb.0:
14 ; RV32I-NEXT: not a1, a1
15 ; RV32I-NEXT: and a0, a1, a0
16 ; RV32I-NEXT: ret
17 ;
18 ; RV32B-LABEL: andn_i32:
19 ; RV32B: # %bb.0:
20 ; RV32B-NEXT: andn a0, a0, a1
21 ; RV32B-NEXT: ret
22 ;
23 ; RV32ZBB-LABEL: andn_i32:
24 ; RV32ZBB: # %bb.0:
25 ; RV32ZBB-NEXT: andn a0, a0, a1
26 ; RV32ZBB-NEXT: ret
27 ;
28 ; RV32ZBP-LABEL: andn_i32:
29 ; RV32ZBP: # %bb.0:
30 ; RV32ZBP-NEXT: andn a0, a0, a1
31 ; RV32ZBP-NEXT: ret
32 %neg = xor i32 %b, -1
33 %and = and i32 %neg, %a
34 ret i32 %and
35 }
37 define i64 @andn_i64(i64 %a, i64 %b) nounwind {
38 ; RV32I-LABEL: andn_i64:
39 ; RV32I: # %bb.0:
40 ; RV32I-NEXT: not a3, a3
41 ; RV32I-NEXT: not a2, a2
42 ; RV32I-NEXT: and a0, a2, a0
43 ; RV32I-NEXT: and a1, a3, a1
44 ; RV32I-NEXT: ret
45 ;
46 ; RV32B-LABEL: andn_i64:
47 ; RV32B: # %bb.0:
48 ; RV32B-NEXT: andn a0, a0, a2
49 ; RV32B-NEXT: andn a1, a1, a3
50 ; RV32B-NEXT: ret
51 ;
52 ; RV32ZBB-LABEL: andn_i64:
53 ; RV32ZBB: # %bb.0:
54 ; RV32ZBB-NEXT: andn a0, a0, a2
55 ; RV32ZBB-NEXT: andn a1, a1, a3
56 ; RV32ZBB-NEXT: ret
57 ;
58 ; RV32ZBP-LABEL: andn_i64:
59 ; RV32ZBP: # %bb.0:
60 ; RV32ZBP-NEXT: andn a0, a0, a2
61 ; RV32ZBP-NEXT: andn a1, a1, a3
62 ; RV32ZBP-NEXT: ret
63 %neg = xor i64 %b, -1
64 %and = and i64 %neg, %a
65 ret i64 %and
66 }
68 define i32 @orn_i32(i32 %a, i32 %b) nounwind {
69 ; RV32I-LABEL: orn_i32:
70 ; RV32I: # %bb.0:
71 ; RV32I-NEXT: not a1, a1
72 ; RV32I-NEXT: or a0, a1, a0
73 ; RV32I-NEXT: ret
74 ;
75 ; RV32B-LABEL: orn_i32:
76 ; RV32B: # %bb.0:
77 ; RV32B-NEXT: orn a0, a0, a1
78 ; RV32B-NEXT: ret
79 ;
80 ; RV32ZBB-LABEL: orn_i32:
81 ; RV32ZBB: # %bb.0:
82 ; RV32ZBB-NEXT: orn a0, a0, a1
83 ; RV32ZBB-NEXT: ret
84 ;
85 ; RV32ZBP-LABEL: orn_i32:
86 ; RV32ZBP: # %bb.0:
87 ; RV32ZBP-NEXT: orn a0, a0, a1
88 ; RV32ZBP-NEXT: ret
89 %neg = xor i32 %b, -1
90 %or = or i32 %neg, %a
91 ret i32 %or
92 }
94 define i64 @orn_i64(i64 %a, i64 %b) nounwind {
95 ; RV32I-LABEL: orn_i64:
96 ; RV32I: # %bb.0:
97 ; RV32I-NEXT: not a3, a3
98 ; RV32I-NEXT: not a2, a2
99 ; RV32I-NEXT: or a0, a2, a0
100 ; RV32I-NEXT: or a1, a3, a1
101 ; RV32I-NEXT: ret
102 ;
103 ; RV32B-LABEL: orn_i64:
104 ; RV32B: # %bb.0:
105 ; RV32B-NEXT: orn a0, a0, a2
106 ; RV32B-NEXT: orn a1, a1, a3
107 ; RV32B-NEXT: ret
108 ;
109 ; RV32ZBB-LABEL: orn_i64:
110 ; RV32ZBB: # %bb.0:
111 ; RV32ZBB-NEXT: orn a0, a0, a2
112 ; RV32ZBB-NEXT: orn a1, a1, a3
113 ; RV32ZBB-NEXT: ret
114 ;
115 ; RV32ZBP-LABEL: orn_i64:
116 ; RV32ZBP: # %bb.0:
117 ; RV32ZBP-NEXT: orn a0, a0, a2
118 ; RV32ZBP-NEXT: orn a1, a1, a3
119 ; RV32ZBP-NEXT: ret
120 %neg = xor i64 %b, -1
121 %or = or i64 %neg, %a
122 ret i64 %or
123 }
125 define i32 @xnor_i32(i32 %a, i32 %b) nounwind {
126 ; RV32I-LABEL: xnor_i32:
127 ; RV32I: # %bb.0:
128 ; RV32I-NEXT: xor a0, a0, a1
129 ; RV32I-NEXT: not a0, a0
130 ; RV32I-NEXT: ret
131 ;
132 ; RV32B-LABEL: xnor_i32:
133 ; RV32B: # %bb.0:
134 ; RV32B-NEXT: xnor a0, a0, a1
135 ; RV32B-NEXT: ret
136 ;
137 ; RV32ZBB-LABEL: xnor_i32:
138 ; RV32ZBB: # %bb.0:
139 ; RV32ZBB-NEXT: xnor a0, a0, a1
140 ; RV32ZBB-NEXT: ret
141 ;
142 ; RV32ZBP-LABEL: xnor_i32:
143 ; RV32ZBP: # %bb.0:
144 ; RV32ZBP-NEXT: xnor a0, a0, a1
145 ; RV32ZBP-NEXT: ret
146 %neg = xor i32 %a, -1
147 %xor = xor i32 %neg, %b
148 ret i32 %xor
149 }
151 define i64 @xnor_i64(i64 %a, i64 %b) nounwind {
152 ; RV32I-LABEL: xnor_i64:
153 ; RV32I: # %bb.0:
154 ; RV32I-NEXT: xor a1, a1, a3
155 ; RV32I-NEXT: xor a0, a0, a2
156 ; RV32I-NEXT: not a0, a0
157 ; RV32I-NEXT: not a1, a1
158 ; RV32I-NEXT: ret
159 ;
160 ; RV32B-LABEL: xnor_i64:
161 ; RV32B: # %bb.0:
162 ; RV32B-NEXT: xnor a0, a0, a2
163 ; RV32B-NEXT: xnor a1, a1, a3
164 ; RV32B-NEXT: ret
165 ;
166 ; RV32ZBB-LABEL: xnor_i64:
167 ; RV32ZBB: # %bb.0:
168 ; RV32ZBB-NEXT: xnor a0, a0, a2
169 ; RV32ZBB-NEXT: xnor a1, a1, a3
170 ; RV32ZBB-NEXT: ret
171 ;
172 ; RV32ZBP-LABEL: xnor_i64:
173 ; RV32ZBP: # %bb.0:
174 ; RV32ZBP-NEXT: xnor a0, a0, a2
175 ; RV32ZBP-NEXT: xnor a1, a1, a3
176 ; RV32ZBP-NEXT: ret
177 %neg = xor i64 %a, -1
178 %xor = xor i64 %neg, %b
179 ret i64 %xor
180 }
182 declare i32 @llvm.fshl.i32(i32, i32, i32)
184 define i32 @rol_i32(i32 %a, i32 %b) nounwind {
185 ; RV32I-LABEL: rol_i32:
186 ; RV32I: # %bb.0:
187 ; RV32I-NEXT: sll a2, a0, a1
188 ; RV32I-NEXT: neg a1, a1
189 ; RV32I-NEXT: srl a0, a0, a1
190 ; RV32I-NEXT: or a0, a2, a0
191 ; RV32I-NEXT: ret
192 ;
193 ; RV32B-LABEL: rol_i32:
194 ; RV32B: # %bb.0:
195 ; RV32B-NEXT: rol a0, a0, a1
196 ; RV32B-NEXT: ret
197 ;
198 ; RV32ZBB-LABEL: rol_i32:
199 ; RV32ZBB: # %bb.0:
200 ; RV32ZBB-NEXT: rol a0, a0, a1
201 ; RV32ZBB-NEXT: ret
202 ;
203 ; RV32ZBP-LABEL: rol_i32:
204 ; RV32ZBP: # %bb.0:
205 ; RV32ZBP-NEXT: rol a0, a0, a1
206 ; RV32ZBP-NEXT: ret
207 %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
208 ret i32 %or
209 }
211 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
212 ; don't have yet any matching bit manipulation instructions on RV32.
213 ; This test is presented here in case future expansions of the experimental-b
214 ; extension introduce instructions suitable for this pattern.
216 declare i64 @llvm.fshl.i64(i64, i64, i64)
218 define i64 @rol_i64(i64 %a, i64 %b) nounwind {
219 ; RV32I-LABEL: rol_i64:
220 ; RV32I: # %bb.0:
221 ; RV32I-NEXT: mv a7, a1
222 ; RV32I-NEXT: andi a1, a2, 63
223 ; RV32I-NEXT: addi t0, a1, -32
224 ; RV32I-NEXT: addi a6, zero, 31
225 ; RV32I-NEXT: bltz t0, .LBB7_2
226 ; RV32I-NEXT: # %bb.1:
227 ; RV32I-NEXT: sll a1, a0, t0
228 ; RV32I-NEXT: j .LBB7_3
229 ; RV32I-NEXT: .LBB7_2:
230 ; RV32I-NEXT: sll a3, a7, a2
231 ; RV32I-NEXT: sub a1, a6, a1
232 ; RV32I-NEXT: srli a4, a0, 1
233 ; RV32I-NEXT: srl a1, a4, a1
234 ; RV32I-NEXT: or a1, a3, a1
235 ; RV32I-NEXT: .LBB7_3:
236 ; RV32I-NEXT: neg a5, a2
237 ; RV32I-NEXT: andi a3, a5, 63
238 ; RV32I-NEXT: addi a4, a3, -32
239 ; RV32I-NEXT: bltz a4, .LBB7_5
240 ; RV32I-NEXT: # %bb.4:
241 ; RV32I-NEXT: srl a3, a7, a4
242 ; RV32I-NEXT: bltz t0, .LBB7_6
243 ; RV32I-NEXT: j .LBB7_7
244 ; RV32I-NEXT: .LBB7_5:
245 ; RV32I-NEXT: srl a4, a7, a5
246 ; RV32I-NEXT: or a1, a1, a4
247 ; RV32I-NEXT: srl a4, a0, a5
248 ; RV32I-NEXT: sub a3, a6, a3
249 ; RV32I-NEXT: slli a5, a7, 1
250 ; RV32I-NEXT: sll a3, a5, a3
251 ; RV32I-NEXT: or a3, a4, a3
252 ; RV32I-NEXT: bgez t0, .LBB7_7
253 ; RV32I-NEXT: .LBB7_6:
254 ; RV32I-NEXT: sll a0, a0, a2
255 ; RV32I-NEXT: or a3, a3, a0
256 ; RV32I-NEXT: .LBB7_7:
257 ; RV32I-NEXT: mv a0, a3
258 ; RV32I-NEXT: ret
259 ;
260 ; RV32B-LABEL: rol_i64:
261 ; RV32B: # %bb.0:
262 ; RV32B-NEXT: sll a7, a1, a2
263 ; RV32B-NEXT: andi a4, a2, 63
264 ; RV32B-NEXT: addi a6, zero, 31
265 ; RV32B-NEXT: sub a5, a6, a4
266 ; RV32B-NEXT: srli a3, a0, 1
267 ; RV32B-NEXT: srl a3, a3, a5
268 ; RV32B-NEXT: or a7, a7, a3
269 ; RV32B-NEXT: addi t1, a4, -32
270 ; RV32B-NEXT: sll a5, a0, t1
271 ; RV32B-NEXT: slti a3, t1, 0
272 ; RV32B-NEXT: cmov a7, a3, a7, a5
273 ; RV32B-NEXT: neg a5, a2
274 ; RV32B-NEXT: srl t0, a1, a5
275 ; RV32B-NEXT: andi t2, a5, 63
276 ; RV32B-NEXT: addi a4, t2, -32
277 ; RV32B-NEXT: srai a3, a4, 31
278 ; RV32B-NEXT: and a3, a3, t0
279 ; RV32B-NEXT: or a7, a7, a3
280 ; RV32B-NEXT: srl t0, a0, a5
281 ; RV32B-NEXT: sub a5, a6, t2
282 ; RV32B-NEXT: slli a3, a1, 1
283 ; RV32B-NEXT: sll a3, a3, a5
284 ; RV32B-NEXT: or a3, t0, a3
285 ; RV32B-NEXT: srl a1, a1, a4
286 ; RV32B-NEXT: slti a4, a4, 0
287 ; RV32B-NEXT: cmov a1, a4, a3, a1
288 ; RV32B-NEXT: sll a0, a0, a2
289 ; RV32B-NEXT: srai a2, t1, 31
290 ; RV32B-NEXT: and a0, a2, a0
291 ; RV32B-NEXT: or a0, a0, a1
292 ; RV32B-NEXT: mv a1, a7
293 ; RV32B-NEXT: ret
294 ;
295 ; RV32ZBB-LABEL: rol_i64:
296 ; RV32ZBB: # %bb.0:
297 ; RV32ZBB-NEXT: mv a7, a1
298 ; RV32ZBB-NEXT: andi a1, a2, 63
299 ; RV32ZBB-NEXT: addi t0, a1, -32
300 ; RV32ZBB-NEXT: addi a6, zero, 31
301 ; RV32ZBB-NEXT: bltz t0, .LBB7_2
302 ; RV32ZBB-NEXT: # %bb.1:
303 ; RV32ZBB-NEXT: sll a1, a0, t0
304 ; RV32ZBB-NEXT: j .LBB7_3
305 ; RV32ZBB-NEXT: .LBB7_2:
306 ; RV32ZBB-NEXT: sll a3, a7, a2
307 ; RV32ZBB-NEXT: sub a1, a6, a1
308 ; RV32ZBB-NEXT: srli a4, a0, 1
309 ; RV32ZBB-NEXT: srl a1, a4, a1
310 ; RV32ZBB-NEXT: or a1, a3, a1
311 ; RV32ZBB-NEXT: .LBB7_3:
312 ; RV32ZBB-NEXT: neg a5, a2
313 ; RV32ZBB-NEXT: andi a3, a5, 63
314 ; RV32ZBB-NEXT: addi a4, a3, -32
315 ; RV32ZBB-NEXT: bltz a4, .LBB7_5
316 ; RV32ZBB-NEXT: # %bb.4:
317 ; RV32ZBB-NEXT: srl a3, a7, a4
318 ; RV32ZBB-NEXT: bltz t0, .LBB7_6
319 ; RV32ZBB-NEXT: j .LBB7_7
320 ; RV32ZBB-NEXT: .LBB7_5:
321 ; RV32ZBB-NEXT: srl a4, a7, a5
322 ; RV32ZBB-NEXT: or a1, a1, a4
323 ; RV32ZBB-NEXT: srl a4, a0, a5
324 ; RV32ZBB-NEXT: sub a3, a6, a3
325 ; RV32ZBB-NEXT: slli a5, a7, 1
326 ; RV32ZBB-NEXT: sll a3, a5, a3
327 ; RV32ZBB-NEXT: or a3, a4, a3
328 ; RV32ZBB-NEXT: bgez t0, .LBB7_7
329 ; RV32ZBB-NEXT: .LBB7_6:
330 ; RV32ZBB-NEXT: sll a0, a0, a2
331 ; RV32ZBB-NEXT: or a3, a3, a0
332 ; RV32ZBB-NEXT: .LBB7_7:
333 ; RV32ZBB-NEXT: mv a0, a3
334 ; RV32ZBB-NEXT: ret
335 ;
336 ; RV32ZBP-LABEL: rol_i64:
337 ; RV32ZBP: # %bb.0:
338 ; RV32ZBP-NEXT: mv a7, a1
339 ; RV32ZBP-NEXT: andi a1, a2, 63
340 ; RV32ZBP-NEXT: addi t0, a1, -32
341 ; RV32ZBP-NEXT: addi a6, zero, 31
342 ; RV32ZBP-NEXT: bltz t0, .LBB7_2
343 ; RV32ZBP-NEXT: # %bb.1:
344 ; RV32ZBP-NEXT: sll a1, a0, t0
345 ; RV32ZBP-NEXT: j .LBB7_3
346 ; RV32ZBP-NEXT: .LBB7_2:
347 ; RV32ZBP-NEXT: sll a3, a7, a2
348 ; RV32ZBP-NEXT: sub a1, a6, a1
349 ; RV32ZBP-NEXT: srli a4, a0, 1
350 ; RV32ZBP-NEXT: srl a1, a4, a1
351 ; RV32ZBP-NEXT: or a1, a3, a1
352 ; RV32ZBP-NEXT: .LBB7_3:
353 ; RV32ZBP-NEXT: neg a5, a2
354 ; RV32ZBP-NEXT: andi a3, a5, 63
355 ; RV32ZBP-NEXT: addi a4, a3, -32
356 ; RV32ZBP-NEXT: bltz a4, .LBB7_5
357 ; RV32ZBP-NEXT: # %bb.4:
358 ; RV32ZBP-NEXT: srl a3, a7, a4
359 ; RV32ZBP-NEXT: bltz t0, .LBB7_6
360 ; RV32ZBP-NEXT: j .LBB7_7
361 ; RV32ZBP-NEXT: .LBB7_5:
362 ; RV32ZBP-NEXT: srl a4, a7, a5
363 ; RV32ZBP-NEXT: or a1, a1, a4
364 ; RV32ZBP-NEXT: srl a4, a0, a5
365 ; RV32ZBP-NEXT: sub a3, a6, a3
366 ; RV32ZBP-NEXT: slli a5, a7, 1
367 ; RV32ZBP-NEXT: sll a3, a5, a3
368 ; RV32ZBP-NEXT: or a3, a4, a3
369 ; RV32ZBP-NEXT: bgez t0, .LBB7_7
370 ; RV32ZBP-NEXT: .LBB7_6:
371 ; RV32ZBP-NEXT: sll a0, a0, a2
372 ; RV32ZBP-NEXT: or a3, a3, a0
373 ; RV32ZBP-NEXT: .LBB7_7:
374 ; RV32ZBP-NEXT: mv a0, a3
375 ; RV32ZBP-NEXT: ret
376 %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
377 ret i64 %or
378 }
380 declare i32 @llvm.fshr.i32(i32, i32, i32)
382 define i32 @ror_i32(i32 %a, i32 %b) nounwind {
383 ; RV32I-LABEL: ror_i32:
384 ; RV32I: # %bb.0:
385 ; RV32I-NEXT: srl a2, a0, a1
386 ; RV32I-NEXT: neg a1, a1
387 ; RV32I-NEXT: sll a0, a0, a1
388 ; RV32I-NEXT: or a0, a2, a0
389 ; RV32I-NEXT: ret
390 ;
391 ; RV32B-LABEL: ror_i32:
392 ; RV32B: # %bb.0:
393 ; RV32B-NEXT: ror a0, a0, a1
394 ; RV32B-NEXT: ret
395 ;
396 ; RV32ZBB-LABEL: ror_i32:
397 ; RV32ZBB: # %bb.0:
398 ; RV32ZBB-NEXT: ror a0, a0, a1
399 ; RV32ZBB-NEXT: ret
400 ;
401 ; RV32ZBP-LABEL: ror_i32:
402 ; RV32ZBP: # %bb.0:
403 ; RV32ZBP-NEXT: ror a0, a0, a1
404 ; RV32ZBP-NEXT: ret
405 %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
406 ret i32 %or
407 }
409 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
410 ; don't have yet any matching bit manipulation instructions on RV32.
411 ; This test is presented here in case future expansions of the experimental-b
412 ; extension introduce instructions suitable for this pattern.
414 declare i64 @llvm.fshr.i64(i64, i64, i64)
416 define i64 @ror_i64(i64 %a, i64 %b) nounwind {
417 ; RV32I-LABEL: ror_i64:
418 ; RV32I: # %bb.0:
419 ; RV32I-NEXT: mv t0, a0
420 ; RV32I-NEXT: andi a0, a2, 63
421 ; RV32I-NEXT: addi a7, a0, -32
422 ; RV32I-NEXT: addi a6, zero, 31
423 ; RV32I-NEXT: bltz a7, .LBB9_2
424 ; RV32I-NEXT: # %bb.1:
425 ; RV32I-NEXT: srl a0, a1, a7
426 ; RV32I-NEXT: j .LBB9_3
427 ; RV32I-NEXT: .LBB9_2:
428 ; RV32I-NEXT: srl a3, t0, a2
429 ; RV32I-NEXT: sub a0, a6, a0
430 ; RV32I-NEXT: slli a4, a1, 1
431 ; RV32I-NEXT: sll a0, a4, a0
432 ; RV32I-NEXT: or a0, a3, a0
433 ; RV32I-NEXT: .LBB9_3:
434 ; RV32I-NEXT: neg a5, a2
435 ; RV32I-NEXT: andi a4, a5, 63
436 ; RV32I-NEXT: addi a3, a4, -32
437 ; RV32I-NEXT: bltz a3, .LBB9_5
438 ; RV32I-NEXT: # %bb.4:
439 ; RV32I-NEXT: sll a3, t0, a3
440 ; RV32I-NEXT: bltz a7, .LBB9_6
441 ; RV32I-NEXT: j .LBB9_7
442 ; RV32I-NEXT: .LBB9_5:
443 ; RV32I-NEXT: sll a3, t0, a5
444 ; RV32I-NEXT: or a0, a0, a3
445 ; RV32I-NEXT: sll a3, a1, a5
446 ; RV32I-NEXT: sub a4, a6, a4
447 ; RV32I-NEXT: srli a5, t0, 1
448 ; RV32I-NEXT: srl a4, a5, a4
449 ; RV32I-NEXT: or a3, a3, a4
450 ; RV32I-NEXT: bgez a7, .LBB9_7
451 ; RV32I-NEXT: .LBB9_6:
452 ; RV32I-NEXT: srl a1, a1, a2
453 ; RV32I-NEXT: or a3, a3, a1
454 ; RV32I-NEXT: .LBB9_7:
455 ; RV32I-NEXT: mv a1, a3
456 ; RV32I-NEXT: ret
457 ;
458 ; RV32B-LABEL: ror_i64:
459 ; RV32B: # %bb.0:
460 ; RV32B-NEXT: srl a7, a0, a2
461 ; RV32B-NEXT: andi a4, a2, 63
462 ; RV32B-NEXT: addi a6, zero, 31
463 ; RV32B-NEXT: sub a5, a6, a4
464 ; RV32B-NEXT: slli a3, a1, 1
465 ; RV32B-NEXT: sll a3, a3, a5
466 ; RV32B-NEXT: or a7, a7, a3
467 ; RV32B-NEXT: addi t1, a4, -32
468 ; RV32B-NEXT: srl a5, a1, t1
469 ; RV32B-NEXT: slti a3, t1, 0
470 ; RV32B-NEXT: cmov a7, a3, a7, a5
471 ; RV32B-NEXT: neg a5, a2
472 ; RV32B-NEXT: sll t0, a0, a5
473 ; RV32B-NEXT: andi t2, a5, 63
474 ; RV32B-NEXT: addi a4, t2, -32
475 ; RV32B-NEXT: srai a3, a4, 31
476 ; RV32B-NEXT: and a3, a3, t0
477 ; RV32B-NEXT: or a7, a7, a3
478 ; RV32B-NEXT: sll t0, a1, a5
479 ; RV32B-NEXT: sub a5, a6, t2
480 ; RV32B-NEXT: srli a3, a0, 1
481 ; RV32B-NEXT: srl a3, a3, a5
482 ; RV32B-NEXT: or a3, t0, a3
483 ; RV32B-NEXT: sll a0, a0, a4
484 ; RV32B-NEXT: slti a4, a4, 0
485 ; RV32B-NEXT: cmov a0, a4, a3, a0
486 ; RV32B-NEXT: srl a1, a1, a2
487 ; RV32B-NEXT: srai a2, t1, 31
488 ; RV32B-NEXT: and a1, a2, a1
489 ; RV32B-NEXT: or a1, a1, a0
490 ; RV32B-NEXT: mv a0, a7
491 ; RV32B-NEXT: ret
492 ;
493 ; RV32ZBB-LABEL: ror_i64:
494 ; RV32ZBB: # %bb.0:
495 ; RV32ZBB-NEXT: mv t0, a0
496 ; RV32ZBB-NEXT: andi a0, a2, 63
497 ; RV32ZBB-NEXT: addi a7, a0, -32
498 ; RV32ZBB-NEXT: addi a6, zero, 31
499 ; RV32ZBB-NEXT: bltz a7, .LBB9_2
500 ; RV32ZBB-NEXT: # %bb.1:
501 ; RV32ZBB-NEXT: srl a0, a1, a7
502 ; RV32ZBB-NEXT: j .LBB9_3
503 ; RV32ZBB-NEXT: .LBB9_2:
504 ; RV32ZBB-NEXT: srl a3, t0, a2
505 ; RV32ZBB-NEXT: sub a0, a6, a0
506 ; RV32ZBB-NEXT: slli a4, a1, 1
507 ; RV32ZBB-NEXT: sll a0, a4, a0
508 ; RV32ZBB-NEXT: or a0, a3, a0
509 ; RV32ZBB-NEXT: .LBB9_3:
510 ; RV32ZBB-NEXT: neg a5, a2
511 ; RV32ZBB-NEXT: andi a4, a5, 63
512 ; RV32ZBB-NEXT: addi a3, a4, -32
513 ; RV32ZBB-NEXT: bltz a3, .LBB9_5
514 ; RV32ZBB-NEXT: # %bb.4:
515 ; RV32ZBB-NEXT: sll a3, t0, a3
516 ; RV32ZBB-NEXT: bltz a7, .LBB9_6
517 ; RV32ZBB-NEXT: j .LBB9_7
518 ; RV32ZBB-NEXT: .LBB9_5:
519 ; RV32ZBB-NEXT: sll a3, t0, a5
520 ; RV32ZBB-NEXT: or a0, a0, a3
521 ; RV32ZBB-NEXT: sll a3, a1, a5
522 ; RV32ZBB-NEXT: sub a4, a6, a4
523 ; RV32ZBB-NEXT: srli a5, t0, 1
524 ; RV32ZBB-NEXT: srl a4, a5, a4
525 ; RV32ZBB-NEXT: or a3, a3, a4
526 ; RV32ZBB-NEXT: bgez a7, .LBB9_7
527 ; RV32ZBB-NEXT: .LBB9_6:
528 ; RV32ZBB-NEXT: srl a1, a1, a2
529 ; RV32ZBB-NEXT: or a3, a3, a1
530 ; RV32ZBB-NEXT: .LBB9_7:
531 ; RV32ZBB-NEXT: mv a1, a3
532 ; RV32ZBB-NEXT: ret
533 ;
534 ; RV32ZBP-LABEL: ror_i64:
535 ; RV32ZBP: # %bb.0:
536 ; RV32ZBP-NEXT: mv t0, a0
537 ; RV32ZBP-NEXT: andi a0, a2, 63
538 ; RV32ZBP-NEXT: addi a7, a0, -32
539 ; RV32ZBP-NEXT: addi a6, zero, 31
540 ; RV32ZBP-NEXT: bltz a7, .LBB9_2
541 ; RV32ZBP-NEXT: # %bb.1:
542 ; RV32ZBP-NEXT: srl a0, a1, a7
543 ; RV32ZBP-NEXT: j .LBB9_3
544 ; RV32ZBP-NEXT: .LBB9_2:
545 ; RV32ZBP-NEXT: srl a3, t0, a2
546 ; RV32ZBP-NEXT: sub a0, a6, a0
547 ; RV32ZBP-NEXT: slli a4, a1, 1
548 ; RV32ZBP-NEXT: sll a0, a4, a0
549 ; RV32ZBP-NEXT: or a0, a3, a0
550 ; RV32ZBP-NEXT: .LBB9_3:
551 ; RV32ZBP-NEXT: neg a5, a2
552 ; RV32ZBP-NEXT: andi a4, a5, 63
553 ; RV32ZBP-NEXT: addi a3, a4, -32
554 ; RV32ZBP-NEXT: bltz a3, .LBB9_5
555 ; RV32ZBP-NEXT: # %bb.4:
556 ; RV32ZBP-NEXT: sll a3, t0, a3
557 ; RV32ZBP-NEXT: bltz a7, .LBB9_6
558 ; RV32ZBP-NEXT: j .LBB9_7
559 ; RV32ZBP-NEXT: .LBB9_5:
560 ; RV32ZBP-NEXT: sll a3, t0, a5
561 ; RV32ZBP-NEXT: or a0, a0, a3
562 ; RV32ZBP-NEXT: sll a3, a1, a5
563 ; RV32ZBP-NEXT: sub a4, a6, a4
564 ; RV32ZBP-NEXT: srli a5, t0, 1
565 ; RV32ZBP-NEXT: srl a4, a5, a4
566 ; RV32ZBP-NEXT: or a3, a3, a4
567 ; RV32ZBP-NEXT: bgez a7, .LBB9_7
568 ; RV32ZBP-NEXT: .LBB9_6:
569 ; RV32ZBP-NEXT: srl a1, a1, a2
570 ; RV32ZBP-NEXT: or a3, a3, a1
571 ; RV32ZBP-NEXT: .LBB9_7:
572 ; RV32ZBP-NEXT: mv a1, a3
573 ; RV32ZBP-NEXT: ret
574 %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
575 ret i64 %or
576 }
578 define i32 @rori_i32_fshl(i32 %a) nounwind {
579 ; RV32I-LABEL: rori_i32_fshl:
580 ; RV32I: # %bb.0:
581 ; RV32I-NEXT: srli a1, a0, 1
582 ; RV32I-NEXT: slli a0, a0, 31
583 ; RV32I-NEXT: or a0, a0, a1
584 ; RV32I-NEXT: ret
585 ;
586 ; RV32B-LABEL: rori_i32_fshl:
587 ; RV32B: # %bb.0:
588 ; RV32B-NEXT: rori a0, a0, 1
589 ; RV32B-NEXT: ret
590 ;
591 ; RV32ZBB-LABEL: rori_i32_fshl:
592 ; RV32ZBB: # %bb.0:
593 ; RV32ZBB-NEXT: rori a0, a0, 1
594 ; RV32ZBB-NEXT: ret
595 ;
596 ; RV32ZBP-LABEL: rori_i32_fshl:
597 ; RV32ZBP: # %bb.0:
598 ; RV32ZBP-NEXT: rori a0, a0, 1
599 ; RV32ZBP-NEXT: ret
600 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)
601 ret i32 %1
602 }
604 define i32 @rori_i32_fshr(i32 %a) nounwind {
605 ; RV32I-LABEL: rori_i32_fshr:
606 ; RV32I: # %bb.0:
607 ; RV32I-NEXT: slli a1, a0, 1
608 ; RV32I-NEXT: srli a0, a0, 31
609 ; RV32I-NEXT: or a0, a0, a1
610 ; RV32I-NEXT: ret
611 ;
612 ; RV32B-LABEL: rori_i32_fshr:
613 ; RV32B: # %bb.0:
614 ; RV32B-NEXT: rori a0, a0, 31
615 ; RV32B-NEXT: ret
616 ;
617 ; RV32ZBB-LABEL: rori_i32_fshr:
618 ; RV32ZBB: # %bb.0:
619 ; RV32ZBB-NEXT: rori a0, a0, 31
620 ; RV32ZBB-NEXT: ret
621 ;
622 ; RV32ZBP-LABEL: rori_i32_fshr:
623 ; RV32ZBP: # %bb.0:
624 ; RV32ZBP-NEXT: rori a0, a0, 31
625 ; RV32ZBP-NEXT: ret
626 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
627 ret i32 %1
628 }
630 define i64 @rori_i64(i64 %a) nounwind {
631 ; RV32I-LABEL: rori_i64:
632 ; RV32I: # %bb.0:
633 ; RV32I-NEXT: slli a2, a1, 31
634 ; RV32I-NEXT: srli a3, a0, 1
635 ; RV32I-NEXT: or a2, a3, a2
636 ; RV32I-NEXT: srli a1, a1, 1
637 ; RV32I-NEXT: slli a0, a0, 31
638 ; RV32I-NEXT: or a1, a0, a1
639 ; RV32I-NEXT: mv a0, a2
640 ; RV32I-NEXT: ret
641 ;
642 ; RV32B-LABEL: rori_i64:
643 ; RV32B: # %bb.0:
644 ; RV32B-NEXT: fsri a2, a0, a1, 1
645 ; RV32B-NEXT: fsri a1, a1, a0, 1
646 ; RV32B-NEXT: mv a0, a2
647 ; RV32B-NEXT: ret
648 ;
649 ; RV32ZBB-LABEL: rori_i64:
650 ; RV32ZBB: # %bb.0:
651 ; RV32ZBB-NEXT: slli a2, a1, 31
652 ; RV32ZBB-NEXT: srli a3, a0, 1
653 ; RV32ZBB-NEXT: or a2, a3, a2
654 ; RV32ZBB-NEXT: srli a1, a1, 1
655 ; RV32ZBB-NEXT: slli a0, a0, 31
656 ; RV32ZBB-NEXT: or a1, a0, a1
657 ; RV32ZBB-NEXT: mv a0, a2
658 ; RV32ZBB-NEXT: ret
659 ;
660 ; RV32ZBP-LABEL: rori_i64:
661 ; RV32ZBP: # %bb.0:
662 ; RV32ZBP-NEXT: slli a2, a1, 31
663 ; RV32ZBP-NEXT: srli a3, a0, 1
664 ; RV32ZBP-NEXT: or a2, a3, a2
665 ; RV32ZBP-NEXT: srli a1, a1, 1
666 ; RV32ZBP-NEXT: slli a0, a0, 31
667 ; RV32ZBP-NEXT: or a1, a0, a1
668 ; RV32ZBP-NEXT: mv a0, a2
669 ; RV32ZBP-NEXT: ret
670 %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63)
671 ret i64 %1
672 }
674 define i64 @rori_i64_fshr(i64 %a) nounwind {
675 ; RV32I-LABEL: rori_i64_fshr:
676 ; RV32I: # %bb.0:
677 ; RV32I-NEXT: slli a2, a0, 1
678 ; RV32I-NEXT: srli a3, a1, 31
679 ; RV32I-NEXT: or a2, a3, a2
680 ; RV32I-NEXT: srli a0, a0, 31
681 ; RV32I-NEXT: slli a1, a1, 1
682 ; RV32I-NEXT: or a1, a1, a0
683 ; RV32I-NEXT: mv a0, a2
684 ; RV32I-NEXT: ret
685 ;
686 ; RV32B-LABEL: rori_i64_fshr:
687 ; RV32B: # %bb.0:
688 ; RV32B-NEXT: fsri a2, a1, a0, 31
689 ; RV32B-NEXT: fsri a1, a0, a1, 31
690 ; RV32B-NEXT: mv a0, a2
691 ; RV32B-NEXT: ret
692 ;
693 ; RV32ZBB-LABEL: rori_i64_fshr:
694 ; RV32ZBB: # %bb.0:
695 ; RV32ZBB-NEXT: slli a2, a0, 1
696 ; RV32ZBB-NEXT: srli a3, a1, 31
697 ; RV32ZBB-NEXT: or a2, a3, a2
698 ; RV32ZBB-NEXT: srli a0, a0, 31
699 ; RV32ZBB-NEXT: slli a1, a1, 1
700 ; RV32ZBB-NEXT: or a1, a1, a0
701 ; RV32ZBB-NEXT: mv a0, a2
702 ; RV32ZBB-NEXT: ret
703 ;
704 ; RV32ZBP-LABEL: rori_i64_fshr:
705 ; RV32ZBP: # %bb.0:
706 ; RV32ZBP-NEXT: slli a2, a0, 1
707 ; RV32ZBP-NEXT: srli a3, a1, 31
708 ; RV32ZBP-NEXT: or a2, a3, a2
709 ; RV32ZBP-NEXT: srli a0, a0, 31
710 ; RV32ZBP-NEXT: slli a1, a1, 1
711 ; RV32ZBP-NEXT: or a1, a1, a0
712 ; RV32ZBP-NEXT: mv a0, a2
713 ; RV32ZBP-NEXT: ret
714 %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
715 ret i64 %1
716 }
718 define i8 @srli_i8(i8 %a) nounwind {
719 ; RV32I-LABEL: srli_i8:
720 ; RV32I: # %bb.0:
721 ; RV32I-NEXT: andi a0, a0, 192
722 ; RV32I-NEXT: srli a0, a0, 6
723 ; RV32I-NEXT: ret
724 ;
725 ; RV32B-LABEL: srli_i8:
726 ; RV32B: # %bb.0:
727 ; RV32B-NEXT: andi a0, a0, 192
728 ; RV32B-NEXT: srli a0, a0, 6
729 ; RV32B-NEXT: ret
730 ;
731 ; RV32ZBB-LABEL: srli_i8:
732 ; RV32ZBB: # %bb.0:
733 ; RV32ZBB-NEXT: andi a0, a0, 192
734 ; RV32ZBB-NEXT: srli a0, a0, 6
735 ; RV32ZBB-NEXT: ret
736 ;
737 ; RV32ZBP-LABEL: srli_i8:
738 ; RV32ZBP: # %bb.0:
739 ; RV32ZBP-NEXT: andi a0, a0, 192
740 ; RV32ZBP-NEXT: srli a0, a0, 6
741 ; RV32ZBP-NEXT: ret
742 %1 = lshr i8 %a, 6
743 ret i8 %1
744 }
746 define i8 @srai_i8(i8 %a) nounwind {
747 ; RV32I-LABEL: srai_i8:
748 ; RV32I: # %bb.0:
749 ; RV32I-NEXT: slli a0, a0, 24
750 ; RV32I-NEXT: srai a0, a0, 29
751 ; RV32I-NEXT: ret
752 ;
753 ; RV32B-LABEL: srai_i8:
754 ; RV32B: # %bb.0:
755 ; RV32B-NEXT: sext.b a0, a0
756 ; RV32B-NEXT: srai a0, a0, 5
757 ; RV32B-NEXT: ret
758 ;
759 ; RV32ZBB-LABEL: srai_i8:
760 ; RV32ZBB: # %bb.0:
761 ; RV32ZBB-NEXT: sext.b a0, a0
762 ; RV32ZBB-NEXT: srai a0, a0, 5
763 ; RV32ZBB-NEXT: ret
764 ;
765 ; RV32ZBP-LABEL: srai_i8:
766 ; RV32ZBP: # %bb.0:
767 ; RV32ZBP-NEXT: slli a0, a0, 24
768 ; RV32ZBP-NEXT: srai a0, a0, 29
769 ; RV32ZBP-NEXT: ret
770 %1 = ashr i8 %a, 5
771 ret i8 %1
772 }
774 define i16 @srli_i16(i16 %a) nounwind {
775 ; RV32I-LABEL: srli_i16:
776 ; RV32I: # %bb.0:
777 ; RV32I-NEXT: slli a0, a0, 16
778 ; RV32I-NEXT: srli a0, a0, 22
779 ; RV32I-NEXT: ret
780 ;
781 ; RV32B-LABEL: srli_i16:
782 ; RV32B: # %bb.0:
783 ; RV32B-NEXT: zext.h a0, a0
784 ; RV32B-NEXT: srli a0, a0, 6
785 ; RV32B-NEXT: ret
786 ;
787 ; RV32ZBB-LABEL: srli_i16:
788 ; RV32ZBB: # %bb.0:
789 ; RV32ZBB-NEXT: zext.h a0, a0
790 ; RV32ZBB-NEXT: srli a0, a0, 6
791 ; RV32ZBB-NEXT: ret
792 ;
793 ; RV32ZBP-LABEL: srli_i16:
794 ; RV32ZBP: # %bb.0:
795 ; RV32ZBP-NEXT: zext.h a0, a0
796 ; RV32ZBP-NEXT: srli a0, a0, 6
797 ; RV32ZBP-NEXT: ret
798 %1 = lshr i16 %a, 6
799 ret i16 %1
800 }
802 define i16 @srai_i16(i16 %a) nounwind {
803 ; RV32I-LABEL: srai_i16:
804 ; RV32I: # %bb.0:
805 ; RV32I-NEXT: slli a0, a0, 16
806 ; RV32I-NEXT: srai a0, a0, 25
807 ; RV32I-NEXT: ret
808 ;
809 ; RV32B-LABEL: srai_i16:
810 ; RV32B: # %bb.0:
811 ; RV32B-NEXT: sext.h a0, a0
812 ; RV32B-NEXT: srai a0, a0, 9
813 ; RV32B-NEXT: ret
814 ;
815 ; RV32ZBB-LABEL: srai_i16:
816 ; RV32ZBB: # %bb.0:
817 ; RV32ZBB-NEXT: sext.h a0, a0
818 ; RV32ZBB-NEXT: srai a0, a0, 9
819 ; RV32ZBB-NEXT: ret
820 ;
821 ; RV32ZBP-LABEL: srai_i16:
822 ; RV32ZBP: # %bb.0:
823 ; RV32ZBP-NEXT: slli a0, a0, 16
824 ; RV32ZBP-NEXT: srai a0, a0, 25
825 ; RV32ZBP-NEXT: ret
826 %1 = ashr i16 %a, 9
827 ret i16 %1
828 }