| blob | 94acffac7a8159d18e27323ee187629bfa329253 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
3 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
4 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt
5 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt
6 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
7 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
9 declare i4 @llvm.ssub.sat.i4(i4, i4)
10 declare i8 @llvm.ssub.sat.i8(i8, i8)
11 declare i16 @llvm.ssub.sat.i16(i16, i16)
12 declare i32 @llvm.ssub.sat.i32(i32, i32)
13 declare i64 @llvm.ssub.sat.i64(i64, i64)
15 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
16 ; RV32I-LABEL: func:
17 ; RV32I: # %bb.0:
18 ; RV32I-NEXT: mv a2, a0
19 ; RV32I-NEXT: sgtz a3, a1
20 ; RV32I-NEXT: sub a0, a0, a1
21 ; RV32I-NEXT: slt a1, a0, a2
22 ; RV32I-NEXT: beq a3, a1, .LBB0_2
23 ; RV32I-NEXT: # %bb.1:
24 ; RV32I-NEXT: srai a0, a0, 31
25 ; RV32I-NEXT: lui a1, 524288
26 ; RV32I-NEXT: xor a0, a0, a1
27 ; RV32I-NEXT: .LBB0_2:
28 ; RV32I-NEXT: ret
29 ;
30 ; RV64I-LABEL: func:
31 ; RV64I: # %bb.0:
32 ; RV64I-NEXT: sub a0, a0, a1
33 ; RV64I-NEXT: lui a1, 524288
34 ; RV64I-NEXT: addiw a2, a1, -1
35 ; RV64I-NEXT: bge a0, a2, .LBB0_3
36 ; RV64I-NEXT: # %bb.1:
37 ; RV64I-NEXT: bge a1, a0, .LBB0_4
38 ; RV64I-NEXT: .LBB0_2:
39 ; RV64I-NEXT: ret
40 ; RV64I-NEXT: .LBB0_3:
41 ; RV64I-NEXT: mv a0, a2
42 ; RV64I-NEXT: blt a1, a0, .LBB0_2
43 ; RV64I-NEXT: .LBB0_4:
44 ; RV64I-NEXT: lui a0, 524288
45 ; RV64I-NEXT: ret
46 ;
47 ; RV32IZbbNOZbt-LABEL: func:
48 ; RV32IZbbNOZbt: # %bb.0:
49 ; RV32IZbbNOZbt-NEXT: mv a2, a0
50 ; RV32IZbbNOZbt-NEXT: sgtz a3, a1
51 ; RV32IZbbNOZbt-NEXT: sub a0, a0, a1
52 ; RV32IZbbNOZbt-NEXT: slt a1, a0, a2
53 ; RV32IZbbNOZbt-NEXT: beq a3, a1, .LBB0_2
54 ; RV32IZbbNOZbt-NEXT: # %bb.1:
55 ; RV32IZbbNOZbt-NEXT: srai a0, a0, 31
56 ; RV32IZbbNOZbt-NEXT: lui a1, 524288
57 ; RV32IZbbNOZbt-NEXT: xor a0, a0, a1
58 ; RV32IZbbNOZbt-NEXT: .LBB0_2:
59 ; RV32IZbbNOZbt-NEXT: ret
60 ;
61 ; RV64IZbb-LABEL: func:
62 ; RV64IZbb: # %bb.0:
63 ; RV64IZbb-NEXT: sub a0, a0, a1
64 ; RV64IZbb-NEXT: lui a1, 524288
65 ; RV64IZbb-NEXT: addiw a2, a1, -1
66 ; RV64IZbb-NEXT: min a0, a0, a2
67 ; RV64IZbb-NEXT: max a0, a0, a1
68 ; RV64IZbb-NEXT: ret
69 ;
70 ; RV32IZbbZbt-LABEL: func:
71 ; RV32IZbbZbt: # %bb.0:
72 ; RV32IZbbZbt-NEXT: sgtz a2, a1
73 ; RV32IZbbZbt-NEXT: sub a1, a0, a1
74 ; RV32IZbbZbt-NEXT: slt a0, a1, a0
75 ; RV32IZbbZbt-NEXT: xor a0, a2, a0
76 ; RV32IZbbZbt-NEXT: srai a2, a1, 31
77 ; RV32IZbbZbt-NEXT: lui a3, 524288
78 ; RV32IZbbZbt-NEXT: xor a2, a2, a3
79 ; RV32IZbbZbt-NEXT: cmov a0, a0, a2, a1
80 ; RV32IZbbZbt-NEXT: ret
81 %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
82 ret i32 %tmp;
83 }
85 define i64 @func2(i64 %x, i64 %y) nounwind {
86 ; RV32I-LABEL: func2:
87 ; RV32I: # %bb.0:
88 ; RV32I-NEXT: mv a4, a1
89 ; RV32I-NEXT: sltu a1, a0, a2
90 ; RV32I-NEXT: sub a5, a4, a3
91 ; RV32I-NEXT: sub a1, a5, a1
92 ; RV32I-NEXT: xor a5, a4, a1
93 ; RV32I-NEXT: xor a3, a4, a3
94 ; RV32I-NEXT: and a3, a3, a5
95 ; RV32I-NEXT: bltz a3, .LBB1_2
96 ; RV32I-NEXT: # %bb.1:
97 ; RV32I-NEXT: sub a0, a0, a2
98 ; RV32I-NEXT: ret
99 ; RV32I-NEXT: .LBB1_2:
100 ; RV32I-NEXT: srai a0, a1, 31
101 ; RV32I-NEXT: lui a1, 524288
102 ; RV32I-NEXT: xor a1, a0, a1
103 ; RV32I-NEXT: ret
104 ;
105 ; RV64I-LABEL: func2:
106 ; RV64I: # %bb.0:
107 ; RV64I-NEXT: mv a2, a0
108 ; RV64I-NEXT: sgtz a3, a1
109 ; RV64I-NEXT: sub a0, a0, a1
110 ; RV64I-NEXT: slt a1, a0, a2
111 ; RV64I-NEXT: beq a3, a1, .LBB1_2
112 ; RV64I-NEXT: # %bb.1:
113 ; RV64I-NEXT: srai a0, a0, 63
114 ; RV64I-NEXT: addi a1, zero, -1
115 ; RV64I-NEXT: slli a1, a1, 63
116 ; RV64I-NEXT: xor a0, a0, a1
117 ; RV64I-NEXT: .LBB1_2:
118 ; RV64I-NEXT: ret
119 ;
120 ; RV32IZbbNOZbt-LABEL: func2:
121 ; RV32IZbbNOZbt: # %bb.0:
122 ; RV32IZbbNOZbt-NEXT: mv a4, a1
123 ; RV32IZbbNOZbt-NEXT: sltu a1, a0, a2
124 ; RV32IZbbNOZbt-NEXT: sub a5, a4, a3
125 ; RV32IZbbNOZbt-NEXT: sub a1, a5, a1
126 ; RV32IZbbNOZbt-NEXT: xor a5, a4, a1
127 ; RV32IZbbNOZbt-NEXT: xor a3, a4, a3
128 ; RV32IZbbNOZbt-NEXT: and a3, a3, a5
129 ; RV32IZbbNOZbt-NEXT: bltz a3, .LBB1_2
130 ; RV32IZbbNOZbt-NEXT: # %bb.1:
131 ; RV32IZbbNOZbt-NEXT: sub a0, a0, a2
132 ; RV32IZbbNOZbt-NEXT: ret
133 ; RV32IZbbNOZbt-NEXT: .LBB1_2:
134 ; RV32IZbbNOZbt-NEXT: srai a0, a1, 31
135 ; RV32IZbbNOZbt-NEXT: lui a1, 524288
136 ; RV32IZbbNOZbt-NEXT: xor a1, a0, a1
137 ; RV32IZbbNOZbt-NEXT: ret
138 ;
139 ; RV64IZbbNOZbt-LABEL: func2:
140 ; RV64IZbbNOZbt: # %bb.0:
141 ; RV64IZbbNOZbt-NEXT: mv a2, a0
142 ; RV64IZbbNOZbt-NEXT: sgtz a3, a1
143 ; RV64IZbbNOZbt-NEXT: sub a0, a0, a1
144 ; RV64IZbbNOZbt-NEXT: slt a1, a0, a2
145 ; RV64IZbbNOZbt-NEXT: beq a3, a1, .LBB1_2
146 ; RV64IZbbNOZbt-NEXT: # %bb.1:
147 ; RV64IZbbNOZbt-NEXT: srai a0, a0, 63
148 ; RV64IZbbNOZbt-NEXT: addi a1, zero, -1
149 ; RV64IZbbNOZbt-NEXT: slli a1, a1, 63
150 ; RV64IZbbNOZbt-NEXT: xor a0, a0, a1
151 ; RV64IZbbNOZbt-NEXT: .LBB1_2:
152 ; RV64IZbbNOZbt-NEXT: ret
153 ;
154 ; RV32IZbbZbt-LABEL: func2:
155 ; RV32IZbbZbt: # %bb.0:
156 ; RV32IZbbZbt-NEXT: sltu a4, a0, a2
157 ; RV32IZbbZbt-NEXT: sub a5, a1, a3
158 ; RV32IZbbZbt-NEXT: sub a4, a5, a4
159 ; RV32IZbbZbt-NEXT: srai a6, a4, 31
160 ; RV32IZbbZbt-NEXT: lui a5, 524288
161 ; RV32IZbbZbt-NEXT: xor a7, a6, a5
162 ; RV32IZbbZbt-NEXT: xor a5, a1, a4
163 ; RV32IZbbZbt-NEXT: xor a1, a1, a3
164 ; RV32IZbbZbt-NEXT: and a1, a1, a5
165 ; RV32IZbbZbt-NEXT: slti a3, a1, 0
166 ; RV32IZbbZbt-NEXT: cmov a1, a3, a7, a4
167 ; RV32IZbbZbt-NEXT: sub a0, a0, a2
168 ; RV32IZbbZbt-NEXT: cmov a0, a3, a6, a0
169 ; RV32IZbbZbt-NEXT: ret
170 ;
171 ; RV64IZbbZbt-LABEL: func2:
172 ; RV64IZbbZbt: # %bb.0:
173 ; RV64IZbbZbt-NEXT: sgtz a2, a1
174 ; RV64IZbbZbt-NEXT: sub a1, a0, a1
175 ; RV64IZbbZbt-NEXT: slt a0, a1, a0
176 ; RV64IZbbZbt-NEXT: xor a0, a2, a0
177 ; RV64IZbbZbt-NEXT: srai a2, a1, 63
178 ; RV64IZbbZbt-NEXT: addi a3, zero, -1
179 ; RV64IZbbZbt-NEXT: slli a3, a3, 63
180 ; RV64IZbbZbt-NEXT: xor a2, a2, a3
181 ; RV64IZbbZbt-NEXT: cmov a0, a0, a2, a1
182 ; RV64IZbbZbt-NEXT: ret
183 %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
184 ret i64 %tmp;
185 }
187 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
188 ; RV32I-LABEL: func16:
189 ; RV32I: # %bb.0:
190 ; RV32I-NEXT: sub a0, a0, a1
191 ; RV32I-NEXT: lui a1, 8
192 ; RV32I-NEXT: addi a1, a1, -1
193 ; RV32I-NEXT: bge a0, a1, .LBB2_3
194 ; RV32I-NEXT: # %bb.1:
195 ; RV32I-NEXT: lui a1, 1048568
196 ; RV32I-NEXT: bge a1, a0, .LBB2_4
197 ; RV32I-NEXT: .LBB2_2:
198 ; RV32I-NEXT: ret
199 ; RV32I-NEXT: .LBB2_3:
200 ; RV32I-NEXT: mv a0, a1
201 ; RV32I-NEXT: lui a1, 1048568
202 ; RV32I-NEXT: blt a1, a0, .LBB2_2
203 ; RV32I-NEXT: .LBB2_4:
204 ; RV32I-NEXT: lui a0, 1048568
205 ; RV32I-NEXT: ret
206 ;
207 ; RV64I-LABEL: func16:
208 ; RV64I: # %bb.0:
209 ; RV64I-NEXT: sub a0, a0, a1
210 ; RV64I-NEXT: lui a1, 8
211 ; RV64I-NEXT: addiw a1, a1, -1
212 ; RV64I-NEXT: bge a0, a1, .LBB2_3
213 ; RV64I-NEXT: # %bb.1:
214 ; RV64I-NEXT: lui a1, 1048568
215 ; RV64I-NEXT: bge a1, a0, .LBB2_4
216 ; RV64I-NEXT: .LBB2_2:
217 ; RV64I-NEXT: ret
218 ; RV64I-NEXT: .LBB2_3:
219 ; RV64I-NEXT: mv a0, a1
220 ; RV64I-NEXT: lui a1, 1048568
221 ; RV64I-NEXT: blt a1, a0, .LBB2_2
222 ; RV64I-NEXT: .LBB2_4:
223 ; RV64I-NEXT: lui a0, 1048568
224 ; RV64I-NEXT: ret
225 ;
226 ; RV32IZbb-LABEL: func16:
227 ; RV32IZbb: # %bb.0:
228 ; RV32IZbb-NEXT: sub a0, a0, a1
229 ; RV32IZbb-NEXT: lui a1, 8
230 ; RV32IZbb-NEXT: addi a1, a1, -1
231 ; RV32IZbb-NEXT: min a0, a0, a1
232 ; RV32IZbb-NEXT: lui a1, 1048568
233 ; RV32IZbb-NEXT: max a0, a0, a1
234 ; RV32IZbb-NEXT: ret
235 ;
236 ; RV64IZbb-LABEL: func16:
237 ; RV64IZbb: # %bb.0:
238 ; RV64IZbb-NEXT: sub a0, a0, a1
239 ; RV64IZbb-NEXT: lui a1, 8
240 ; RV64IZbb-NEXT: addiw a1, a1, -1
241 ; RV64IZbb-NEXT: min a0, a0, a1
242 ; RV64IZbb-NEXT: lui a1, 1048568
243 ; RV64IZbb-NEXT: max a0, a0, a1
244 ; RV64IZbb-NEXT: ret
245 %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
246 ret i16 %tmp;
247 }
249 define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
250 ; RV32I-LABEL: func8:
251 ; RV32I: # %bb.0:
252 ; RV32I-NEXT: sub a0, a0, a1
253 ; RV32I-NEXT: addi a1, zero, 127
254 ; RV32I-NEXT: bge a0, a1, .LBB3_3
255 ; RV32I-NEXT: # %bb.1:
256 ; RV32I-NEXT: addi a1, zero, -128
257 ; RV32I-NEXT: bge a1, a0, .LBB3_4
258 ; RV32I-NEXT: .LBB3_2:
259 ; RV32I-NEXT: ret
260 ; RV32I-NEXT: .LBB3_3:
261 ; RV32I-NEXT: addi a0, zero, 127
262 ; RV32I-NEXT: addi a1, zero, -128
263 ; RV32I-NEXT: blt a1, a0, .LBB3_2
264 ; RV32I-NEXT: .LBB3_4:
265 ; RV32I-NEXT: addi a0, zero, -128
266 ; RV32I-NEXT: ret
267 ;
268 ; RV64I-LABEL: func8:
269 ; RV64I: # %bb.0:
270 ; RV64I-NEXT: sub a0, a0, a1
271 ; RV64I-NEXT: addi a1, zero, 127
272 ; RV64I-NEXT: bge a0, a1, .LBB3_3
273 ; RV64I-NEXT: # %bb.1:
274 ; RV64I-NEXT: addi a1, zero, -128
275 ; RV64I-NEXT: bge a1, a0, .LBB3_4
276 ; RV64I-NEXT: .LBB3_2:
277 ; RV64I-NEXT: ret
278 ; RV64I-NEXT: .LBB3_3:
279 ; RV64I-NEXT: addi a0, zero, 127
280 ; RV64I-NEXT: addi a1, zero, -128
281 ; RV64I-NEXT: blt a1, a0, .LBB3_2
282 ; RV64I-NEXT: .LBB3_4:
283 ; RV64I-NEXT: addi a0, zero, -128
284 ; RV64I-NEXT: ret
285 ;
286 ; RV32IZbb-LABEL: func8:
287 ; RV32IZbb: # %bb.0:
288 ; RV32IZbb-NEXT: sub a0, a0, a1
289 ; RV32IZbb-NEXT: addi a1, zero, 127
290 ; RV32IZbb-NEXT: min a0, a0, a1
291 ; RV32IZbb-NEXT: addi a1, zero, -128
292 ; RV32IZbb-NEXT: max a0, a0, a1
293 ; RV32IZbb-NEXT: ret
294 ;
295 ; RV64IZbb-LABEL: func8:
296 ; RV64IZbb: # %bb.0:
297 ; RV64IZbb-NEXT: sub a0, a0, a1
298 ; RV64IZbb-NEXT: addi a1, zero, 127
299 ; RV64IZbb-NEXT: min a0, a0, a1
300 ; RV64IZbb-NEXT: addi a1, zero, -128
301 ; RV64IZbb-NEXT: max a0, a0, a1
302 ; RV64IZbb-NEXT: ret
303 %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
304 ret i8 %tmp;
305 }
307 define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
308 ; RV32I-LABEL: func3:
309 ; RV32I: # %bb.0:
310 ; RV32I-NEXT: sub a0, a0, a1
311 ; RV32I-NEXT: addi a1, zero, 7
312 ; RV32I-NEXT: bge a0, a1, .LBB4_3
313 ; RV32I-NEXT: # %bb.1:
314 ; RV32I-NEXT: addi a1, zero, -8
315 ; RV32I-NEXT: bge a1, a0, .LBB4_4
316 ; RV32I-NEXT: .LBB4_2:
317 ; RV32I-NEXT: ret
318 ; RV32I-NEXT: .LBB4_3:
319 ; RV32I-NEXT: addi a0, zero, 7
320 ; RV32I-NEXT: addi a1, zero, -8
321 ; RV32I-NEXT: blt a1, a0, .LBB4_2
322 ; RV32I-NEXT: .LBB4_4:
323 ; RV32I-NEXT: addi a0, zero, -8
324 ; RV32I-NEXT: ret
325 ;
326 ; RV64I-LABEL: func3:
327 ; RV64I: # %bb.0:
328 ; RV64I-NEXT: sub a0, a0, a1
329 ; RV64I-NEXT: addi a1, zero, 7
330 ; RV64I-NEXT: bge a0, a1, .LBB4_3
331 ; RV64I-NEXT: # %bb.1:
332 ; RV64I-NEXT: addi a1, zero, -8
333 ; RV64I-NEXT: bge a1, a0, .LBB4_4
334 ; RV64I-NEXT: .LBB4_2:
335 ; RV64I-NEXT: ret
336 ; RV64I-NEXT: .LBB4_3:
337 ; RV64I-NEXT: addi a0, zero, 7
338 ; RV64I-NEXT: addi a1, zero, -8
339 ; RV64I-NEXT: blt a1, a0, .LBB4_2
340 ; RV64I-NEXT: .LBB4_4:
341 ; RV64I-NEXT: addi a0, zero, -8
342 ; RV64I-NEXT: ret
343 ;
344 ; RV32IZbb-LABEL: func3:
345 ; RV32IZbb: # %bb.0:
346 ; RV32IZbb-NEXT: sub a0, a0, a1
347 ; RV32IZbb-NEXT: addi a1, zero, 7
348 ; RV32IZbb-NEXT: min a0, a0, a1
349 ; RV32IZbb-NEXT: addi a1, zero, -8
350 ; RV32IZbb-NEXT: max a0, a0, a1
351 ; RV32IZbb-NEXT: ret
352 ;
353 ; RV64IZbb-LABEL: func3:
354 ; RV64IZbb: # %bb.0:
355 ; RV64IZbb-NEXT: sub a0, a0, a1
356 ; RV64IZbb-NEXT: addi a1, zero, 7
357 ; RV64IZbb-NEXT: min a0, a0, a1
358 ; RV64IZbb-NEXT: addi a1, zero, -8
359 ; RV64IZbb-NEXT: max a0, a0, a1
360 ; RV64IZbb-NEXT: ret
361 %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
362 ret i4 %tmp;
363 }