| blob | e34845807c3f225f60ae4e48262efbae8d72ba97 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
6 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7 ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
11 define i32 @fold_urem_positive_odd(i32 %x) nounwind {
12 ; RV32I-LABEL: fold_urem_positive_odd:
13 ; RV32I: # %bb.0:
14 ; RV32I-NEXT: addi sp, sp, -16
15 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
16 ; RV32I-NEXT: addi a1, zero, 95
17 ; RV32I-NEXT: call __umodsi3@plt
18 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
19 ; RV32I-NEXT: addi sp, sp, 16
20 ; RV32I-NEXT: ret
21 ;
22 ; RV32IM-LABEL: fold_urem_positive_odd:
23 ; RV32IM: # %bb.0:
24 ; RV32IM-NEXT: lui a1, 364242
25 ; RV32IM-NEXT: addi a1, a1, 777
26 ; RV32IM-NEXT: mulhu a1, a0, a1
27 ; RV32IM-NEXT: sub a2, a0, a1
28 ; RV32IM-NEXT: srli a2, a2, 1
29 ; RV32IM-NEXT: add a1, a2, a1
30 ; RV32IM-NEXT: srli a1, a1, 6
31 ; RV32IM-NEXT: addi a2, zero, 95
32 ; RV32IM-NEXT: mul a1, a1, a2
33 ; RV32IM-NEXT: sub a0, a0, a1
34 ; RV32IM-NEXT: ret
35 ;
36 ; RV64I-LABEL: fold_urem_positive_odd:
37 ; RV64I: # %bb.0:
38 ; RV64I-NEXT: addi sp, sp, -16
39 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
40 ; RV64I-NEXT: slli a0, a0, 32
41 ; RV64I-NEXT: srli a0, a0, 32
42 ; RV64I-NEXT: addi a1, zero, 95
43 ; RV64I-NEXT: call __umoddi3@plt
44 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
45 ; RV64I-NEXT: addi sp, sp, 16
46 ; RV64I-NEXT: ret
47 ;
48 ; RV64IM-LABEL: fold_urem_positive_odd:
49 ; RV64IM: # %bb.0:
50 ; RV64IM-NEXT: slli a1, a0, 32
51 ; RV64IM-NEXT: srli a1, a1, 32
52 ; RV64IM-NEXT: lui a2, 364242
53 ; RV64IM-NEXT: addiw a2, a2, 777
54 ; RV64IM-NEXT: mul a1, a1, a2
55 ; RV64IM-NEXT: srli a1, a1, 32
56 ; RV64IM-NEXT: subw a2, a0, a1
57 ; RV64IM-NEXT: srliw a2, a2, 1
58 ; RV64IM-NEXT: add a1, a2, a1
59 ; RV64IM-NEXT: srli a1, a1, 6
60 ; RV64IM-NEXT: addi a2, zero, 95
61 ; RV64IM-NEXT: mulw a1, a1, a2
62 ; RV64IM-NEXT: subw a0, a0, a1
63 ; RV64IM-NEXT: ret
64 %1 = urem i32 %x, 95
65 ret i32 %1
66 }
69 define i32 @fold_urem_positive_even(i32 %x) nounwind {
70 ; RV32I-LABEL: fold_urem_positive_even:
71 ; RV32I: # %bb.0:
72 ; RV32I-NEXT: addi sp, sp, -16
73 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
74 ; RV32I-NEXT: addi a1, zero, 1060
75 ; RV32I-NEXT: call __umodsi3@plt
76 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
77 ; RV32I-NEXT: addi sp, sp, 16
78 ; RV32I-NEXT: ret
79 ;
80 ; RV32IM-LABEL: fold_urem_positive_even:
81 ; RV32IM: # %bb.0:
82 ; RV32IM-NEXT: lui a1, 1012964
83 ; RV32IM-NEXT: addi a1, a1, -61
84 ; RV32IM-NEXT: mulhu a1, a0, a1
85 ; RV32IM-NEXT: srli a1, a1, 10
86 ; RV32IM-NEXT: addi a2, zero, 1060
87 ; RV32IM-NEXT: mul a1, a1, a2
88 ; RV32IM-NEXT: sub a0, a0, a1
89 ; RV32IM-NEXT: ret
90 ;
91 ; RV64I-LABEL: fold_urem_positive_even:
92 ; RV64I: # %bb.0:
93 ; RV64I-NEXT: addi sp, sp, -16
94 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
95 ; RV64I-NEXT: slli a0, a0, 32
96 ; RV64I-NEXT: srli a0, a0, 32
97 ; RV64I-NEXT: addi a1, zero, 1060
98 ; RV64I-NEXT: call __umoddi3@plt
99 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
100 ; RV64I-NEXT: addi sp, sp, 16
101 ; RV64I-NEXT: ret
102 ;
103 ; RV64IM-LABEL: fold_urem_positive_even:
104 ; RV64IM: # %bb.0:
105 ; RV64IM-NEXT: slli a1, a0, 32
106 ; RV64IM-NEXT: srli a1, a1, 32
107 ; RV64IM-NEXT: lui a2, 253241
108 ; RV64IM-NEXT: slli a2, a2, 2
109 ; RV64IM-NEXT: addi a2, a2, -61
110 ; RV64IM-NEXT: mul a1, a1, a2
111 ; RV64IM-NEXT: srli a1, a1, 42
112 ; RV64IM-NEXT: addi a2, zero, 1060
113 ; RV64IM-NEXT: mulw a1, a1, a2
114 ; RV64IM-NEXT: subw a0, a0, a1
115 ; RV64IM-NEXT: ret
116 %1 = urem i32 %x, 1060
117 ret i32 %1
118 }
121 ; Don't fold if we can combine urem with udiv.
122 define i32 @combine_urem_udiv(i32 %x) nounwind {
123 ; RV32I-LABEL: combine_urem_udiv:
124 ; RV32I: # %bb.0:
125 ; RV32I-NEXT: addi sp, sp, -16
126 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
127 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
128 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
129 ; RV32I-NEXT: mv s0, a0
130 ; RV32I-NEXT: addi a1, zero, 95
131 ; RV32I-NEXT: call __umodsi3@plt
132 ; RV32I-NEXT: mv s1, a0
133 ; RV32I-NEXT: addi a1, zero, 95
134 ; RV32I-NEXT: mv a0, s0
135 ; RV32I-NEXT: call __udivsi3@plt
136 ; RV32I-NEXT: add a0, s1, a0
137 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
138 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
139 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
140 ; RV32I-NEXT: addi sp, sp, 16
141 ; RV32I-NEXT: ret
142 ;
143 ; RV32IM-LABEL: combine_urem_udiv:
144 ; RV32IM: # %bb.0:
145 ; RV32IM-NEXT: lui a1, 364242
146 ; RV32IM-NEXT: addi a1, a1, 777
147 ; RV32IM-NEXT: mulhu a1, a0, a1
148 ; RV32IM-NEXT: sub a2, a0, a1
149 ; RV32IM-NEXT: srli a2, a2, 1
150 ; RV32IM-NEXT: add a1, a2, a1
151 ; RV32IM-NEXT: srli a1, a1, 6
152 ; RV32IM-NEXT: addi a2, zero, 95
153 ; RV32IM-NEXT: mul a2, a1, a2
154 ; RV32IM-NEXT: sub a0, a0, a2
155 ; RV32IM-NEXT: add a0, a0, a1
156 ; RV32IM-NEXT: ret
157 ;
158 ; RV64I-LABEL: combine_urem_udiv:
159 ; RV64I: # %bb.0:
160 ; RV64I-NEXT: addi sp, sp, -32
161 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
162 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
163 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
164 ; RV64I-NEXT: slli a0, a0, 32
165 ; RV64I-NEXT: srli s0, a0, 32
166 ; RV64I-NEXT: addi a1, zero, 95
167 ; RV64I-NEXT: mv a0, s0
168 ; RV64I-NEXT: call __umoddi3@plt
169 ; RV64I-NEXT: mv s1, a0
170 ; RV64I-NEXT: addi a1, zero, 95
171 ; RV64I-NEXT: mv a0, s0
172 ; RV64I-NEXT: call __udivdi3@plt
173 ; RV64I-NEXT: add a0, s1, a0
174 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
175 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
176 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
177 ; RV64I-NEXT: addi sp, sp, 32
178 ; RV64I-NEXT: ret
179 ;
180 ; RV64IM-LABEL: combine_urem_udiv:
181 ; RV64IM: # %bb.0:
182 ; RV64IM-NEXT: slli a1, a0, 32
183 ; RV64IM-NEXT: srli a1, a1, 32
184 ; RV64IM-NEXT: lui a2, 364242
185 ; RV64IM-NEXT: addiw a2, a2, 777
186 ; RV64IM-NEXT: mul a1, a1, a2
187 ; RV64IM-NEXT: srli a1, a1, 32
188 ; RV64IM-NEXT: subw a2, a0, a1
189 ; RV64IM-NEXT: srliw a2, a2, 1
190 ; RV64IM-NEXT: add a1, a2, a1
191 ; RV64IM-NEXT: srli a1, a1, 6
192 ; RV64IM-NEXT: addi a2, zero, 95
193 ; RV64IM-NEXT: mulw a2, a1, a2
194 ; RV64IM-NEXT: subw a0, a0, a2
195 ; RV64IM-NEXT: addw a0, a0, a1
196 ; RV64IM-NEXT: ret
197 %1 = urem i32 %x, 95
198 %2 = udiv i32 %x, 95
199 %3 = add i32 %1, %2
200 ret i32 %3
201 }
203 ; Don't fold for divisors that are a power of two.
204 define i32 @dont_fold_urem_power_of_two(i32 %x) nounwind {
205 ; CHECK-LABEL: dont_fold_urem_power_of_two:
206 ; CHECK: # %bb.0:
207 ; CHECK-NEXT: andi a0, a0, 63
208 ; CHECK-NEXT: ret
209 %1 = urem i32 %x, 64
210 ret i32 %1
211 }
213 ; Don't fold if the divisor is one.
214 define i32 @dont_fold_urem_one(i32 %x) nounwind {
215 ; CHECK-LABEL: dont_fold_urem_one:
216 ; CHECK: # %bb.0:
217 ; CHECK-NEXT: mv a0, zero
218 ; CHECK-NEXT: ret
219 %1 = urem i32 %x, 1
220 ret i32 %1
221 }
223 ; Don't fold if the divisor is 2^32.
224 define i32 @dont_fold_urem_i32_umax(i32 %x) nounwind {
225 ; CHECK-LABEL: dont_fold_urem_i32_umax:
226 ; CHECK: # %bb.0:
227 ; CHECK-NEXT: ret
228 %1 = urem i32 %x, 4294967296
229 ret i32 %1
230 }
232 ; Don't fold i64 urem
233 define i64 @dont_fold_urem_i64(i64 %x) nounwind {
234 ; RV32I-LABEL: dont_fold_urem_i64:
235 ; RV32I: # %bb.0:
236 ; RV32I-NEXT: addi sp, sp, -16
237 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
238 ; RV32I-NEXT: addi a2, zero, 98
239 ; RV32I-NEXT: mv a3, zero
240 ; RV32I-NEXT: call __umoddi3@plt
241 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
242 ; RV32I-NEXT: addi sp, sp, 16
243 ; RV32I-NEXT: ret
244 ;
245 ; RV32IM-LABEL: dont_fold_urem_i64:
246 ; RV32IM: # %bb.0:
247 ; RV32IM-NEXT: addi sp, sp, -16
248 ; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
249 ; RV32IM-NEXT: addi a2, zero, 98
250 ; RV32IM-NEXT: mv a3, zero
251 ; RV32IM-NEXT: call __umoddi3@plt
252 ; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
253 ; RV32IM-NEXT: addi sp, sp, 16
254 ; RV32IM-NEXT: ret
255 ;
256 ; RV64I-LABEL: dont_fold_urem_i64:
257 ; RV64I: # %bb.0:
258 ; RV64I-NEXT: addi sp, sp, -16
259 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
260 ; RV64I-NEXT: addi a1, zero, 98
261 ; RV64I-NEXT: call __umoddi3@plt
262 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
263 ; RV64I-NEXT: addi sp, sp, 16
264 ; RV64I-NEXT: ret
265 ;
266 ; RV64IM-LABEL: dont_fold_urem_i64:
267 ; RV64IM: # %bb.0:
268 ; RV64IM-NEXT: srli a1, a0, 1
269 ; RV64IM-NEXT: lui a2, 2675
270 ; RV64IM-NEXT: addiw a2, a2, -251
271 ; RV64IM-NEXT: slli a2, a2, 13
272 ; RV64IM-NEXT: addi a2, a2, 1839
273 ; RV64IM-NEXT: slli a2, a2, 13
274 ; RV64IM-NEXT: addi a2, a2, 167
275 ; RV64IM-NEXT: slli a2, a2, 13
276 ; RV64IM-NEXT: addi a2, a2, 1505
277 ; RV64IM-NEXT: mulhu a1, a1, a2
278 ; RV64IM-NEXT: srli a1, a1, 4
279 ; RV64IM-NEXT: addi a2, zero, 98
280 ; RV64IM-NEXT: mul a1, a1, a2
281 ; RV64IM-NEXT: sub a0, a0, a1
282 ; RV64IM-NEXT: ret
283 %1 = urem i64 %x, 98
284 ret i64 %1
285 }