| blob | 17b68b99fc0b12b83c535834d1420063d85fc888 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
6 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7 ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
12 define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
13 ; RV32I-LABEL: fold_urem_vec_1:
14 ; RV32I: # %bb.0:
15 ; RV32I-NEXT: addi sp, sp, -32
16 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
17 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
18 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
19 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
20 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
21 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
22 ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
23 ; RV32I-NEXT: lhu s2, 12(a1)
24 ; RV32I-NEXT: lhu s3, 8(a1)
25 ; RV32I-NEXT: lhu s0, 4(a1)
26 ; RV32I-NEXT: lhu a2, 0(a1)
27 ; RV32I-NEXT: mv s1, a0
28 ; RV32I-NEXT: addi a1, zero, 95
29 ; RV32I-NEXT: mv a0, a2
30 ; RV32I-NEXT: call __umodsi3@plt
31 ; RV32I-NEXT: mv s4, a0
32 ; RV32I-NEXT: addi a1, zero, 124
33 ; RV32I-NEXT: mv a0, s0
34 ; RV32I-NEXT: call __umodsi3@plt
35 ; RV32I-NEXT: mv s5, a0
36 ; RV32I-NEXT: addi a1, zero, 98
37 ; RV32I-NEXT: mv a0, s3
38 ; RV32I-NEXT: call __umodsi3@plt
39 ; RV32I-NEXT: mv s0, a0
40 ; RV32I-NEXT: addi a1, zero, 1003
41 ; RV32I-NEXT: mv a0, s2
42 ; RV32I-NEXT: call __umodsi3@plt
43 ; RV32I-NEXT: sh a0, 6(s1)
44 ; RV32I-NEXT: sh s0, 4(s1)
45 ; RV32I-NEXT: sh s5, 2(s1)
46 ; RV32I-NEXT: sh s4, 0(s1)
47 ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
48 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
49 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
50 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
51 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
52 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
53 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
54 ; RV32I-NEXT: addi sp, sp, 32
55 ; RV32I-NEXT: ret
56 ;
57 ; RV32IM-LABEL: fold_urem_vec_1:
58 ; RV32IM: # %bb.0:
59 ; RV32IM-NEXT: lhu a6, 12(a1)
60 ; RV32IM-NEXT: lhu a3, 8(a1)
61 ; RV32IM-NEXT: lhu a4, 0(a1)
62 ; RV32IM-NEXT: lhu a1, 4(a1)
63 ; RV32IM-NEXT: lui a5, 364242
64 ; RV32IM-NEXT: addi a5, a5, 777
65 ; RV32IM-NEXT: mulhu a5, a4, a5
66 ; RV32IM-NEXT: sub a2, a4, a5
67 ; RV32IM-NEXT: srli a2, a2, 1
68 ; RV32IM-NEXT: add a2, a2, a5
69 ; RV32IM-NEXT: srli a2, a2, 6
70 ; RV32IM-NEXT: addi a5, zero, 95
71 ; RV32IM-NEXT: mul a2, a2, a5
72 ; RV32IM-NEXT: sub a2, a4, a2
73 ; RV32IM-NEXT: srli a4, a1, 2
74 ; RV32IM-NEXT: lui a5, 135300
75 ; RV32IM-NEXT: addi a5, a5, 529
76 ; RV32IM-NEXT: mulhu a4, a4, a5
77 ; RV32IM-NEXT: srli a4, a4, 2
78 ; RV32IM-NEXT: addi a5, zero, 124
79 ; RV32IM-NEXT: mul a4, a4, a5
80 ; RV32IM-NEXT: sub a1, a1, a4
81 ; RV32IM-NEXT: lui a4, 342392
82 ; RV32IM-NEXT: addi a4, a4, 669
83 ; RV32IM-NEXT: mulhu a4, a3, a4
84 ; RV32IM-NEXT: srli a4, a4, 5
85 ; RV32IM-NEXT: addi a5, zero, 98
86 ; RV32IM-NEXT: mul a4, a4, a5
87 ; RV32IM-NEXT: sub a3, a3, a4
88 ; RV32IM-NEXT: lui a4, 267633
89 ; RV32IM-NEXT: addi a4, a4, -1809
90 ; RV32IM-NEXT: mulhu a4, a6, a4
91 ; RV32IM-NEXT: srli a4, a4, 8
92 ; RV32IM-NEXT: addi a5, zero, 1003
93 ; RV32IM-NEXT: mul a4, a4, a5
94 ; RV32IM-NEXT: sub a4, a6, a4
95 ; RV32IM-NEXT: sh a4, 6(a0)
96 ; RV32IM-NEXT: sh a3, 4(a0)
97 ; RV32IM-NEXT: sh a1, 2(a0)
98 ; RV32IM-NEXT: sh a2, 0(a0)
99 ; RV32IM-NEXT: ret
100 ;
101 ; RV64I-LABEL: fold_urem_vec_1:
102 ; RV64I: # %bb.0:
103 ; RV64I-NEXT: addi sp, sp, -64
104 ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
105 ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
106 ; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
107 ; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
108 ; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
109 ; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
110 ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
111 ; RV64I-NEXT: lhu s2, 24(a1)
112 ; RV64I-NEXT: lhu s3, 16(a1)
113 ; RV64I-NEXT: lhu s0, 8(a1)
114 ; RV64I-NEXT: lhu a2, 0(a1)
115 ; RV64I-NEXT: mv s1, a0
116 ; RV64I-NEXT: addi a1, zero, 95
117 ; RV64I-NEXT: mv a0, a2
118 ; RV64I-NEXT: call __umoddi3@plt
119 ; RV64I-NEXT: mv s4, a0
120 ; RV64I-NEXT: addi a1, zero, 124
121 ; RV64I-NEXT: mv a0, s0
122 ; RV64I-NEXT: call __umoddi3@plt
123 ; RV64I-NEXT: mv s5, a0
124 ; RV64I-NEXT: addi a1, zero, 98
125 ; RV64I-NEXT: mv a0, s3
126 ; RV64I-NEXT: call __umoddi3@plt
127 ; RV64I-NEXT: mv s0, a0
128 ; RV64I-NEXT: addi a1, zero, 1003
129 ; RV64I-NEXT: mv a0, s2
130 ; RV64I-NEXT: call __umoddi3@plt
131 ; RV64I-NEXT: sh a0, 6(s1)
132 ; RV64I-NEXT: sh s0, 4(s1)
133 ; RV64I-NEXT: sh s5, 2(s1)
134 ; RV64I-NEXT: sh s4, 0(s1)
135 ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
136 ; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
137 ; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
138 ; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
139 ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
140 ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
141 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
142 ; RV64I-NEXT: addi sp, sp, 64
143 ; RV64I-NEXT: ret
144 ;
145 ; RV64IM-LABEL: fold_urem_vec_1:
146 ; RV64IM: # %bb.0:
147 ; RV64IM-NEXT: lhu a6, 24(a1)
148 ; RV64IM-NEXT: lhu a3, 16(a1)
149 ; RV64IM-NEXT: lhu a4, 8(a1)
150 ; RV64IM-NEXT: lhu a1, 0(a1)
151 ; RV64IM-NEXT: lui a5, 1423
152 ; RV64IM-NEXT: addiw a5, a5, -733
153 ; RV64IM-NEXT: slli a5, a5, 15
154 ; RV64IM-NEXT: addi a5, a5, 1035
155 ; RV64IM-NEXT: slli a5, a5, 13
156 ; RV64IM-NEXT: addi a5, a5, -1811
157 ; RV64IM-NEXT: slli a5, a5, 12
158 ; RV64IM-NEXT: addi a5, a5, 561
159 ; RV64IM-NEXT: mulhu a5, a1, a5
160 ; RV64IM-NEXT: sub a2, a1, a5
161 ; RV64IM-NEXT: srli a2, a2, 1
162 ; RV64IM-NEXT: add a2, a2, a5
163 ; RV64IM-NEXT: srli a2, a2, 6
164 ; RV64IM-NEXT: addi a5, zero, 95
165 ; RV64IM-NEXT: mulw a2, a2, a5
166 ; RV64IM-NEXT: subw a1, a1, a2
167 ; RV64IM-NEXT: srli a2, a4, 2
168 ; RV64IM-NEXT: lui a5, 264
169 ; RV64IM-NEXT: addiw a5, a5, 1057
170 ; RV64IM-NEXT: slli a5, a5, 15
171 ; RV64IM-NEXT: addi a5, a5, 1057
172 ; RV64IM-NEXT: slli a5, a5, 15
173 ; RV64IM-NEXT: addi a5, a5, 1057
174 ; RV64IM-NEXT: slli a5, a5, 12
175 ; RV64IM-NEXT: addi a5, a5, 133
176 ; RV64IM-NEXT: mulhu a2, a2, a5
177 ; RV64IM-NEXT: srli a2, a2, 3
178 ; RV64IM-NEXT: addi a5, zero, 124
179 ; RV64IM-NEXT: mulw a2, a2, a5
180 ; RV64IM-NEXT: subw a2, a4, a2
181 ; RV64IM-NEXT: srli a4, a3, 1
182 ; RV64IM-NEXT: lui a5, 2675
183 ; RV64IM-NEXT: addiw a5, a5, -251
184 ; RV64IM-NEXT: slli a5, a5, 13
185 ; RV64IM-NEXT: addi a5, a5, 1839
186 ; RV64IM-NEXT: slli a5, a5, 13
187 ; RV64IM-NEXT: addi a5, a5, 167
188 ; RV64IM-NEXT: slli a5, a5, 13
189 ; RV64IM-NEXT: addi a5, a5, 1505
190 ; RV64IM-NEXT: mulhu a4, a4, a5
191 ; RV64IM-NEXT: srli a4, a4, 4
192 ; RV64IM-NEXT: addi a5, zero, 98
193 ; RV64IM-NEXT: mulw a4, a4, a5
194 ; RV64IM-NEXT: subw a3, a3, a4
195 ; RV64IM-NEXT: lui a4, 8364
196 ; RV64IM-NEXT: addiw a4, a4, -1977
197 ; RV64IM-NEXT: slli a4, a4, 12
198 ; RV64IM-NEXT: addi a4, a4, 1907
199 ; RV64IM-NEXT: slli a4, a4, 12
200 ; RV64IM-NEXT: addi a4, a4, 453
201 ; RV64IM-NEXT: slli a4, a4, 12
202 ; RV64IM-NEXT: addi a4, a4, 1213
203 ; RV64IM-NEXT: mulhu a4, a6, a4
204 ; RV64IM-NEXT: srli a4, a4, 7
205 ; RV64IM-NEXT: addi a5, zero, 1003
206 ; RV64IM-NEXT: mulw a4, a4, a5
207 ; RV64IM-NEXT: subw a4, a6, a4
208 ; RV64IM-NEXT: sh a4, 6(a0)
209 ; RV64IM-NEXT: sh a3, 4(a0)
210 ; RV64IM-NEXT: sh a2, 2(a0)
211 ; RV64IM-NEXT: sh a1, 0(a0)
212 ; RV64IM-NEXT: ret
213 %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
214 ret <4 x i16> %1
215 }
217 define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind {
218 ; RV32I-LABEL: fold_urem_vec_2:
219 ; RV32I: # %bb.0:
220 ; RV32I-NEXT: addi sp, sp, -32
221 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
222 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
223 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
224 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
225 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
226 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
227 ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
228 ; RV32I-NEXT: lhu s2, 12(a1)
229 ; RV32I-NEXT: lhu s3, 8(a1)
230 ; RV32I-NEXT: lhu s0, 4(a1)
231 ; RV32I-NEXT: lhu a2, 0(a1)
232 ; RV32I-NEXT: mv s1, a0
233 ; RV32I-NEXT: addi a1, zero, 95
234 ; RV32I-NEXT: mv a0, a2
235 ; RV32I-NEXT: call __umodsi3@plt
236 ; RV32I-NEXT: mv s4, a0
237 ; RV32I-NEXT: addi a1, zero, 95
238 ; RV32I-NEXT: mv a0, s0
239 ; RV32I-NEXT: call __umodsi3@plt
240 ; RV32I-NEXT: mv s5, a0
241 ; RV32I-NEXT: addi a1, zero, 95
242 ; RV32I-NEXT: mv a0, s3
243 ; RV32I-NEXT: call __umodsi3@plt
244 ; RV32I-NEXT: mv s0, a0
245 ; RV32I-NEXT: addi a1, zero, 95
246 ; RV32I-NEXT: mv a0, s2
247 ; RV32I-NEXT: call __umodsi3@plt
248 ; RV32I-NEXT: sh a0, 6(s1)
249 ; RV32I-NEXT: sh s0, 4(s1)
250 ; RV32I-NEXT: sh s5, 2(s1)
251 ; RV32I-NEXT: sh s4, 0(s1)
252 ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
253 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
254 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
255 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
256 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
257 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
258 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
259 ; RV32I-NEXT: addi sp, sp, 32
260 ; RV32I-NEXT: ret
261 ;
262 ; RV32IM-LABEL: fold_urem_vec_2:
263 ; RV32IM: # %bb.0:
264 ; RV32IM-NEXT: lhu a6, 12(a1)
265 ; RV32IM-NEXT: lhu a7, 8(a1)
266 ; RV32IM-NEXT: lhu a4, 0(a1)
267 ; RV32IM-NEXT: lhu a1, 4(a1)
268 ; RV32IM-NEXT: lui a5, 364242
269 ; RV32IM-NEXT: addi a5, a5, 777
270 ; RV32IM-NEXT: mulhu a2, a4, a5
271 ; RV32IM-NEXT: sub a3, a4, a2
272 ; RV32IM-NEXT: srli a3, a3, 1
273 ; RV32IM-NEXT: add a2, a3, a2
274 ; RV32IM-NEXT: srli a2, a2, 6
275 ; RV32IM-NEXT: addi a3, zero, 95
276 ; RV32IM-NEXT: mul a2, a2, a3
277 ; RV32IM-NEXT: sub t0, a4, a2
278 ; RV32IM-NEXT: mulhu a4, a1, a5
279 ; RV32IM-NEXT: sub a2, a1, a4
280 ; RV32IM-NEXT: srli a2, a2, 1
281 ; RV32IM-NEXT: add a2, a2, a4
282 ; RV32IM-NEXT: srli a2, a2, 6
283 ; RV32IM-NEXT: mul a2, a2, a3
284 ; RV32IM-NEXT: sub a1, a1, a2
285 ; RV32IM-NEXT: mulhu a2, a7, a5
286 ; RV32IM-NEXT: sub a4, a7, a2
287 ; RV32IM-NEXT: srli a4, a4, 1
288 ; RV32IM-NEXT: add a2, a4, a2
289 ; RV32IM-NEXT: srli a2, a2, 6
290 ; RV32IM-NEXT: mul a2, a2, a3
291 ; RV32IM-NEXT: sub a2, a7, a2
292 ; RV32IM-NEXT: mulhu a4, a6, a5
293 ; RV32IM-NEXT: sub a5, a6, a4
294 ; RV32IM-NEXT: srli a5, a5, 1
295 ; RV32IM-NEXT: add a4, a5, a4
296 ; RV32IM-NEXT: srli a4, a4, 6
297 ; RV32IM-NEXT: mul a3, a4, a3
298 ; RV32IM-NEXT: sub a3, a6, a3
299 ; RV32IM-NEXT: sh a3, 6(a0)
300 ; RV32IM-NEXT: sh a2, 4(a0)
301 ; RV32IM-NEXT: sh a1, 2(a0)
302 ; RV32IM-NEXT: sh t0, 0(a0)
303 ; RV32IM-NEXT: ret
304 ;
305 ; RV64I-LABEL: fold_urem_vec_2:
306 ; RV64I: # %bb.0:
307 ; RV64I-NEXT: addi sp, sp, -64
308 ; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
309 ; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
310 ; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
311 ; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
312 ; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
313 ; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
314 ; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
315 ; RV64I-NEXT: lhu s2, 24(a1)
316 ; RV64I-NEXT: lhu s3, 16(a1)
317 ; RV64I-NEXT: lhu s0, 8(a1)
318 ; RV64I-NEXT: lhu a2, 0(a1)
319 ; RV64I-NEXT: mv s1, a0
320 ; RV64I-NEXT: addi a1, zero, 95
321 ; RV64I-NEXT: mv a0, a2
322 ; RV64I-NEXT: call __umoddi3@plt
323 ; RV64I-NEXT: mv s4, a0
324 ; RV64I-NEXT: addi a1, zero, 95
325 ; RV64I-NEXT: mv a0, s0
326 ; RV64I-NEXT: call __umoddi3@plt
327 ; RV64I-NEXT: mv s5, a0
328 ; RV64I-NEXT: addi a1, zero, 95
329 ; RV64I-NEXT: mv a0, s3
330 ; RV64I-NEXT: call __umoddi3@plt
331 ; RV64I-NEXT: mv s0, a0
332 ; RV64I-NEXT: addi a1, zero, 95
333 ; RV64I-NEXT: mv a0, s2
334 ; RV64I-NEXT: call __umoddi3@plt
335 ; RV64I-NEXT: sh a0, 6(s1)
336 ; RV64I-NEXT: sh s0, 4(s1)
337 ; RV64I-NEXT: sh s5, 2(s1)
338 ; RV64I-NEXT: sh s4, 0(s1)
339 ; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
340 ; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
341 ; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
342 ; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
343 ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
344 ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
345 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
346 ; RV64I-NEXT: addi sp, sp, 64
347 ; RV64I-NEXT: ret
348 ;
349 ; RV64IM-LABEL: fold_urem_vec_2:
350 ; RV64IM: # %bb.0:
351 ; RV64IM-NEXT: lhu a6, 24(a1)
352 ; RV64IM-NEXT: lhu a7, 16(a1)
353 ; RV64IM-NEXT: lhu a4, 8(a1)
354 ; RV64IM-NEXT: lhu a1, 0(a1)
355 ; RV64IM-NEXT: lui a5, 1423
356 ; RV64IM-NEXT: addiw a5, a5, -733
357 ; RV64IM-NEXT: slli a5, a5, 15
358 ; RV64IM-NEXT: addi a5, a5, 1035
359 ; RV64IM-NEXT: slli a5, a5, 13
360 ; RV64IM-NEXT: addi a5, a5, -1811
361 ; RV64IM-NEXT: slli a5, a5, 12
362 ; RV64IM-NEXT: addi a5, a5, 561
363 ; RV64IM-NEXT: mulhu a2, a1, a5
364 ; RV64IM-NEXT: sub a3, a1, a2
365 ; RV64IM-NEXT: srli a3, a3, 1
366 ; RV64IM-NEXT: add a2, a3, a2
367 ; RV64IM-NEXT: srli a2, a2, 6
368 ; RV64IM-NEXT: addi a3, zero, 95
369 ; RV64IM-NEXT: mulw a2, a2, a3
370 ; RV64IM-NEXT: subw t0, a1, a2
371 ; RV64IM-NEXT: mulhu a2, a4, a5
372 ; RV64IM-NEXT: sub a1, a4, a2
373 ; RV64IM-NEXT: srli a1, a1, 1
374 ; RV64IM-NEXT: add a1, a1, a2
375 ; RV64IM-NEXT: srli a1, a1, 6
376 ; RV64IM-NEXT: mulw a1, a1, a3
377 ; RV64IM-NEXT: subw a1, a4, a1
378 ; RV64IM-NEXT: mulhu a2, a7, a5
379 ; RV64IM-NEXT: sub a4, a7, a2
380 ; RV64IM-NEXT: srli a4, a4, 1
381 ; RV64IM-NEXT: add a2, a4, a2
382 ; RV64IM-NEXT: srli a2, a2, 6
383 ; RV64IM-NEXT: mulw a2, a2, a3
384 ; RV64IM-NEXT: subw a2, a7, a2
385 ; RV64IM-NEXT: mulhu a4, a6, a5
386 ; RV64IM-NEXT: sub a5, a6, a4
387 ; RV64IM-NEXT: srli a5, a5, 1
388 ; RV64IM-NEXT: add a4, a5, a4
389 ; RV64IM-NEXT: srli a4, a4, 6
390 ; RV64IM-NEXT: mulw a3, a4, a3
391 ; RV64IM-NEXT: subw a3, a6, a3
392 ; RV64IM-NEXT: sh a3, 6(a0)
393 ; RV64IM-NEXT: sh a2, 4(a0)
394 ; RV64IM-NEXT: sh a1, 2(a0)
395 ; RV64IM-NEXT: sh t0, 0(a0)
396 ; RV64IM-NEXT: ret
397 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
398 ret <4 x i16> %1
399 }
402 ; Don't fold if we can combine urem with udiv.
403 define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind {
404 ; RV32I-LABEL: combine_urem_udiv:
405 ; RV32I: # %bb.0:
406 ; RV32I-NEXT: addi sp, sp, -48
407 ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
408 ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
409 ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
410 ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
411 ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
412 ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
413 ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
414 ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
415 ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
416 ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
417 ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
418 ; RV32I-NEXT: lhu s2, 0(a1)
419 ; RV32I-NEXT: lhu s3, 4(a1)
420 ; RV32I-NEXT: lhu s4, 8(a1)
421 ; RV32I-NEXT: lhu s1, 12(a1)
422 ; RV32I-NEXT: mv s0, a0
423 ; RV32I-NEXT: addi a1, zero, 95
424 ; RV32I-NEXT: mv a0, s1
425 ; RV32I-NEXT: call __umodsi3@plt
426 ; RV32I-NEXT: mv s5, a0
427 ; RV32I-NEXT: addi a1, zero, 95
428 ; RV32I-NEXT: mv a0, s4
429 ; RV32I-NEXT: call __umodsi3@plt
430 ; RV32I-NEXT: mv s6, a0
431 ; RV32I-NEXT: addi a1, zero, 95
432 ; RV32I-NEXT: mv a0, s3
433 ; RV32I-NEXT: call __umodsi3@plt
434 ; RV32I-NEXT: mv s7, a0
435 ; RV32I-NEXT: addi a1, zero, 95
436 ; RV32I-NEXT: mv a0, s2
437 ; RV32I-NEXT: call __umodsi3@plt
438 ; RV32I-NEXT: mv s8, a0
439 ; RV32I-NEXT: addi a1, zero, 95
440 ; RV32I-NEXT: mv a0, s1
441 ; RV32I-NEXT: call __udivsi3@plt
442 ; RV32I-NEXT: mv s9, a0
443 ; RV32I-NEXT: addi a1, zero, 95
444 ; RV32I-NEXT: mv a0, s4
445 ; RV32I-NEXT: call __udivsi3@plt
446 ; RV32I-NEXT: mv s4, a0
447 ; RV32I-NEXT: addi a1, zero, 95
448 ; RV32I-NEXT: mv a0, s3
449 ; RV32I-NEXT: call __udivsi3@plt
450 ; RV32I-NEXT: mv s1, a0
451 ; RV32I-NEXT: addi a1, zero, 95
452 ; RV32I-NEXT: mv a0, s2
453 ; RV32I-NEXT: call __udivsi3@plt
454 ; RV32I-NEXT: add a0, s8, a0
455 ; RV32I-NEXT: add a1, s7, s1
456 ; RV32I-NEXT: add a2, s6, s4
457 ; RV32I-NEXT: add a3, s5, s9
458 ; RV32I-NEXT: sh a3, 6(s0)
459 ; RV32I-NEXT: sh a2, 4(s0)
460 ; RV32I-NEXT: sh a1, 2(s0)
461 ; RV32I-NEXT: sh a0, 0(s0)
462 ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
463 ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
464 ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
465 ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
466 ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
467 ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
468 ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
469 ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
470 ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
471 ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
472 ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
473 ; RV32I-NEXT: addi sp, sp, 48
474 ; RV32I-NEXT: ret
475 ;
476 ; RV32IM-LABEL: combine_urem_udiv:
477 ; RV32IM: # %bb.0:
478 ; RV32IM-NEXT: lhu a6, 0(a1)
479 ; RV32IM-NEXT: lhu a7, 4(a1)
480 ; RV32IM-NEXT: lhu a4, 12(a1)
481 ; RV32IM-NEXT: lhu a1, 8(a1)
482 ; RV32IM-NEXT: lui a5, 364242
483 ; RV32IM-NEXT: addi a5, a5, 777
484 ; RV32IM-NEXT: mulhu a2, a4, a5
485 ; RV32IM-NEXT: sub a3, a4, a2
486 ; RV32IM-NEXT: srli a3, a3, 1
487 ; RV32IM-NEXT: add a2, a3, a2
488 ; RV32IM-NEXT: srli t3, a2, 6
489 ; RV32IM-NEXT: addi t0, zero, 95
490 ; RV32IM-NEXT: mul a3, t3, t0
491 ; RV32IM-NEXT: sub t1, a4, a3
492 ; RV32IM-NEXT: mulhu a4, a1, a5
493 ; RV32IM-NEXT: sub a3, a1, a4
494 ; RV32IM-NEXT: srli a3, a3, 1
495 ; RV32IM-NEXT: add a3, a3, a4
496 ; RV32IM-NEXT: srli a3, a3, 6
497 ; RV32IM-NEXT: mul a4, a3, t0
498 ; RV32IM-NEXT: sub t2, a1, a4
499 ; RV32IM-NEXT: mulhu a4, a7, a5
500 ; RV32IM-NEXT: sub a1, a7, a4
501 ; RV32IM-NEXT: srli a1, a1, 1
502 ; RV32IM-NEXT: add a1, a1, a4
503 ; RV32IM-NEXT: srli a1, a1, 6
504 ; RV32IM-NEXT: mul a4, a1, t0
505 ; RV32IM-NEXT: sub a4, a7, a4
506 ; RV32IM-NEXT: mulhu a5, a6, a5
507 ; RV32IM-NEXT: sub a2, a6, a5
508 ; RV32IM-NEXT: srli a2, a2, 1
509 ; RV32IM-NEXT: add a2, a2, a5
510 ; RV32IM-NEXT: srli a2, a2, 6
511 ; RV32IM-NEXT: mul a5, a2, t0
512 ; RV32IM-NEXT: sub a5, a6, a5
513 ; RV32IM-NEXT: add a2, a5, a2
514 ; RV32IM-NEXT: add a1, a4, a1
515 ; RV32IM-NEXT: add a3, t2, a3
516 ; RV32IM-NEXT: add a4, t1, t3
517 ; RV32IM-NEXT: sh a4, 6(a0)
518 ; RV32IM-NEXT: sh a3, 4(a0)
519 ; RV32IM-NEXT: sh a1, 2(a0)
520 ; RV32IM-NEXT: sh a2, 0(a0)
521 ; RV32IM-NEXT: ret
522 ;
523 ; RV64I-LABEL: combine_urem_udiv:
524 ; RV64I: # %bb.0:
525 ; RV64I-NEXT: addi sp, sp, -96
526 ; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
527 ; RV64I-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
528 ; RV64I-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
529 ; RV64I-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
530 ; RV64I-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
531 ; RV64I-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
532 ; RV64I-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
533 ; RV64I-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
534 ; RV64I-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
535 ; RV64I-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
536 ; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
537 ; RV64I-NEXT: lhu s2, 0(a1)
538 ; RV64I-NEXT: lhu s3, 8(a1)
539 ; RV64I-NEXT: lhu s4, 16(a1)
540 ; RV64I-NEXT: lhu s1, 24(a1)
541 ; RV64I-NEXT: mv s0, a0
542 ; RV64I-NEXT: addi a1, zero, 95
543 ; RV64I-NEXT: mv a0, s1
544 ; RV64I-NEXT: call __umoddi3@plt
545 ; RV64I-NEXT: mv s5, a0
546 ; RV64I-NEXT: addi a1, zero, 95
547 ; RV64I-NEXT: mv a0, s4
548 ; RV64I-NEXT: call __umoddi3@plt
549 ; RV64I-NEXT: mv s6, a0
550 ; RV64I-NEXT: addi a1, zero, 95
551 ; RV64I-NEXT: mv a0, s3
552 ; RV64I-NEXT: call __umoddi3@plt
553 ; RV64I-NEXT: mv s7, a0
554 ; RV64I-NEXT: addi a1, zero, 95
555 ; RV64I-NEXT: mv a0, s2
556 ; RV64I-NEXT: call __umoddi3@plt
557 ; RV64I-NEXT: mv s8, a0
558 ; RV64I-NEXT: addi a1, zero, 95
559 ; RV64I-NEXT: mv a0, s1
560 ; RV64I-NEXT: call __udivdi3@plt
561 ; RV64I-NEXT: mv s9, a0
562 ; RV64I-NEXT: addi a1, zero, 95
563 ; RV64I-NEXT: mv a0, s4
564 ; RV64I-NEXT: call __udivdi3@plt
565 ; RV64I-NEXT: mv s4, a0
566 ; RV64I-NEXT: addi a1, zero, 95
567 ; RV64I-NEXT: mv a0, s3
568 ; RV64I-NEXT: call __udivdi3@plt
569 ; RV64I-NEXT: mv s1, a0
570 ; RV64I-NEXT: addi a1, zero, 95
571 ; RV64I-NEXT: mv a0, s2
572 ; RV64I-NEXT: call __udivdi3@plt
573 ; RV64I-NEXT: addw a0, s8, a0
574 ; RV64I-NEXT: addw a1, s7, s1
575 ; RV64I-NEXT: addw a2, s6, s4
576 ; RV64I-NEXT: addw a3, s5, s9
577 ; RV64I-NEXT: sh a3, 6(s0)
578 ; RV64I-NEXT: sh a2, 4(s0)
579 ; RV64I-NEXT: sh a1, 2(s0)
580 ; RV64I-NEXT: sh a0, 0(s0)
581 ; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
582 ; RV64I-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
583 ; RV64I-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
584 ; RV64I-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
585 ; RV64I-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
586 ; RV64I-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
587 ; RV64I-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
588 ; RV64I-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
589 ; RV64I-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
590 ; RV64I-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
591 ; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
592 ; RV64I-NEXT: addi sp, sp, 96
593 ; RV64I-NEXT: ret
594 ;
595 ; RV64IM-LABEL: combine_urem_udiv:
596 ; RV64IM: # %bb.0:
597 ; RV64IM-NEXT: lhu a6, 0(a1)
598 ; RV64IM-NEXT: lhu a7, 8(a1)
599 ; RV64IM-NEXT: lhu a4, 16(a1)
600 ; RV64IM-NEXT: lhu a1, 24(a1)
601 ; RV64IM-NEXT: lui a5, 1423
602 ; RV64IM-NEXT: addiw a5, a5, -733
603 ; RV64IM-NEXT: slli a5, a5, 15
604 ; RV64IM-NEXT: addi a5, a5, 1035
605 ; RV64IM-NEXT: slli a5, a5, 13
606 ; RV64IM-NEXT: addi a5, a5, -1811
607 ; RV64IM-NEXT: slli a5, a5, 12
608 ; RV64IM-NEXT: addi a5, a5, 561
609 ; RV64IM-NEXT: mulhu a2, a1, a5
610 ; RV64IM-NEXT: sub a3, a1, a2
611 ; RV64IM-NEXT: srli a3, a3, 1
612 ; RV64IM-NEXT: add a2, a3, a2
613 ; RV64IM-NEXT: srli t3, a2, 6
614 ; RV64IM-NEXT: addi t0, zero, 95
615 ; RV64IM-NEXT: mulw a3, t3, t0
616 ; RV64IM-NEXT: subw t1, a1, a3
617 ; RV64IM-NEXT: mulhu a3, a4, a5
618 ; RV64IM-NEXT: sub a1, a4, a3
619 ; RV64IM-NEXT: srli a1, a1, 1
620 ; RV64IM-NEXT: add a1, a1, a3
621 ; RV64IM-NEXT: srli a1, a1, 6
622 ; RV64IM-NEXT: mulw a3, a1, t0
623 ; RV64IM-NEXT: subw t2, a4, a3
624 ; RV64IM-NEXT: mulhu a4, a7, a5
625 ; RV64IM-NEXT: sub a3, a7, a4
626 ; RV64IM-NEXT: srli a3, a3, 1
627 ; RV64IM-NEXT: add a3, a3, a4
628 ; RV64IM-NEXT: srli a3, a3, 6
629 ; RV64IM-NEXT: mulw a4, a3, t0
630 ; RV64IM-NEXT: subw a4, a7, a4
631 ; RV64IM-NEXT: mulhu a5, a6, a5
632 ; RV64IM-NEXT: sub a2, a6, a5
633 ; RV64IM-NEXT: srli a2, a2, 1
634 ; RV64IM-NEXT: add a2, a2, a5
635 ; RV64IM-NEXT: srli a2, a2, 6
636 ; RV64IM-NEXT: mulw a5, a2, t0
637 ; RV64IM-NEXT: subw a5, a6, a5
638 ; RV64IM-NEXT: addw a2, a5, a2
639 ; RV64IM-NEXT: addw a3, a4, a3
640 ; RV64IM-NEXT: addw a1, t2, a1
641 ; RV64IM-NEXT: addw a4, t1, t3
642 ; RV64IM-NEXT: sh a4, 6(a0)
643 ; RV64IM-NEXT: sh a1, 4(a0)
644 ; RV64IM-NEXT: sh a3, 2(a0)
645 ; RV64IM-NEXT: sh a2, 0(a0)
646 ; RV64IM-NEXT: ret
647 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
648 %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
649 %3 = add <4 x i16> %1, %2
650 ret <4 x i16> %3
651 }
653 ; Don't fold for divisors that are a power of two.
654 define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind {
655 ; RV32I-LABEL: dont_fold_urem_power_of_two:
656 ; RV32I: # %bb.0:
657 ; RV32I-NEXT: addi sp, sp, -32
658 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
659 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
660 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
661 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
662 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
663 ; RV32I-NEXT: lhu s2, 8(a1)
664 ; RV32I-NEXT: lhu s3, 4(a1)
665 ; RV32I-NEXT: lhu s1, 0(a1)
666 ; RV32I-NEXT: lhu a2, 12(a1)
667 ; RV32I-NEXT: mv s0, a0
668 ; RV32I-NEXT: addi a1, zero, 95
669 ; RV32I-NEXT: mv a0, a2
670 ; RV32I-NEXT: call __umodsi3@plt
671 ; RV32I-NEXT: andi a1, s1, 63
672 ; RV32I-NEXT: andi a2, s3, 31
673 ; RV32I-NEXT: andi a3, s2, 7
674 ; RV32I-NEXT: sh a0, 6(s0)
675 ; RV32I-NEXT: sh a3, 4(s0)
676 ; RV32I-NEXT: sh a2, 2(s0)
677 ; RV32I-NEXT: sh a1, 0(s0)
678 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
679 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
680 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
681 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
682 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
683 ; RV32I-NEXT: addi sp, sp, 32
684 ; RV32I-NEXT: ret
685 ;
686 ; RV32IM-LABEL: dont_fold_urem_power_of_two:
687 ; RV32IM: # %bb.0:
688 ; RV32IM-NEXT: lhu a6, 8(a1)
689 ; RV32IM-NEXT: lhu a3, 4(a1)
690 ; RV32IM-NEXT: lhu a4, 12(a1)
691 ; RV32IM-NEXT: lhu a1, 0(a1)
692 ; RV32IM-NEXT: lui a5, 364242
693 ; RV32IM-NEXT: addi a5, a5, 777
694 ; RV32IM-NEXT: mulhu a5, a4, a5
695 ; RV32IM-NEXT: sub a2, a4, a5
696 ; RV32IM-NEXT: srli a2, a2, 1
697 ; RV32IM-NEXT: add a2, a2, a5
698 ; RV32IM-NEXT: srli a2, a2, 6
699 ; RV32IM-NEXT: addi a5, zero, 95
700 ; RV32IM-NEXT: mul a2, a2, a5
701 ; RV32IM-NEXT: sub a2, a4, a2
702 ; RV32IM-NEXT: andi a1, a1, 63
703 ; RV32IM-NEXT: andi a3, a3, 31
704 ; RV32IM-NEXT: andi a4, a6, 7
705 ; RV32IM-NEXT: sh a4, 4(a0)
706 ; RV32IM-NEXT: sh a3, 2(a0)
707 ; RV32IM-NEXT: sh a1, 0(a0)
708 ; RV32IM-NEXT: sh a2, 6(a0)
709 ; RV32IM-NEXT: ret
710 ;
711 ; RV64I-LABEL: dont_fold_urem_power_of_two:
712 ; RV64I: # %bb.0:
713 ; RV64I-NEXT: addi sp, sp, -48
714 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
715 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
716 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
717 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
718 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
719 ; RV64I-NEXT: lhu s2, 16(a1)
720 ; RV64I-NEXT: lhu s3, 8(a1)
721 ; RV64I-NEXT: lhu s1, 0(a1)
722 ; RV64I-NEXT: lhu a2, 24(a1)
723 ; RV64I-NEXT: mv s0, a0
724 ; RV64I-NEXT: addi a1, zero, 95
725 ; RV64I-NEXT: mv a0, a2
726 ; RV64I-NEXT: call __umoddi3@plt
727 ; RV64I-NEXT: andi a1, s1, 63
728 ; RV64I-NEXT: andi a2, s3, 31
729 ; RV64I-NEXT: andi a3, s2, 7
730 ; RV64I-NEXT: sh a0, 6(s0)
731 ; RV64I-NEXT: sh a3, 4(s0)
732 ; RV64I-NEXT: sh a2, 2(s0)
733 ; RV64I-NEXT: sh a1, 0(s0)
734 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
735 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
736 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
737 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
738 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
739 ; RV64I-NEXT: addi sp, sp, 48
740 ; RV64I-NEXT: ret
741 ;
742 ; RV64IM-LABEL: dont_fold_urem_power_of_two:
743 ; RV64IM: # %bb.0:
744 ; RV64IM-NEXT: lhu a6, 16(a1)
745 ; RV64IM-NEXT: lhu a3, 8(a1)
746 ; RV64IM-NEXT: lhu a4, 0(a1)
747 ; RV64IM-NEXT: lhu a1, 24(a1)
748 ; RV64IM-NEXT: lui a5, 1423
749 ; RV64IM-NEXT: addiw a5, a5, -733
750 ; RV64IM-NEXT: slli a5, a5, 15
751 ; RV64IM-NEXT: addi a5, a5, 1035
752 ; RV64IM-NEXT: slli a5, a5, 13
753 ; RV64IM-NEXT: addi a5, a5, -1811
754 ; RV64IM-NEXT: slli a5, a5, 12
755 ; RV64IM-NEXT: addi a5, a5, 561
756 ; RV64IM-NEXT: mulhu a5, a1, a5
757 ; RV64IM-NEXT: sub a2, a1, a5
758 ; RV64IM-NEXT: srli a2, a2, 1
759 ; RV64IM-NEXT: add a2, a2, a5
760 ; RV64IM-NEXT: srli a2, a2, 6
761 ; RV64IM-NEXT: addi a5, zero, 95
762 ; RV64IM-NEXT: mulw a2, a2, a5
763 ; RV64IM-NEXT: subw a1, a1, a2
764 ; RV64IM-NEXT: andi a2, a4, 63
765 ; RV64IM-NEXT: andi a3, a3, 31
766 ; RV64IM-NEXT: andi a4, a6, 7
767 ; RV64IM-NEXT: sh a4, 4(a0)
768 ; RV64IM-NEXT: sh a3, 2(a0)
769 ; RV64IM-NEXT: sh a2, 0(a0)
770 ; RV64IM-NEXT: sh a1, 6(a0)
771 ; RV64IM-NEXT: ret
772 %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
773 ret <4 x i16> %1
774 }
776 ; Don't fold if the divisor is one.
777 define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
778 ; RV32I-LABEL: dont_fold_urem_one:
779 ; RV32I: # %bb.0:
780 ; RV32I-NEXT: addi sp, sp, -32
781 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
782 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
783 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
784 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
785 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
786 ; RV32I-NEXT: lhu s2, 12(a1)
787 ; RV32I-NEXT: lhu s1, 8(a1)
788 ; RV32I-NEXT: lhu a2, 4(a1)
789 ; RV32I-NEXT: mv s0, a0
790 ; RV32I-NEXT: addi a1, zero, 654
791 ; RV32I-NEXT: mv a0, a2
792 ; RV32I-NEXT: call __umodsi3@plt
793 ; RV32I-NEXT: mv s3, a0
794 ; RV32I-NEXT: addi a1, zero, 23
795 ; RV32I-NEXT: mv a0, s1
796 ; RV32I-NEXT: call __umodsi3@plt
797 ; RV32I-NEXT: mv s1, a0
798 ; RV32I-NEXT: lui a0, 1
799 ; RV32I-NEXT: addi a1, a0, 1327
800 ; RV32I-NEXT: mv a0, s2
801 ; RV32I-NEXT: call __umodsi3@plt
802 ; RV32I-NEXT: sh zero, 0(s0)
803 ; RV32I-NEXT: sh a0, 6(s0)
804 ; RV32I-NEXT: sh s1, 4(s0)
805 ; RV32I-NEXT: sh s3, 2(s0)
806 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
807 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
808 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
809 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
810 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
811 ; RV32I-NEXT: addi sp, sp, 32
812 ; RV32I-NEXT: ret
813 ;
814 ; RV32IM-LABEL: dont_fold_urem_one:
815 ; RV32IM: # %bb.0:
816 ; RV32IM-NEXT: lhu a2, 4(a1)
817 ; RV32IM-NEXT: lhu a3, 12(a1)
818 ; RV32IM-NEXT: lhu a1, 8(a1)
819 ; RV32IM-NEXT: srli a4, a2, 1
820 ; RV32IM-NEXT: lui a5, 820904
821 ; RV32IM-NEXT: addi a5, a5, -1903
822 ; RV32IM-NEXT: mulhu a4, a4, a5
823 ; RV32IM-NEXT: srli a4, a4, 8
824 ; RV32IM-NEXT: addi a5, zero, 654
825 ; RV32IM-NEXT: mul a4, a4, a5
826 ; RV32IM-NEXT: sub a2, a2, a4
827 ; RV32IM-NEXT: lui a4, 729444
828 ; RV32IM-NEXT: addi a4, a4, 713
829 ; RV32IM-NEXT: mulhu a4, a1, a4
830 ; RV32IM-NEXT: srli a4, a4, 4
831 ; RV32IM-NEXT: addi a5, zero, 23
832 ; RV32IM-NEXT: mul a4, a4, a5
833 ; RV32IM-NEXT: sub a1, a1, a4
834 ; RV32IM-NEXT: lui a4, 395996
835 ; RV32IM-NEXT: addi a4, a4, -2009
836 ; RV32IM-NEXT: mulhu a4, a3, a4
837 ; RV32IM-NEXT: srli a4, a4, 11
838 ; RV32IM-NEXT: lui a5, 1
839 ; RV32IM-NEXT: addi a5, a5, 1327
840 ; RV32IM-NEXT: mul a4, a4, a5
841 ; RV32IM-NEXT: sub a3, a3, a4
842 ; RV32IM-NEXT: sh zero, 0(a0)
843 ; RV32IM-NEXT: sh a3, 6(a0)
844 ; RV32IM-NEXT: sh a1, 4(a0)
845 ; RV32IM-NEXT: sh a2, 2(a0)
846 ; RV32IM-NEXT: ret
847 ;
848 ; RV64I-LABEL: dont_fold_urem_one:
849 ; RV64I: # %bb.0:
850 ; RV64I-NEXT: addi sp, sp, -48
851 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
852 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
853 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
854 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
855 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
856 ; RV64I-NEXT: lhu s2, 24(a1)
857 ; RV64I-NEXT: lhu s1, 16(a1)
858 ; RV64I-NEXT: lhu a2, 8(a1)
859 ; RV64I-NEXT: mv s0, a0
860 ; RV64I-NEXT: addi a1, zero, 654
861 ; RV64I-NEXT: mv a0, a2
862 ; RV64I-NEXT: call __umoddi3@plt
863 ; RV64I-NEXT: mv s3, a0
864 ; RV64I-NEXT: addi a1, zero, 23
865 ; RV64I-NEXT: mv a0, s1
866 ; RV64I-NEXT: call __umoddi3@plt
867 ; RV64I-NEXT: mv s1, a0
868 ; RV64I-NEXT: lui a0, 1
869 ; RV64I-NEXT: addiw a1, a0, 1327
870 ; RV64I-NEXT: mv a0, s2
871 ; RV64I-NEXT: call __umoddi3@plt
872 ; RV64I-NEXT: sh zero, 0(s0)
873 ; RV64I-NEXT: sh a0, 6(s0)
874 ; RV64I-NEXT: sh s1, 4(s0)
875 ; RV64I-NEXT: sh s3, 2(s0)
876 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
877 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
878 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
879 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
880 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
881 ; RV64I-NEXT: addi sp, sp, 48
882 ; RV64I-NEXT: ret
883 ;
884 ; RV64IM-LABEL: dont_fold_urem_one:
885 ; RV64IM: # %bb.0:
886 ; RV64IM-NEXT: lhu a2, 24(a1)
887 ; RV64IM-NEXT: lhu a3, 8(a1)
888 ; RV64IM-NEXT: lhu a1, 16(a1)
889 ; RV64IM-NEXT: lui a4, 3206
890 ; RV64IM-NEXT: addiw a4, a4, -1781
891 ; RV64IM-NEXT: slli a4, a4, 13
892 ; RV64IM-NEXT: addi a4, a4, 1069
893 ; RV64IM-NEXT: slli a4, a4, 12
894 ; RV64IM-NEXT: addi a4, a4, -1959
895 ; RV64IM-NEXT: slli a4, a4, 14
896 ; RV64IM-NEXT: addi a4, a4, 713
897 ; RV64IM-NEXT: mulhu a4, a1, a4
898 ; RV64IM-NEXT: sub a5, a1, a4
899 ; RV64IM-NEXT: srli a5, a5, 1
900 ; RV64IM-NEXT: add a4, a5, a4
901 ; RV64IM-NEXT: srli a4, a4, 4
902 ; RV64IM-NEXT: addi a5, zero, 23
903 ; RV64IM-NEXT: mulw a4, a4, a5
904 ; RV64IM-NEXT: subw a1, a1, a4
905 ; RV64IM-NEXT: srli a4, a3, 1
906 ; RV64IM-NEXT: lui a5, 6413
907 ; RV64IM-NEXT: addiw a5, a5, 1265
908 ; RV64IM-NEXT: slli a5, a5, 13
909 ; RV64IM-NEXT: addi a5, a5, 1027
910 ; RV64IM-NEXT: slli a5, a5, 13
911 ; RV64IM-NEXT: addi a5, a5, 1077
912 ; RV64IM-NEXT: slli a5, a5, 12
913 ; RV64IM-NEXT: addi a5, a5, 965
914 ; RV64IM-NEXT: mulhu a4, a4, a5
915 ; RV64IM-NEXT: srli a4, a4, 7
916 ; RV64IM-NEXT: addi a5, zero, 654
917 ; RV64IM-NEXT: mulw a4, a4, a5
918 ; RV64IM-NEXT: subw a3, a3, a4
919 ; RV64IM-NEXT: lui a4, 1044567
920 ; RV64IM-NEXT: addiw a4, a4, -575
921 ; RV64IM-NEXT: slli a4, a4, 12
922 ; RV64IM-NEXT: addi a4, a4, 883
923 ; RV64IM-NEXT: slli a4, a4, 14
924 ; RV64IM-NEXT: addi a4, a4, -861
925 ; RV64IM-NEXT: slli a4, a4, 12
926 ; RV64IM-NEXT: addi a4, a4, -179
927 ; RV64IM-NEXT: mulhu a4, a2, a4
928 ; RV64IM-NEXT: srli a4, a4, 12
929 ; RV64IM-NEXT: lui a5, 1
930 ; RV64IM-NEXT: addiw a5, a5, 1327
931 ; RV64IM-NEXT: mulw a4, a4, a5
932 ; RV64IM-NEXT: subw a2, a2, a4
933 ; RV64IM-NEXT: sh zero, 0(a0)
934 ; RV64IM-NEXT: sh a2, 6(a0)
935 ; RV64IM-NEXT: sh a3, 2(a0)
936 ; RV64IM-NEXT: sh a1, 4(a0)
937 ; RV64IM-NEXT: ret
938 %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
939 ret <4 x i16> %1
940 }
942 ; Don't fold if the divisor is 2^16.
943 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
944 ; CHECK-LABEL: dont_fold_urem_i16_smax:
945 ; CHECK: # %bb.0:
946 ; CHECK-NEXT: ret
947 %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
948 ret <4 x i16> %1
949 }
951 ; Don't fold i64 urem.
952 define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind {
953 ; RV32I-LABEL: dont_fold_urem_i64:
954 ; RV32I: # %bb.0:
955 ; RV32I-NEXT: addi sp, sp, -48
956 ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
957 ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
958 ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
959 ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
960 ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
961 ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
962 ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
963 ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
964 ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
965 ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
966 ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
967 ; RV32I-NEXT: lw s2, 24(a1)
968 ; RV32I-NEXT: lw s3, 28(a1)
969 ; RV32I-NEXT: lw s4, 16(a1)
970 ; RV32I-NEXT: lw s5, 20(a1)
971 ; RV32I-NEXT: lw s6, 8(a1)
972 ; RV32I-NEXT: lw s1, 12(a1)
973 ; RV32I-NEXT: lw a3, 0(a1)
974 ; RV32I-NEXT: lw a1, 4(a1)
975 ; RV32I-NEXT: mv s0, a0
976 ; RV32I-NEXT: addi a2, zero, 1
977 ; RV32I-NEXT: mv a0, a3
978 ; RV32I-NEXT: mv a3, zero
979 ; RV32I-NEXT: call __umoddi3@plt
980 ; RV32I-NEXT: mv s7, a0
981 ; RV32I-NEXT: mv s8, a1
982 ; RV32I-NEXT: addi a2, zero, 654
983 ; RV32I-NEXT: mv a0, s6
984 ; RV32I-NEXT: mv a1, s1
985 ; RV32I-NEXT: mv a3, zero
986 ; RV32I-NEXT: call __umoddi3@plt
987 ; RV32I-NEXT: mv s6, a0
988 ; RV32I-NEXT: mv s9, a1
989 ; RV32I-NEXT: addi a2, zero, 23
990 ; RV32I-NEXT: mv a0, s4
991 ; RV32I-NEXT: mv a1, s5
992 ; RV32I-NEXT: mv a3, zero
993 ; RV32I-NEXT: call __umoddi3@plt
994 ; RV32I-NEXT: mv s4, a0
995 ; RV32I-NEXT: mv s1, a1
996 ; RV32I-NEXT: lui a0, 1
997 ; RV32I-NEXT: addi a2, a0, 1327
998 ; RV32I-NEXT: mv a0, s2
999 ; RV32I-NEXT: mv a1, s3
1000 ; RV32I-NEXT: mv a3, zero
1001 ; RV32I-NEXT: call __umoddi3@plt
1002 ; RV32I-NEXT: sw a1, 28(s0)
1003 ; RV32I-NEXT: sw a0, 24(s0)
1004 ; RV32I-NEXT: sw s1, 20(s0)
1005 ; RV32I-NEXT: sw s4, 16(s0)
1006 ; RV32I-NEXT: sw s9, 12(s0)
1007 ; RV32I-NEXT: sw s6, 8(s0)
1008 ; RV32I-NEXT: sw s8, 4(s0)
1009 ; RV32I-NEXT: sw s7, 0(s0)
1010 ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
1011 ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
1012 ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
1013 ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
1014 ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
1015 ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
1016 ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
1017 ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
1018 ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
1019 ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
1020 ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
1021 ; RV32I-NEXT: addi sp, sp, 48
1022 ; RV32I-NEXT: ret
1023 ;
1024 ; RV32IM-LABEL: dont_fold_urem_i64:
1025 ; RV32IM: # %bb.0:
1026 ; RV32IM-NEXT: addi sp, sp, -48
1027 ; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
1028 ; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
1029 ; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
1030 ; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
1031 ; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
1032 ; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
1033 ; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
1034 ; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
1035 ; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
1036 ; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
1037 ; RV32IM-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
1038 ; RV32IM-NEXT: lw s2, 24(a1)
1039 ; RV32IM-NEXT: lw s3, 28(a1)
1040 ; RV32IM-NEXT: lw s4, 16(a1)
1041 ; RV32IM-NEXT: lw s5, 20(a1)
1042 ; RV32IM-NEXT: lw s6, 8(a1)
1043 ; RV32IM-NEXT: lw s1, 12(a1)
1044 ; RV32IM-NEXT: lw a3, 0(a1)
1045 ; RV32IM-NEXT: lw a1, 4(a1)
1046 ; RV32IM-NEXT: mv s0, a0
1047 ; RV32IM-NEXT: addi a2, zero, 1
1048 ; RV32IM-NEXT: mv a0, a3
1049 ; RV32IM-NEXT: mv a3, zero
1050 ; RV32IM-NEXT: call __umoddi3@plt
1051 ; RV32IM-NEXT: mv s7, a0
1052 ; RV32IM-NEXT: mv s8, a1
1053 ; RV32IM-NEXT: addi a2, zero, 654
1054 ; RV32IM-NEXT: mv a0, s6
1055 ; RV32IM-NEXT: mv a1, s1
1056 ; RV32IM-NEXT: mv a3, zero
1057 ; RV32IM-NEXT: call __umoddi3@plt
1058 ; RV32IM-NEXT: mv s6, a0
1059 ; RV32IM-NEXT: mv s9, a1
1060 ; RV32IM-NEXT: addi a2, zero, 23
1061 ; RV32IM-NEXT: mv a0, s4
1062 ; RV32IM-NEXT: mv a1, s5
1063 ; RV32IM-NEXT: mv a3, zero
1064 ; RV32IM-NEXT: call __umoddi3@plt
1065 ; RV32IM-NEXT: mv s4, a0
1066 ; RV32IM-NEXT: mv s1, a1
1067 ; RV32IM-NEXT: lui a0, 1
1068 ; RV32IM-NEXT: addi a2, a0, 1327
1069 ; RV32IM-NEXT: mv a0, s2
1070 ; RV32IM-NEXT: mv a1, s3
1071 ; RV32IM-NEXT: mv a3, zero
1072 ; RV32IM-NEXT: call __umoddi3@plt
1073 ; RV32IM-NEXT: sw a1, 28(s0)
1074 ; RV32IM-NEXT: sw a0, 24(s0)
1075 ; RV32IM-NEXT: sw s1, 20(s0)
1076 ; RV32IM-NEXT: sw s4, 16(s0)
1077 ; RV32IM-NEXT: sw s9, 12(s0)
1078 ; RV32IM-NEXT: sw s6, 8(s0)
1079 ; RV32IM-NEXT: sw s8, 4(s0)
1080 ; RV32IM-NEXT: sw s7, 0(s0)
1081 ; RV32IM-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
1082 ; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
1083 ; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
1084 ; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
1085 ; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
1086 ; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
1087 ; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
1088 ; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
1089 ; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
1090 ; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
1091 ; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
1092 ; RV32IM-NEXT: addi sp, sp, 48
1093 ; RV32IM-NEXT: ret
1094 ;
1095 ; RV64I-LABEL: dont_fold_urem_i64:
1096 ; RV64I: # %bb.0:
1097 ; RV64I-NEXT: addi sp, sp, -48
1098 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
1099 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
1100 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
1101 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
1102 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
1103 ; RV64I-NEXT: ld s2, 24(a1)
1104 ; RV64I-NEXT: ld s1, 16(a1)
1105 ; RV64I-NEXT: ld a2, 8(a1)
1106 ; RV64I-NEXT: mv s0, a0
1107 ; RV64I-NEXT: addi a1, zero, 654
1108 ; RV64I-NEXT: mv a0, a2
1109 ; RV64I-NEXT: call __umoddi3@plt
1110 ; RV64I-NEXT: mv s3, a0
1111 ; RV64I-NEXT: addi a1, zero, 23
1112 ; RV64I-NEXT: mv a0, s1
1113 ; RV64I-NEXT: call __umoddi3@plt
1114 ; RV64I-NEXT: mv s1, a0
1115 ; RV64I-NEXT: lui a0, 1
1116 ; RV64I-NEXT: addiw a1, a0, 1327
1117 ; RV64I-NEXT: mv a0, s2
1118 ; RV64I-NEXT: call __umoddi3@plt
1119 ; RV64I-NEXT: sd zero, 0(s0)
1120 ; RV64I-NEXT: sd a0, 24(s0)
1121 ; RV64I-NEXT: sd s1, 16(s0)
1122 ; RV64I-NEXT: sd s3, 8(s0)
1123 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
1124 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
1125 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
1126 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
1127 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
1128 ; RV64I-NEXT: addi sp, sp, 48
1129 ; RV64I-NEXT: ret
1130 ;
1131 ; RV64IM-LABEL: dont_fold_urem_i64:
1132 ; RV64IM: # %bb.0:
1133 ; RV64IM-NEXT: ld a2, 24(a1)
1134 ; RV64IM-NEXT: ld a3, 8(a1)
1135 ; RV64IM-NEXT: ld a1, 16(a1)
1136 ; RV64IM-NEXT: lui a4, 3206
1137 ; RV64IM-NEXT: addiw a4, a4, -1781
1138 ; RV64IM-NEXT: slli a4, a4, 13
1139 ; RV64IM-NEXT: addi a4, a4, 1069
1140 ; RV64IM-NEXT: slli a4, a4, 12
1141 ; RV64IM-NEXT: addi a4, a4, -1959
1142 ; RV64IM-NEXT: slli a4, a4, 14
1143 ; RV64IM-NEXT: addi a4, a4, 713
1144 ; RV64IM-NEXT: mulhu a4, a1, a4
1145 ; RV64IM-NEXT: sub a5, a1, a4
1146 ; RV64IM-NEXT: srli a5, a5, 1
1147 ; RV64IM-NEXT: add a4, a5, a4
1148 ; RV64IM-NEXT: srli a4, a4, 4
1149 ; RV64IM-NEXT: addi a5, zero, 23
1150 ; RV64IM-NEXT: mul a4, a4, a5
1151 ; RV64IM-NEXT: sub a1, a1, a4
1152 ; RV64IM-NEXT: srli a4, a3, 1
1153 ; RV64IM-NEXT: lui a5, 6413
1154 ; RV64IM-NEXT: addiw a5, a5, 1265
1155 ; RV64IM-NEXT: slli a5, a5, 13
1156 ; RV64IM-NEXT: addi a5, a5, 1027
1157 ; RV64IM-NEXT: slli a5, a5, 13
1158 ; RV64IM-NEXT: addi a5, a5, 1077
1159 ; RV64IM-NEXT: slli a5, a5, 12
1160 ; RV64IM-NEXT: addi a5, a5, 965
1161 ; RV64IM-NEXT: mulhu a4, a4, a5
1162 ; RV64IM-NEXT: srli a4, a4, 7
1163 ; RV64IM-NEXT: addi a5, zero, 654
1164 ; RV64IM-NEXT: mul a4, a4, a5
1165 ; RV64IM-NEXT: sub a3, a3, a4
1166 ; RV64IM-NEXT: lui a4, 1044567
1167 ; RV64IM-NEXT: addiw a4, a4, -575
1168 ; RV64IM-NEXT: slli a4, a4, 12
1169 ; RV64IM-NEXT: addi a4, a4, 883
1170 ; RV64IM-NEXT: slli a4, a4, 14
1171 ; RV64IM-NEXT: addi a4, a4, -861
1172 ; RV64IM-NEXT: slli a4, a4, 12
1173 ; RV64IM-NEXT: addi a4, a4, -179
1174 ; RV64IM-NEXT: mulhu a4, a2, a4
1175 ; RV64IM-NEXT: srli a4, a4, 12
1176 ; RV64IM-NEXT: lui a5, 1
1177 ; RV64IM-NEXT: addiw a5, a5, 1327
1178 ; RV64IM-NEXT: mul a4, a4, a5
1179 ; RV64IM-NEXT: sub a2, a2, a4
1180 ; RV64IM-NEXT: sd zero, 0(a0)
1181 ; RV64IM-NEXT: sd a2, 24(a0)
1182 ; RV64IM-NEXT: sd a3, 8(a0)
1183 ; RV64IM-NEXT: sd a1, 16(a0)
1184 ; RV64IM-NEXT: ret
1185 %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
1186 ret <4 x i64> %1
1187 }