1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
3 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
4 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
5 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
7 declare i4 @llvm.usub.sat.i4(i4, i4)
8 declare i8 @llvm.usub.sat.i8(i8, i8)
9 declare i16 @llvm.usub.sat.i16(i16, i16)
10 declare i32 @llvm.usub.sat.i32(i32, i32)
11 declare i64 @llvm.usub.sat.i64(i64, i64)
13 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
16 ; RV32I-NEXT: mv a2, a0
17 ; RV32I-NEXT: sub a1, a0, a1
18 ; RV32I-NEXT: mv a0, zero
19 ; RV32I-NEXT: bltu a2, a1, .LBB0_2
20 ; RV32I-NEXT: # %bb.1:
21 ; RV32I-NEXT: mv a0, a1
22 ; RV32I-NEXT: .LBB0_2:
27 ; RV64I-NEXT: mv a2, a0
28 ; RV64I-NEXT: subw a1, a0, a1
29 ; RV64I-NEXT: mv a0, zero
30 ; RV64I-NEXT: bltu a2, a1, .LBB0_2
31 ; RV64I-NEXT: # %bb.1:
32 ; RV64I-NEXT: mv a0, a1
33 ; RV64I-NEXT: .LBB0_2:
36 ; RV32IZbb-LABEL: func:
38 ; RV32IZbb-NEXT: maxu a0, a0, a1
39 ; RV32IZbb-NEXT: sub a0, a0, a1
42 ; RV64IZbb-LABEL: func:
44 ; RV64IZbb-NEXT: maxu a0, a0, a1
45 ; RV64IZbb-NEXT: subw a0, a0, a1
47 %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y);
51 define i64 @func2(i64 %x, i64 %y) nounwind {
54 ; RV32I-NEXT: sltu a4, a0, a2
55 ; RV32I-NEXT: sub a3, a1, a3
56 ; RV32I-NEXT: sub a3, a3, a4
57 ; RV32I-NEXT: sub a2, a0, a2
58 ; RV32I-NEXT: beq a3, a1, .LBB1_2
59 ; RV32I-NEXT: # %bb.1:
60 ; RV32I-NEXT: sltu a4, a1, a3
61 ; RV32I-NEXT: j .LBB1_3
62 ; RV32I-NEXT: .LBB1_2:
63 ; RV32I-NEXT: sltu a4, a0, a2
64 ; RV32I-NEXT: .LBB1_3:
65 ; RV32I-NEXT: mv a0, zero
66 ; RV32I-NEXT: mv a1, zero
67 ; RV32I-NEXT: bnez a4, .LBB1_5
68 ; RV32I-NEXT: # %bb.4:
69 ; RV32I-NEXT: mv a0, a2
70 ; RV32I-NEXT: mv a1, a3
71 ; RV32I-NEXT: .LBB1_5:
76 ; RV64I-NEXT: mv a2, a0
77 ; RV64I-NEXT: sub a1, a0, a1
78 ; RV64I-NEXT: mv a0, zero
79 ; RV64I-NEXT: bltu a2, a1, .LBB1_2
80 ; RV64I-NEXT: # %bb.1:
81 ; RV64I-NEXT: mv a0, a1
82 ; RV64I-NEXT: .LBB1_2:
85 ; RV32IZbb-LABEL: func2:
87 ; RV32IZbb-NEXT: sltu a4, a0, a2
88 ; RV32IZbb-NEXT: sub a3, a1, a3
89 ; RV32IZbb-NEXT: sub a3, a3, a4
90 ; RV32IZbb-NEXT: sub a2, a0, a2
91 ; RV32IZbb-NEXT: beq a3, a1, .LBB1_2
92 ; RV32IZbb-NEXT: # %bb.1:
93 ; RV32IZbb-NEXT: sltu a4, a1, a3
94 ; RV32IZbb-NEXT: j .LBB1_3
95 ; RV32IZbb-NEXT: .LBB1_2:
96 ; RV32IZbb-NEXT: sltu a4, a0, a2
97 ; RV32IZbb-NEXT: .LBB1_3:
98 ; RV32IZbb-NEXT: mv a0, zero
99 ; RV32IZbb-NEXT: mv a1, zero
100 ; RV32IZbb-NEXT: bnez a4, .LBB1_5
101 ; RV32IZbb-NEXT: # %bb.4:
102 ; RV32IZbb-NEXT: mv a0, a2
103 ; RV32IZbb-NEXT: mv a1, a3
104 ; RV32IZbb-NEXT: .LBB1_5:
107 ; RV64IZbb-LABEL: func2:
109 ; RV64IZbb-NEXT: maxu a0, a0, a1
110 ; RV64IZbb-NEXT: sub a0, a0, a1
112 %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y);
116 define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
117 ; RV32I-LABEL: func16:
119 ; RV32I-NEXT: mv a2, a0
120 ; RV32I-NEXT: sub a1, a0, a1
121 ; RV32I-NEXT: mv a0, zero
122 ; RV32I-NEXT: bltu a2, a1, .LBB2_2
123 ; RV32I-NEXT: # %bb.1:
124 ; RV32I-NEXT: mv a0, a1
125 ; RV32I-NEXT: .LBB2_2:
128 ; RV64I-LABEL: func16:
130 ; RV64I-NEXT: mv a2, a0
131 ; RV64I-NEXT: sub a1, a0, a1
132 ; RV64I-NEXT: mv a0, zero
133 ; RV64I-NEXT: bltu a2, a1, .LBB2_2
134 ; RV64I-NEXT: # %bb.1:
135 ; RV64I-NEXT: mv a0, a1
136 ; RV64I-NEXT: .LBB2_2:
139 ; RV32IZbb-LABEL: func16:
141 ; RV32IZbb-NEXT: maxu a0, a0, a1
142 ; RV32IZbb-NEXT: sub a0, a0, a1
145 ; RV64IZbb-LABEL: func16:
147 ; RV64IZbb-NEXT: maxu a0, a0, a1
148 ; RV64IZbb-NEXT: sub a0, a0, a1
150 %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
154 define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
155 ; RV32I-LABEL: func8:
157 ; RV32I-NEXT: mv a2, a0
158 ; RV32I-NEXT: sub a1, a0, a1
159 ; RV32I-NEXT: mv a0, zero
160 ; RV32I-NEXT: bltu a2, a1, .LBB3_2
161 ; RV32I-NEXT: # %bb.1:
162 ; RV32I-NEXT: mv a0, a1
163 ; RV32I-NEXT: .LBB3_2:
166 ; RV64I-LABEL: func8:
168 ; RV64I-NEXT: mv a2, a0
169 ; RV64I-NEXT: sub a1, a0, a1
170 ; RV64I-NEXT: mv a0, zero
171 ; RV64I-NEXT: bltu a2, a1, .LBB3_2
172 ; RV64I-NEXT: # %bb.1:
173 ; RV64I-NEXT: mv a0, a1
174 ; RV64I-NEXT: .LBB3_2:
177 ; RV32IZbb-LABEL: func8:
179 ; RV32IZbb-NEXT: maxu a0, a0, a1
180 ; RV32IZbb-NEXT: sub a0, a0, a1
183 ; RV64IZbb-LABEL: func8:
185 ; RV64IZbb-NEXT: maxu a0, a0, a1
186 ; RV64IZbb-NEXT: sub a0, a0, a1
188 %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
192 define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
193 ; RV32I-LABEL: func3:
195 ; RV32I-NEXT: mv a2, a0
196 ; RV32I-NEXT: sub a1, a0, a1
197 ; RV32I-NEXT: mv a0, zero
198 ; RV32I-NEXT: bltu a2, a1, .LBB4_2
199 ; RV32I-NEXT: # %bb.1:
200 ; RV32I-NEXT: mv a0, a1
201 ; RV32I-NEXT: .LBB4_2:
204 ; RV64I-LABEL: func3:
206 ; RV64I-NEXT: mv a2, a0
207 ; RV64I-NEXT: sub a1, a0, a1
208 ; RV64I-NEXT: mv a0, zero
209 ; RV64I-NEXT: bltu a2, a1, .LBB4_2
210 ; RV64I-NEXT: # %bb.1:
211 ; RV64I-NEXT: mv a0, a1
212 ; RV64I-NEXT: .LBB4_2:
215 ; RV32IZbb-LABEL: func3:
217 ; RV32IZbb-NEXT: maxu a0, a0, a1
218 ; RV32IZbb-NEXT: sub a0, a0, a1
221 ; RV64IZbb-LABEL: func3:
223 ; RV64IZbb-NEXT: maxu a0, a0, a1
224 ; RV64IZbb-NEXT: sub a0, a0, a1
226 %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);