| blob | 2bc521ed87d1c0e63d66a61aa30956200e43c073 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -enable-arm-maskedgatscat=false %s -o - | FileCheck %s
4 define void @remat_vctp(i32* %arg, i32* %arg1, i32* %arg2, i32* %arg3, i32* %arg4, i16 zeroext %arg5) {
5 ; CHECK-LABEL: remat_vctp:
6 ; CHECK: @ %bb.0: @ %bb
7 ; CHECK-NEXT: push {r4, r5, r7, lr}
8 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
9 ; CHECK-NEXT: ldrd r5, r12, [sp, #80]
10 ; CHECK-NEXT: vmvn.i32 q0, #0x80000000
11 ; CHECK-NEXT: vmov.i32 q1, #0x3f
12 ; CHECK-NEXT: vmov.i32 q2, #0x1
13 ; CHECK-NEXT: dlstp.32 lr, r12
14 ; CHECK-NEXT: .LBB0_1: @ %bb6
15 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
16 ; CHECK-NEXT: vldrw.u32 q4, [r1], #16
17 ; CHECK-NEXT: vabs.s32 q5, q4
18 ; CHECK-NEXT: vcls.s32 q3, q5
19 ; CHECK-NEXT: vshl.u32 q5, q5, q3
20 ; CHECK-NEXT: vadd.i32 q3, q3, q2
21 ; CHECK-NEXT: vshr.u32 q6, q5, #24
22 ; CHECK-NEXT: vand q6, q6, q1
23 ; CHECK-NEXT: vldrw.u32 q7, [r5, q6, uxtw #2]
24 ; CHECK-NEXT: vqrdmulh.s32 q6, q7, q5
25 ; CHECK-NEXT: vqsub.s32 q6, q0, q6
26 ; CHECK-NEXT: vqrdmulh.s32 q6, q7, q6
27 ; CHECK-NEXT: vqshl.s32 q6, q6, #1
28 ; CHECK-NEXT: vqrdmulh.s32 q5, q6, q5
29 ; CHECK-NEXT: vqsub.s32 q5, q0, q5
30 ; CHECK-NEXT: vqrdmulh.s32 q5, q6, q5
31 ; CHECK-NEXT: vqshl.s32 q5, q5, #1
32 ; CHECK-NEXT: vpt.s32 lt, q4, zr
33 ; CHECK-NEXT: vnegt.s32 q5, q5
34 ; CHECK-NEXT: vldrw.u32 q4, [r0], #16
35 ; CHECK-NEXT: vqrdmulh.s32 q4, q4, q5
36 ; CHECK-NEXT: vstrw.32 q4, [r2], #16
37 ; CHECK-NEXT: vstrw.32 q3, [r3], #16
38 ; CHECK-NEXT: letp lr, .LBB0_1
39 ; CHECK-NEXT: @ %bb.2: @ %bb44
40 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
41 ; CHECK-NEXT: pop {r4, r5, r7, pc}
42 bb:
43 %i = zext i16 %arg5 to i32
44 br label %bb6
46 bb6: ; preds = %bb6, %bb
47 %i7 = phi i32* [ %arg3, %bb ], [ %i38, %bb6 ]
48 %i8 = phi i32 [ %i, %bb ], [ %i42, %bb6 ]
49 %i9 = phi i32* [ %arg2, %bb ], [ %i41, %bb6 ]
50 %i10 = phi i32* [ %arg1, %bb ], [ %i40, %bb6 ]
51 %i11 = phi i32* [ %arg, %bb ], [ %i39, %bb6 ]
52 %i12 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %i8)
53 %i13 = bitcast i32* %i11 to <4 x i32>*
54 %i14 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %i13, i32 4, <4 x i1> %i12, <4 x i32> zeroinitializer)
55 %i15 = bitcast i32* %i10 to <4 x i32>*
56 %i16 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %i15, i32 4, <4 x i1> %i12, <4 x i32> zeroinitializer)
57 %i17 = icmp slt <4 x i32> %i16, zeroinitializer
58 %i18 = sub <4 x i32> zeroinitializer, %i16
59 %i19 = select <4 x i1> %i17, <4 x i32> %i18, <4 x i32> %i16
60 %i20 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %i19)
61 %i21 = shl <4 x i32> %i19, %i20
62 %i22 = add <4 x i32> %i20, <i32 1, i32 1, i32 1, i32 1>
63 %i23 = lshr <4 x i32> %i21, <i32 24, i32 24, i32 24, i32 24>
64 %i24 = and <4 x i32> %i23, <i32 63, i32 63, i32 63, i32 63>
65 %i25 = tail call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0i32.v4i32(i32* %arg4, <4 x i32> %i24, i32 32, i32 2, i32 0)
66 %i26 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i21)
67 %i27 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i26)
68 %i28 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i27)
69 %i29 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i28, i32 1, i32 0)
70 %i30 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i21)
71 %i31 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i30)
72 %i32 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i31)
73 %i33 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i32, i32 1, i32 0)
74 %i34 = tail call <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32> %i33, <4 x i1> %i17, <4 x i32> %i33)
75 %i35 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i14, <4 x i32> %i34)
76 %i36 = bitcast i32* %i9 to <4 x i32>*
77 %i37 = bitcast i32* %i7 to <4 x i32>*
78 tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %i35, <4 x i32>* %i36, i32 4, <4 x i1> %i12)
79 tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %i22, <4 x i32>* %i37, i32 4, <4 x i1> %i12)
80 %i38 = getelementptr inbounds i32, i32* %i7, i32 4
81 %i39 = getelementptr inbounds i32, i32* %i11, i32 4
82 %i40 = getelementptr inbounds i32, i32* %i10, i32 4
83 %i41 = getelementptr inbounds i32, i32* %i9, i32 4
84 %i42 = add nsw i32 %i8, -4
85 %i43 = icmp sgt i32 %i8, 4
86 br i1 %i43, label %bb6, label %bb44
88 bb44: ; preds = %bb6
89 ret void
90 }
92 define void @dont_remat_predicated_vctp(i32* %arg, i32* %arg1, i32* %arg2, i32* %arg3, i32* %arg4, i16 zeroext %arg5, i32 %conv.mask) {
93 ; CHECK-LABEL: dont_remat_predicated_vctp:
94 ; CHECK: @ %bb.0: @ %bb
95 ; CHECK-NEXT: push {r4, r5, r6, lr}
96 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
97 ; CHECK-NEXT: sub sp, #8
98 ; CHECK-NEXT: ldrd r6, r12, [sp, #88]
99 ; CHECK-NEXT: movs r4, #4
100 ; CHECK-NEXT: cmp.w r12, #4
101 ; CHECK-NEXT: vmvn.i32 q0, #0x80000000
102 ; CHECK-NEXT: csel r5, r12, r4, lt
103 ; CHECK-NEXT: vmov.i32 q1, #0x3f
104 ; CHECK-NEXT: sub.w r5, r12, r5
105 ; CHECK-NEXT: vmov.i32 q2, #0x1
106 ; CHECK-NEXT: add.w lr, r5, #3
107 ; CHECK-NEXT: movs r5, #1
108 ; CHECK-NEXT: add.w lr, r5, lr, lsr #2
109 ; CHECK-NEXT: .LBB1_1: @ %bb6
110 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
111 ; CHECK-NEXT: vctp.32 r12
112 ; CHECK-NEXT: sub.w r12, r12, #4
113 ; CHECK-NEXT: vpst
114 ; CHECK-NEXT: vctpt.32 r4
115 ; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
116 ; CHECK-NEXT: vpst
117 ; CHECK-NEXT: vldrwt.u32 q4, [r1], #16
118 ; CHECK-NEXT: vabs.s32 q5, q4
119 ; CHECK-NEXT: vcls.s32 q3, q5
120 ; CHECK-NEXT: vshl.u32 q5, q5, q3
121 ; CHECK-NEXT: vadd.i32 q3, q3, q2
122 ; CHECK-NEXT: vshr.u32 q6, q5, #24
123 ; CHECK-NEXT: vand q6, q6, q1
124 ; CHECK-NEXT: vldrw.u32 q7, [r6, q6, uxtw #2]
125 ; CHECK-NEXT: vqrdmulh.s32 q6, q7, q5
126 ; CHECK-NEXT: vqsub.s32 q6, q0, q6
127 ; CHECK-NEXT: vqrdmulh.s32 q6, q7, q6
128 ; CHECK-NEXT: vqshl.s32 q6, q6, #1
129 ; CHECK-NEXT: vqrdmulh.s32 q5, q6, q5
130 ; CHECK-NEXT: vqsub.s32 q5, q0, q5
131 ; CHECK-NEXT: vqrdmulh.s32 q5, q6, q5
132 ; CHECK-NEXT: vqshl.s32 q5, q5, #1
133 ; CHECK-NEXT: vpt.s32 lt, q4, zr
134 ; CHECK-NEXT: vnegt.s32 q5, q5
135 ; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
136 ; CHECK-NEXT: vpst
137 ; CHECK-NEXT: vldrwt.u32 q4, [r0], #16
138 ; CHECK-NEXT: vqrdmulh.s32 q4, q4, q5
139 ; CHECK-NEXT: vpstt
140 ; CHECK-NEXT: vstrwt.32 q4, [r2], #16
141 ; CHECK-NEXT: vstrwt.32 q3, [r3], #16
142 ; CHECK-NEXT: le lr, .LBB1_1
143 ; CHECK-NEXT: @ %bb.2: @ %bb44
144 ; CHECK-NEXT: add sp, #8
145 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
146 ; CHECK-NEXT: pop {r4, r5, r6, pc}
147 bb:
148 %i = zext i16 %arg5 to i32
149 br label %bb6
151 bb6: ; preds = %bb6, %bb
152 %i7 = phi i32* [ %arg3, %bb ], [ %i38, %bb6 ]
153 %i8 = phi i32 [ %i, %bb ], [ %i42, %bb6 ]
154 %i9 = phi i32* [ %arg2, %bb ], [ %i41, %bb6 ]
155 %i10 = phi i32* [ %arg1, %bb ], [ %i40, %bb6 ]
156 %i11 = phi i32* [ %arg, %bb ], [ %i39, %bb6 ]
157 %i12 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 4)
158 %mask = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %i8)
159 %pred = and <4 x i1> %i12, %mask
160 %i13 = bitcast i32* %i11 to <4 x i32>*
161 %i14 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %i13, i32 4, <4 x i1> %pred, <4 x i32> zeroinitializer)
162 %i15 = bitcast i32* %i10 to <4 x i32>*
163 %i16 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %i15, i32 4, <4 x i1> %pred, <4 x i32> zeroinitializer)
164 %i17 = icmp slt <4 x i32> %i16, zeroinitializer
165 %i18 = sub <4 x i32> zeroinitializer, %i16
166 %i19 = select <4 x i1> %i17, <4 x i32> %i18, <4 x i32> %i16
167 %i20 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %i19)
168 %i21 = shl <4 x i32> %i19, %i20
169 %i22 = add <4 x i32> %i20, <i32 1, i32 1, i32 1, i32 1>
170 %i23 = lshr <4 x i32> %i21, <i32 24, i32 24, i32 24, i32 24>
171 %i24 = and <4 x i32> %i23, <i32 63, i32 63, i32 63, i32 63>
172 %i25 = tail call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0i32.v4i32(i32* %arg4, <4 x i32> %i24, i32 32, i32 2, i32 0)
173 %i26 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i21)
174 %i27 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i26)
175 %i28 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i27)
176 %i29 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i28, i32 1, i32 0)
177 %i30 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i21)
178 %i31 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %i30)
179 %i32 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i31)
180 %i33 = tail call <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32> %i32, i32 1, i32 0)
181 %i34 = tail call <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32> %i33, <4 x i1> %i17, <4 x i32> %i33)
182 %i35 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i14, <4 x i32> %i34)
183 %i36 = bitcast i32* %i9 to <4 x i32>*
184 %i37 = bitcast i32* %i7 to <4 x i32>*
185 tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %i35, <4 x i32>* %i36, i32 4, <4 x i1> %pred)
186 tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %i22, <4 x i32>* %i37, i32 4, <4 x i1> %pred)
187 %i38 = getelementptr inbounds i32, i32* %i7, i32 4
188 %i39 = getelementptr inbounds i32, i32* %i11, i32 4
189 %i40 = getelementptr inbounds i32, i32* %i10, i32 4
190 %i41 = getelementptr inbounds i32, i32* %i9, i32 4
191 %i42 = add nsw i32 %i8, -4
192 %i43 = icmp sgt i32 %i8, 4
193 br i1 %i43, label %bb6, label %bb44
195 bb44: ; preds = %bb6
196 ret void
197 }
199 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
200 declare <4 x i1> @llvm.arm.mve.vctp32(i32)
201 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
202 declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
203 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
204 declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>)
205 declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0i32.v4i32(i32*, <4 x i32>, i32, i32, i32)
206 declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
207 declare <4 x i32> @llvm.arm.mve.vqshl.imm.v4i32(<4 x i32>, i32, i32)
208 declare <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)