| blob | 607a55b52370bdde13a6717ed9b43b356a448d2b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s
4 define <4 x i32> @v4i32(i32 %index, i32 %TC, <4 x i32> %V1, <4 x i32> %V2) {
5 ; CHECK-LABEL: v4i32:
6 ; CHECK: @ %bb.0:
7 ; CHECK-NEXT: adr.w r12, .LCPI0_0
8 ; CHECK-NEXT: vdup.32 q1, r0
9 ; CHECK-NEXT: vldrw.u32 q0, [r12]
10 ; CHECK-NEXT: vadd.i32 q0, q0, r0
11 ; CHECK-NEXT: add r0, sp, #8
12 ; CHECK-NEXT: vcmp.u32 hi, q1, q0
13 ; CHECK-NEXT: vdup.32 q1, r1
14 ; CHECK-NEXT: vpnot
15 ; CHECK-NEXT: vpst
16 ; CHECK-NEXT: vcmpt.u32 hi, q1, q0
17 ; CHECK-NEXT: vldr d1, [sp]
18 ; CHECK-NEXT: vldrw.u32 q1, [r0]
19 ; CHECK-NEXT: vmov d0, r2, r3
20 ; CHECK-NEXT: vpsel q0, q0, q1
21 ; CHECK-NEXT: vmov r0, r1, d0
22 ; CHECK-NEXT: vmov r2, r3, d1
23 ; CHECK-NEXT: bx lr
24 ; CHECK-NEXT: .p2align 4
25 ; CHECK-NEXT: @ %bb.1:
26 ; CHECK-NEXT: .LCPI0_0:
27 ; CHECK-NEXT: .long 0 @ 0x0
28 ; CHECK-NEXT: .long 1 @ 0x1
29 ; CHECK-NEXT: .long 2 @ 0x2
30 ; CHECK-NEXT: .long 3 @ 0x3
31 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)
32 %select = select <4 x i1> %active.lane.mask, <4 x i32> %V1, <4 x i32> %V2
33 ret <4 x i32> %select
34 }
36 define <7 x i32> @v7i32(i32 %index, i32 %TC, <7 x i32> %V1, <7 x i32> %V2) {
37 ; CHECK-LABEL: v7i32:
38 ; CHECK: @ %bb.0:
39 ; CHECK-NEXT: adr r3, .LCPI1_0
40 ; CHECK-NEXT: vdup.32 q1, r1
41 ; CHECK-NEXT: vldrw.u32 q0, [r3]
42 ; CHECK-NEXT: ldr r3, [sp, #32]
43 ; CHECK-NEXT: vadd.i32 q2, q0, r1
44 ; CHECK-NEXT: vdup.32 q0, r2
45 ; CHECK-NEXT: vcmp.u32 hi, q1, q2
46 ; CHECK-NEXT: ldr r2, [sp, #40]
47 ; CHECK-NEXT: vpnot
48 ; CHECK-NEXT: vpst
49 ; CHECK-NEXT: vcmpt.u32 hi, q0, q2
50 ; CHECK-NEXT: vmov q2[2], q2[0], r3, r2
51 ; CHECK-NEXT: ldr r2, [sp, #44]
52 ; CHECK-NEXT: ldr r3, [sp, #36]
53 ; CHECK-NEXT: vmov q2[3], q2[1], r3, r2
54 ; CHECK-NEXT: ldr r2, [sp, #8]
55 ; CHECK-NEXT: ldr r3, [sp]
56 ; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
57 ; CHECK-NEXT: ldr r2, [sp, #12]
58 ; CHECK-NEXT: ldr r3, [sp, #4]
59 ; CHECK-NEXT: vmov q3[3], q3[1], r3, r2
60 ; CHECK-NEXT: adr r2, .LCPI1_1
61 ; CHECK-NEXT: vpsel q2, q3, q2
62 ; CHECK-NEXT: vstrw.32 q2, [r0]
63 ; CHECK-NEXT: vldrw.u32 q2, [r2]
64 ; CHECK-NEXT: movw r2, #4095
65 ; CHECK-NEXT: vadd.i32 q2, q2, r1
66 ; CHECK-NEXT: vcmp.u32 hi, q1, q2
67 ; CHECK-NEXT: vmrs r1, p0
68 ; CHECK-NEXT: eors r1, r2
69 ; CHECK-NEXT: ldr r2, [sp, #48]
70 ; CHECK-NEXT: vmsr p0, r1
71 ; CHECK-NEXT: ldr r1, [sp, #52]
72 ; CHECK-NEXT: vpst
73 ; CHECK-NEXT: vcmpt.u32 hi, q0, q2
74 ; CHECK-NEXT: vmov.32 q0[1], r1
75 ; CHECK-NEXT: ldr r1, [sp, #56]
76 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r1
77 ; CHECK-NEXT: ldr r1, [sp, #20]
78 ; CHECK-NEXT: ldr r2, [sp, #16]
79 ; CHECK-NEXT: vmov.32 q1[1], r1
80 ; CHECK-NEXT: ldr r1, [sp, #24]
81 ; CHECK-NEXT: vmov q1[2], q1[0], r2, r1
82 ; CHECK-NEXT: vpsel q0, q1, q0
83 ; CHECK-NEXT: vmov r1, s2
84 ; CHECK-NEXT: vmov.f32 s2, s1
85 ; CHECK-NEXT: vmov r3, s0
86 ; CHECK-NEXT: vmov r2, s2
87 ; CHECK-NEXT: strd r3, r2, [r0, #16]
88 ; CHECK-NEXT: str r1, [r0, #24]
89 ; CHECK-NEXT: bx lr
90 ; CHECK-NEXT: .p2align 4
91 ; CHECK-NEXT: @ %bb.1:
92 ; CHECK-NEXT: .LCPI1_0:
93 ; CHECK-NEXT: .long 0 @ 0x0
94 ; CHECK-NEXT: .long 1 @ 0x1
95 ; CHECK-NEXT: .long 2 @ 0x2
96 ; CHECK-NEXT: .long 3 @ 0x3
97 ; CHECK-NEXT: .LCPI1_1:
98 ; CHECK-NEXT: .long 4 @ 0x4
99 ; CHECK-NEXT: .long 5 @ 0x5
100 ; CHECK-NEXT: .long 6 @ 0x6
101 ; CHECK-NEXT: .zero 4
102 %active.lane.mask = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i32(i32 %index, i32 %TC)
103 %select = select <7 x i1> %active.lane.mask, <7 x i32> %V1, <7 x i32> %V2
104 ret <7 x i32> %select
105 }
107 define <8 x i16> @v8i16(i32 %index, i32 %TC, <8 x i16> %V1, <8 x i16> %V2) {
108 ; CHECK-LABEL: v8i16:
109 ; CHECK: @ %bb.0:
110 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
111 ; CHECK-NEXT: adr.w r12, .LCPI2_0
112 ; CHECK-NEXT: vdup.32 q5, r1
113 ; CHECK-NEXT: vldrw.u32 q0, [r12]
114 ; CHECK-NEXT: vmov.i8 q1, #0x0
115 ; CHECK-NEXT: vmov.i8 q2, #0xff
116 ; CHECK-NEXT: vadd.i32 q3, q0, r0
117 ; CHECK-NEXT: vcmp.u32 hi, q5, q3
118 ; CHECK-NEXT: vpsel q4, q2, q1
119 ; CHECK-NEXT: vmov r1, r12, d8
120 ; CHECK-NEXT: vmov.16 q0[0], r1
121 ; CHECK-NEXT: vmov.16 q0[1], r12
122 ; CHECK-NEXT: vmov r1, r12, d9
123 ; CHECK-NEXT: vmov.16 q0[2], r1
124 ; CHECK-NEXT: adr r1, .LCPI2_1
125 ; CHECK-NEXT: vldrw.u32 q4, [r1]
126 ; CHECK-NEXT: vmov.16 q0[3], r12
127 ; CHECK-NEXT: vadd.i32 q4, q4, r0
128 ; CHECK-NEXT: vcmp.u32 hi, q5, q4
129 ; CHECK-NEXT: vpsel q5, q2, q1
130 ; CHECK-NEXT: vmov r1, r12, d10
131 ; CHECK-NEXT: vmov.16 q0[4], r1
132 ; CHECK-NEXT: vmov.16 q0[5], r12
133 ; CHECK-NEXT: vmov r1, r12, d11
134 ; CHECK-NEXT: vdup.32 q5, r0
135 ; CHECK-NEXT: vmov.16 q0[6], r1
136 ; CHECK-NEXT: vcmp.u32 hi, q5, q3
137 ; CHECK-NEXT: vmov.16 q0[7], r12
138 ; CHECK-NEXT: vpsel q6, q2, q1
139 ; CHECK-NEXT: vcmp.u32 hi, q5, q4
140 ; CHECK-NEXT: vmov r0, r1, d12
141 ; CHECK-NEXT: vpsel q1, q2, q1
142 ; CHECK-NEXT: vmov.16 q3[0], r0
143 ; CHECK-NEXT: vmov.16 q3[1], r1
144 ; CHECK-NEXT: vmov r0, r1, d13
145 ; CHECK-NEXT: vmov.16 q3[2], r0
146 ; CHECK-NEXT: vmov.16 q3[3], r1
147 ; CHECK-NEXT: vmov r0, r1, d2
148 ; CHECK-NEXT: vmov.16 q3[4], r0
149 ; CHECK-NEXT: vmov.16 q3[5], r1
150 ; CHECK-NEXT: vmov r0, r1, d3
151 ; CHECK-NEXT: vmov.16 q3[6], r0
152 ; CHECK-NEXT: add r0, sp, #56
153 ; CHECK-NEXT: vmov.16 q3[7], r1
154 ; CHECK-NEXT: vldrw.u32 q1, [r0]
155 ; CHECK-NEXT: vcmp.i16 ne, q3, zr
156 ; CHECK-NEXT: vpnot
157 ; CHECK-NEXT: vpst
158 ; CHECK-NEXT: vcmpt.i16 ne, q0, zr
159 ; CHECK-NEXT: vldr d1, [sp, #48]
160 ; CHECK-NEXT: vmov d0, r2, r3
161 ; CHECK-NEXT: vpsel q0, q0, q1
162 ; CHECK-NEXT: vmov r0, r1, d0
163 ; CHECK-NEXT: vmov r2, r3, d1
164 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
165 ; CHECK-NEXT: bx lr
166 ; CHECK-NEXT: .p2align 4
167 ; CHECK-NEXT: @ %bb.1:
168 ; CHECK-NEXT: .LCPI2_0:
169 ; CHECK-NEXT: .long 0 @ 0x0
170 ; CHECK-NEXT: .long 1 @ 0x1
171 ; CHECK-NEXT: .long 2 @ 0x2
172 ; CHECK-NEXT: .long 3 @ 0x3
173 ; CHECK-NEXT: .LCPI2_1:
174 ; CHECK-NEXT: .long 4 @ 0x4
175 ; CHECK-NEXT: .long 5 @ 0x5
176 ; CHECK-NEXT: .long 6 @ 0x6
177 ; CHECK-NEXT: .long 7 @ 0x7
178 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)
179 %select = select <8 x i1> %active.lane.mask, <8 x i16> %V1, <8 x i16> %V2
180 ret <8 x i16> %select
181 }
183 define <16 x i8> @v16i8(i32 %index, i32 %TC, <16 x i8> %V1, <16 x i8> %V2) {
184 ; CHECK-LABEL: v16i8:
185 ; CHECK: @ %bb.0:
186 ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
187 ; CHECK-NEXT: sub sp, #16
188 ; CHECK-NEXT: adr.w r12, .LCPI3_0
189 ; CHECK-NEXT: vdup.32 q7, r1
190 ; CHECK-NEXT: vldrw.u32 q0, [r12]
191 ; CHECK-NEXT: vmov.i8 q5, #0x0
192 ; CHECK-NEXT: vmov.i8 q4, #0xff
193 ; CHECK-NEXT: vadd.i32 q1, q0, r0
194 ; CHECK-NEXT: vcmp.u32 hi, q7, q1
195 ; CHECK-NEXT: vpsel q0, q4, q5
196 ; CHECK-NEXT: vmov r1, r12, d0
197 ; CHECK-NEXT: vmov.16 q2[0], r1
198 ; CHECK-NEXT: vmov.16 q2[1], r12
199 ; CHECK-NEXT: vmov r1, r12, d1
200 ; CHECK-NEXT: vmov.16 q2[2], r1
201 ; CHECK-NEXT: adr r1, .LCPI3_1
202 ; CHECK-NEXT: vldrw.u32 q0, [r1]
203 ; CHECK-NEXT: vmov.16 q2[3], r12
204 ; CHECK-NEXT: vadd.i32 q3, q0, r0
205 ; CHECK-NEXT: vcmp.u32 hi, q7, q3
206 ; CHECK-NEXT: vpsel q0, q4, q5
207 ; CHECK-NEXT: vmov r1, r12, d0
208 ; CHECK-NEXT: vmov.16 q2[4], r1
209 ; CHECK-NEXT: vmov.16 q2[5], r12
210 ; CHECK-NEXT: vmov r1, r12, d1
211 ; CHECK-NEXT: vmov.16 q2[6], r1
212 ; CHECK-NEXT: vmov.16 q2[7], r12
213 ; CHECK-NEXT: vcmp.i16 ne, q2, zr
214 ; CHECK-NEXT: vpsel q0, q4, q5
215 ; CHECK-NEXT: vmov.u16 r1, q0[0]
216 ; CHECK-NEXT: vmov.8 q2[0], r1
217 ; CHECK-NEXT: vmov.u16 r1, q0[1]
218 ; CHECK-NEXT: vmov.8 q2[1], r1
219 ; CHECK-NEXT: vmov.u16 r1, q0[2]
220 ; CHECK-NEXT: vmov.8 q2[2], r1
221 ; CHECK-NEXT: vmov.u16 r1, q0[3]
222 ; CHECK-NEXT: vmov.8 q2[3], r1
223 ; CHECK-NEXT: vmov.u16 r1, q0[4]
224 ; CHECK-NEXT: vmov.8 q2[4], r1
225 ; CHECK-NEXT: vmov.u16 r1, q0[5]
226 ; CHECK-NEXT: vmov.8 q2[5], r1
227 ; CHECK-NEXT: vmov.u16 r1, q0[6]
228 ; CHECK-NEXT: vmov.8 q2[6], r1
229 ; CHECK-NEXT: vmov.u16 r1, q0[7]
230 ; CHECK-NEXT: vmov.8 q2[7], r1
231 ; CHECK-NEXT: adr r1, .LCPI3_2
232 ; CHECK-NEXT: vldrw.u32 q0, [r1]
233 ; CHECK-NEXT: vadd.i32 q0, q0, r0
234 ; CHECK-NEXT: vcmp.u32 hi, q7, q0
235 ; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
236 ; CHECK-NEXT: vpsel q6, q4, q5
237 ; CHECK-NEXT: vmov r1, r12, d12
238 ; CHECK-NEXT: vmov.16 q0[0], r1
239 ; CHECK-NEXT: vmov.16 q0[1], r12
240 ; CHECK-NEXT: vmov r1, r12, d13
241 ; CHECK-NEXT: vmov.16 q0[2], r1
242 ; CHECK-NEXT: adr r1, .LCPI3_3
243 ; CHECK-NEXT: vldrw.u32 q6, [r1]
244 ; CHECK-NEXT: vmov.16 q0[3], r12
245 ; CHECK-NEXT: vadd.i32 q6, q6, r0
246 ; CHECK-NEXT: vcmp.u32 hi, q7, q6
247 ; CHECK-NEXT: vpsel q7, q4, q5
248 ; CHECK-NEXT: vmov r1, r12, d14
249 ; CHECK-NEXT: vmov.16 q0[4], r1
250 ; CHECK-NEXT: vmov.16 q0[5], r12
251 ; CHECK-NEXT: vmov r1, r12, d15
252 ; CHECK-NEXT: vmov.16 q0[6], r1
253 ; CHECK-NEXT: vdup.32 q7, r0
254 ; CHECK-NEXT: vmov.16 q0[7], r12
255 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
256 ; CHECK-NEXT: vpsel q0, q4, q5
257 ; CHECK-NEXT: vcmp.u32 hi, q7, q1
258 ; CHECK-NEXT: vmov.u16 r1, q0[0]
259 ; CHECK-NEXT: vpsel q1, q4, q5
260 ; CHECK-NEXT: vmov.8 q2[8], r1
261 ; CHECK-NEXT: vmov.u16 r1, q0[1]
262 ; CHECK-NEXT: vmov.8 q2[9], r1
263 ; CHECK-NEXT: vmov.u16 r1, q0[2]
264 ; CHECK-NEXT: vmov.8 q2[10], r1
265 ; CHECK-NEXT: vmov.u16 r1, q0[3]
266 ; CHECK-NEXT: vmov.8 q2[11], r1
267 ; CHECK-NEXT: vmov.u16 r1, q0[4]
268 ; CHECK-NEXT: vmov.8 q2[12], r1
269 ; CHECK-NEXT: vmov.u16 r1, q0[5]
270 ; CHECK-NEXT: vmov.8 q2[13], r1
271 ; CHECK-NEXT: vmov.u16 r1, q0[6]
272 ; CHECK-NEXT: vmov.8 q2[14], r1
273 ; CHECK-NEXT: vmov.u16 r1, q0[7]
274 ; CHECK-NEXT: vmov.8 q2[15], r1
275 ; CHECK-NEXT: vmov r0, r1, d2
276 ; CHECK-NEXT: vmov.16 q0[0], r0
277 ; CHECK-NEXT: vcmp.u32 hi, q7, q3
278 ; CHECK-NEXT: vmov.16 q0[1], r1
279 ; CHECK-NEXT: vmov r0, r1, d3
280 ; CHECK-NEXT: vmov.16 q0[2], r0
281 ; CHECK-NEXT: vpsel q1, q4, q5
282 ; CHECK-NEXT: vmov.16 q0[3], r1
283 ; CHECK-NEXT: vmov r0, r1, d2
284 ; CHECK-NEXT: vmov.16 q0[4], r0
285 ; CHECK-NEXT: vmov.16 q0[5], r1
286 ; CHECK-NEXT: vmov r0, r1, d3
287 ; CHECK-NEXT: vmov.16 q0[6], r0
288 ; CHECK-NEXT: vmov.16 q0[7], r1
289 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
290 ; CHECK-NEXT: vpsel q0, q4, q5
291 ; CHECK-NEXT: vmov.u16 r0, q0[0]
292 ; CHECK-NEXT: vmov.8 q3[0], r0
293 ; CHECK-NEXT: vmov.u16 r0, q0[1]
294 ; CHECK-NEXT: vmov.8 q3[1], r0
295 ; CHECK-NEXT: vmov.u16 r0, q0[2]
296 ; CHECK-NEXT: vmov.8 q3[2], r0
297 ; CHECK-NEXT: vmov.u16 r0, q0[3]
298 ; CHECK-NEXT: vmov.8 q3[3], r0
299 ; CHECK-NEXT: vmov.u16 r0, q0[4]
300 ; CHECK-NEXT: vmov.8 q3[4], r0
301 ; CHECK-NEXT: vmov.u16 r0, q0[5]
302 ; CHECK-NEXT: vmov.8 q3[5], r0
303 ; CHECK-NEXT: vmov.u16 r0, q0[6]
304 ; CHECK-NEXT: vmov.8 q3[6], r0
305 ; CHECK-NEXT: vmov.u16 r0, q0[7]
306 ; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
307 ; CHECK-NEXT: vmov.8 q3[7], r0
308 ; CHECK-NEXT: vcmp.u32 hi, q7, q0
309 ; CHECK-NEXT: vpsel q1, q4, q5
310 ; CHECK-NEXT: vcmp.u32 hi, q7, q6
311 ; CHECK-NEXT: vmov r0, r1, d2
312 ; CHECK-NEXT: vmov.16 q0[0], r0
313 ; CHECK-NEXT: vmov.16 q0[1], r1
314 ; CHECK-NEXT: vmov r0, r1, d3
315 ; CHECK-NEXT: vmov.16 q0[2], r0
316 ; CHECK-NEXT: vpsel q1, q4, q5
317 ; CHECK-NEXT: vmov.16 q0[3], r1
318 ; CHECK-NEXT: vmov r0, r1, d2
319 ; CHECK-NEXT: vmov.16 q0[4], r0
320 ; CHECK-NEXT: vmov.16 q0[5], r1
321 ; CHECK-NEXT: vmov r0, r1, d3
322 ; CHECK-NEXT: vmov.16 q0[6], r0
323 ; CHECK-NEXT: vmov.16 q0[7], r1
324 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
325 ; CHECK-NEXT: vpsel q0, q4, q5
326 ; CHECK-NEXT: vmov.u16 r0, q0[0]
327 ; CHECK-NEXT: vmov.8 q3[8], r0
328 ; CHECK-NEXT: vmov.u16 r0, q0[1]
329 ; CHECK-NEXT: vmov.8 q3[9], r0
330 ; CHECK-NEXT: vmov.u16 r0, q0[2]
331 ; CHECK-NEXT: vmov.8 q3[10], r0
332 ; CHECK-NEXT: vmov.u16 r0, q0[3]
333 ; CHECK-NEXT: vmov.8 q3[11], r0
334 ; CHECK-NEXT: vmov.u16 r0, q0[4]
335 ; CHECK-NEXT: vmov.8 q3[12], r0
336 ; CHECK-NEXT: vmov.u16 r0, q0[5]
337 ; CHECK-NEXT: vmov.8 q3[13], r0
338 ; CHECK-NEXT: vmov.u16 r0, q0[6]
339 ; CHECK-NEXT: vmov.8 q3[14], r0
340 ; CHECK-NEXT: vmov.u16 r0, q0[7]
341 ; CHECK-NEXT: vmov.8 q3[15], r0
342 ; CHECK-NEXT: add r0, sp, #88
343 ; CHECK-NEXT: vcmp.i8 ne, q3, zr
344 ; CHECK-NEXT: vldr d1, [sp, #80]
345 ; CHECK-NEXT: vldrw.u32 q1, [r0]
346 ; CHECK-NEXT: vpnot
347 ; CHECK-NEXT: vmov d0, r2, r3
348 ; CHECK-NEXT: vpst
349 ; CHECK-NEXT: vcmpt.i8 ne, q2, zr
350 ; CHECK-NEXT: vpsel q0, q0, q1
351 ; CHECK-NEXT: vmov r0, r1, d0
352 ; CHECK-NEXT: vmov r2, r3, d1
353 ; CHECK-NEXT: add sp, #16
354 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
355 ; CHECK-NEXT: bx lr
356 ; CHECK-NEXT: .p2align 4
357 ; CHECK-NEXT: @ %bb.1:
358 ; CHECK-NEXT: .LCPI3_0:
359 ; CHECK-NEXT: .long 0 @ 0x0
360 ; CHECK-NEXT: .long 1 @ 0x1
361 ; CHECK-NEXT: .long 2 @ 0x2
362 ; CHECK-NEXT: .long 3 @ 0x3
363 ; CHECK-NEXT: .LCPI3_1:
364 ; CHECK-NEXT: .long 4 @ 0x4
365 ; CHECK-NEXT: .long 5 @ 0x5
366 ; CHECK-NEXT: .long 6 @ 0x6
367 ; CHECK-NEXT: .long 7 @ 0x7
368 ; CHECK-NEXT: .LCPI3_2:
369 ; CHECK-NEXT: .long 8 @ 0x8
370 ; CHECK-NEXT: .long 9 @ 0x9
371 ; CHECK-NEXT: .long 10 @ 0xa
372 ; CHECK-NEXT: .long 11 @ 0xb
373 ; CHECK-NEXT: .LCPI3_3:
374 ; CHECK-NEXT: .long 12 @ 0xc
375 ; CHECK-NEXT: .long 13 @ 0xd
376 ; CHECK-NEXT: .long 14 @ 0xe
377 ; CHECK-NEXT: .long 15 @ 0xf
378 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)
379 %select = select <16 x i1> %active.lane.mask, <16 x i8> %V1, <16 x i8> %V2
380 ret <16 x i8> %select
381 }
383 define void @test_width2(i32* nocapture readnone %x, i32* nocapture %y, i8 zeroext %m) {
384 ; CHECK-LABEL: test_width2:
385 ; CHECK: @ %bb.0: @ %entry
386 ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
387 ; CHECK-NEXT: sub sp, #4
388 ; CHECK-NEXT: vpush {d8, d9}
389 ; CHECK-NEXT: sub sp, #8
390 ; CHECK-NEXT: cmp r2, #0
391 ; CHECK-NEXT: beq.w .LBB4_3
392 ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
393 ; CHECK-NEXT: adds r0, r2, #1
394 ; CHECK-NEXT: vmov q1[2], q1[0], r2, r2
395 ; CHECK-NEXT: bic r0, r0, #1
396 ; CHECK-NEXT: adr r2, .LCPI4_0
397 ; CHECK-NEXT: subs r0, #2
398 ; CHECK-NEXT: movs r3, #1
399 ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
400 ; CHECK-NEXT: vldrw.u32 q2, [r2]
401 ; CHECK-NEXT: add.w lr, r3, r0, lsr #1
402 ; CHECK-NEXT: mov.w r12, #0
403 ; CHECK-NEXT: vand q1, q1, q0
404 ; CHECK-NEXT: .LBB4_2: @ %vector.body
405 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
406 ; CHECK-NEXT: vmov q3[2], q3[0], r12, r12
407 ; CHECK-NEXT: vmov r6, r7, d3
408 ; CHECK-NEXT: vand q3, q3, q0
409 ; CHECK-NEXT: add.w r12, r12, #2
410 ; CHECK-NEXT: vmov r2, r3, d7
411 ; CHECK-NEXT: vmov r9, s12
412 ; CHECK-NEXT: adds r0, r2, #1
413 ; CHECK-NEXT: vmov q3[2], q3[0], r9, r0
414 ; CHECK-NEXT: adc r8, r3, #0
415 ; CHECK-NEXT: vand q3, q3, q0
416 ; CHECK-NEXT: vmov r3, r2, d2
417 ; CHECK-NEXT: vmov r4, r5, d7
418 ; CHECK-NEXT: subs r6, r4, r6
419 ; CHECK-NEXT: eor.w r0, r0, r4
420 ; CHECK-NEXT: sbcs r5, r7
421 ; CHECK-NEXT: vmov r6, r7, d6
422 ; CHECK-NEXT: mov.w r5, #0
423 ; CHECK-NEXT: it lo
424 ; CHECK-NEXT: movlo r5, #1
425 ; CHECK-NEXT: cmp r5, #0
426 ; CHECK-NEXT: csetm r5, ne
427 ; CHECK-NEXT: subs r3, r6, r3
428 ; CHECK-NEXT: sbcs.w r2, r7, r2
429 ; CHECK-NEXT: mov.w r2, #0
430 ; CHECK-NEXT: it lo
431 ; CHECK-NEXT: movlo r2, #1
432 ; CHECK-NEXT: cmp r2, #0
433 ; CHECK-NEXT: csetm r2, ne
434 ; CHECK-NEXT: orrs.w r0, r0, r8
435 ; CHECK-NEXT: cset r0, ne
436 ; CHECK-NEXT: vmov q3[2], q3[0], r2, r5
437 ; CHECK-NEXT: cmp r0, #0
438 ; CHECK-NEXT: vmov q3[3], q3[1], r2, r5
439 ; CHECK-NEXT: csetm r0, ne
440 ; CHECK-NEXT: teq.w r6, r9
441 ; CHECK-NEXT: cset r2, ne
442 ; CHECK-NEXT: cmp r2, #0
443 ; CHECK-NEXT: csetm r2, ne
444 ; CHECK-NEXT: vmov q4[2], q4[0], r2, r0
445 ; CHECK-NEXT: vmov q4[3], q4[1], r2, r0
446 ; CHECK-NEXT: veor q4, q4, q2
447 ; CHECK-NEXT: vand q4, q4, q3
448 ; CHECK-NEXT: @ implicit-def: $q3
449 ; CHECK-NEXT: vmov r2, s16
450 ; CHECK-NEXT: vmov r0, s18
451 ; CHECK-NEXT: and r2, r2, #1
452 ; CHECK-NEXT: orr.w r3, r2, r0, lsl #1
453 ; CHECK-NEXT: sub.w r2, r1, #8
454 ; CHECK-NEXT: lsls r0, r3, #31
455 ; CHECK-NEXT: itt ne
456 ; CHECK-NEXT: ldrne r0, [r2]
457 ; CHECK-NEXT: vmovne.32 q3[0], r0
458 ; CHECK-NEXT: and r0, r3, #3
459 ; CHECK-NEXT: lsls r0, r0, #30
460 ; CHECK-NEXT: itt mi
461 ; CHECK-NEXT: ldrmi r0, [r2, #4]
462 ; CHECK-NEXT: vmovmi.32 q3[2], r0
463 ; CHECK-NEXT: vmov r2, s16
464 ; CHECK-NEXT: vmov r0, s18
465 ; CHECK-NEXT: and r2, r2, #1
466 ; CHECK-NEXT: orr.w r2, r2, r0, lsl #1
467 ; CHECK-NEXT: lsls r0, r2, #31
468 ; CHECK-NEXT: itt ne
469 ; CHECK-NEXT: vmovne r0, s12
470 ; CHECK-NEXT: strne r0, [r1]
471 ; CHECK-NEXT: and r0, r2, #3
472 ; CHECK-NEXT: lsls r0, r0, #30
473 ; CHECK-NEXT: itt mi
474 ; CHECK-NEXT: vmovmi r0, s14
475 ; CHECK-NEXT: strmi r0, [r1, #4]
476 ; CHECK-NEXT: adds r1, #8
477 ; CHECK-NEXT: le lr, .LBB4_2
478 ; CHECK-NEXT: .LBB4_3: @ %for.cond.cleanup
479 ; CHECK-NEXT: add sp, #8
480 ; CHECK-NEXT: vpop {d8, d9}
481 ; CHECK-NEXT: add sp, #4
482 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
483 ; CHECK-NEXT: .p2align 4
484 ; CHECK-NEXT: @ %bb.4:
485 ; CHECK-NEXT: .LCPI4_0:
486 ; CHECK-NEXT: .long 1 @ 0x1
487 ; CHECK-NEXT: .long 0 @ 0x0
488 ; CHECK-NEXT: .long 1 @ 0x1
489 ; CHECK-NEXT: .long 0 @ 0x0
490 entry:
491 %cmp9.not = icmp eq i8 %m, 0
492 br i1 %cmp9.not, label %for.cond.cleanup, label %for.body.preheader
494 for.body.preheader: ; preds = %entry
495 %wide.trip.count = zext i8 %m to i32
496 %n.rnd.up = add nuw nsw i32 %wide.trip.count, 1
497 %n.vec = and i32 %n.rnd.up, 510
498 br label %vector.body
500 vector.body: ; preds = %vector.body, %for.body.preheader
501 %index = phi i32 [ 0, %for.body.preheader ], [ %index.next, %vector.body ]
502 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %wide.trip.count)
503 %0 = add nsw i32 %index, -2
504 %1 = getelementptr inbounds i32, i32* %y, i32 %0
505 %2 = bitcast i32* %1 to <2 x i32>*
506 %wide.masked.load = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %2, i32 4, <2 x i1> %active.lane.mask, <2 x i32> undef)
507 %3 = getelementptr inbounds i32, i32* %y, i32 %index
508 %4 = bitcast i32* %3 to <2 x i32>*
509 call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %wide.masked.load, <2 x i32>* %4, i32 4, <2 x i1> %active.lane.mask)
510 %index.next = add i32 %index, 2
511 %5 = icmp eq i32 %index.next, %n.vec
512 br i1 %5, label %for.cond.cleanup, label %vector.body
514 for.cond.cleanup: ; preds = %vector.body, %entry
515 ret void
516 }
518 declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32)
519 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
520 declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i32(i32, i32)
521 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
522 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
523 declare <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)
524 declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)