| blob | 8c30520d02cd4a94a2bc96eb54e8db32ee649646 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE
3 ; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE
5 define arm_aapcs_vfpcc void @masked_v4i32(<4 x i32> *%dest, <4 x i32> %a) {
6 ; CHECK-LE-LABEL: masked_v4i32:
7 ; CHECK-LE: @ %bb.0: @ %entry
8 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
9 ; CHECK-LE-NEXT: vstrwt.32 q0, [r0]
10 ; CHECK-LE-NEXT: bx lr
11 ;
12 ; CHECK-BE-LABEL: masked_v4i32:
13 ; CHECK-BE: @ %bb.0: @ %entry
14 ; CHECK-BE-NEXT: vrev64.32 q1, q0
15 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
16 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0]
17 ; CHECK-BE-NEXT: bx lr
18 entry:
19 %c = icmp sgt <4 x i32> %a, zeroinitializer
20 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a, <4 x i32>* %dest, i32 4, <4 x i1> %c)
21 ret void
22 }
24 define arm_aapcs_vfpcc void @masked_v4i32_align1(<4 x i32> *%dest, <4 x i32> %a) {
25 ; CHECK-LE-LABEL: masked_v4i32_align1:
26 ; CHECK-LE: @ %bb.0: @ %entry
27 ; CHECK-LE-NEXT: .pad #4
28 ; CHECK-LE-NEXT: sub sp, #4
29 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
30 ; CHECK-LE-NEXT: vmrs r2, p0
31 ; CHECK-LE-NEXT: and r1, r2, #1
32 ; CHECK-LE-NEXT: rsbs r3, r1, #0
33 ; CHECK-LE-NEXT: movs r1, #0
34 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
35 ; CHECK-LE-NEXT: ubfx r3, r2, #4, #1
36 ; CHECK-LE-NEXT: rsbs r3, r3, #0
37 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
38 ; CHECK-LE-NEXT: ubfx r3, r2, #8, #1
39 ; CHECK-LE-NEXT: ubfx r2, r2, #12, #1
40 ; CHECK-LE-NEXT: rsbs r3, r3, #0
41 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
42 ; CHECK-LE-NEXT: rsbs r2, r2, #0
43 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
44 ; CHECK-LE-NEXT: lsls r2, r1, #31
45 ; CHECK-LE-NEXT: itt ne
46 ; CHECK-LE-NEXT: vmovne r2, s0
47 ; CHECK-LE-NEXT: strne r2, [r0]
48 ; CHECK-LE-NEXT: lsls r2, r1, #30
49 ; CHECK-LE-NEXT: itt mi
50 ; CHECK-LE-NEXT: vmovmi r2, s1
51 ; CHECK-LE-NEXT: strmi r2, [r0, #4]
52 ; CHECK-LE-NEXT: lsls r2, r1, #29
53 ; CHECK-LE-NEXT: itt mi
54 ; CHECK-LE-NEXT: vmovmi r2, s2
55 ; CHECK-LE-NEXT: strmi r2, [r0, #8]
56 ; CHECK-LE-NEXT: lsls r1, r1, #28
57 ; CHECK-LE-NEXT: itt mi
58 ; CHECK-LE-NEXT: vmovmi r1, s3
59 ; CHECK-LE-NEXT: strmi r1, [r0, #12]
60 ; CHECK-LE-NEXT: add sp, #4
61 ; CHECK-LE-NEXT: bx lr
62 ;
63 ; CHECK-BE-LABEL: masked_v4i32_align1:
64 ; CHECK-BE: @ %bb.0: @ %entry
65 ; CHECK-BE-NEXT: .pad #4
66 ; CHECK-BE-NEXT: sub sp, #4
67 ; CHECK-BE-NEXT: vrev64.32 q1, q0
68 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
69 ; CHECK-BE-NEXT: vmrs r2, p0
70 ; CHECK-BE-NEXT: ubfx r1, r2, #12, #1
71 ; CHECK-BE-NEXT: rsbs r3, r1, #0
72 ; CHECK-BE-NEXT: movs r1, #0
73 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
74 ; CHECK-BE-NEXT: ubfx r3, r2, #8, #1
75 ; CHECK-BE-NEXT: rsbs r3, r3, #0
76 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
77 ; CHECK-BE-NEXT: ubfx r3, r2, #4, #1
78 ; CHECK-BE-NEXT: and r2, r2, #1
79 ; CHECK-BE-NEXT: rsbs r3, r3, #0
80 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
81 ; CHECK-BE-NEXT: rsbs r2, r2, #0
82 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
83 ; CHECK-BE-NEXT: lsls r2, r1, #28
84 ; CHECK-BE-NEXT: itt mi
85 ; CHECK-BE-NEXT: vmovmi r2, s4
86 ; CHECK-BE-NEXT: strmi r2, [r0]
87 ; CHECK-BE-NEXT: lsls r2, r1, #29
88 ; CHECK-BE-NEXT: itt mi
89 ; CHECK-BE-NEXT: vmovmi r2, s5
90 ; CHECK-BE-NEXT: strmi r2, [r0, #4]
91 ; CHECK-BE-NEXT: lsls r2, r1, #30
92 ; CHECK-BE-NEXT: itt mi
93 ; CHECK-BE-NEXT: vmovmi r2, s6
94 ; CHECK-BE-NEXT: strmi r2, [r0, #8]
95 ; CHECK-BE-NEXT: lsls r1, r1, #31
96 ; CHECK-BE-NEXT: itt ne
97 ; CHECK-BE-NEXT: vmovne r1, s7
98 ; CHECK-BE-NEXT: strne r1, [r0, #12]
99 ; CHECK-BE-NEXT: add sp, #4
100 ; CHECK-BE-NEXT: bx lr
101 entry:
102 %c = icmp sgt <4 x i32> %a, zeroinitializer
103 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a, <4 x i32>* %dest, i32 1, <4 x i1> %c)
104 ret void
105 }
107 define i8* @masked_v4i32_pre(i8* %y, i8* %x, <4 x i32> %a) {
108 ; CHECK-LE-LABEL: masked_v4i32_pre:
109 ; CHECK-LE: @ %bb.0: @ %entry
110 ; CHECK-LE-NEXT: vldr d1, [sp]
111 ; CHECK-LE-NEXT: vmov d0, r2, r3
112 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
113 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
114 ; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]!
115 ; CHECK-LE-NEXT: bx lr
116 ;
117 ; CHECK-BE-LABEL: masked_v4i32_pre:
118 ; CHECK-BE: @ %bb.0: @ %entry
119 ; CHECK-BE-NEXT: vldr d1, [sp]
120 ; CHECK-BE-NEXT: vmov d0, r3, r2
121 ; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
122 ; CHECK-BE-NEXT: vrev64.32 q2, q0
123 ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
124 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]!
125 ; CHECK-BE-NEXT: bx lr
126 entry:
127 %z = getelementptr inbounds i8, i8* %y, i32 4
128 %0 = bitcast i8* %x to <4 x i32>*
129 %1 = load <4 x i32>, <4 x i32>* %0, align 4
130 %2 = bitcast i8* %z to <4 x i32>*
131 %c = icmp sgt <4 x i32> %a, zeroinitializer
132 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %1, <4 x i32>* %2, i32 4, <4 x i1> %c)
133 ret i8* %z
134 }
136 define i8* @masked_v4i32_post(i8* %y, i8* %x, <4 x i32> %a) {
137 ; CHECK-LE-LABEL: masked_v4i32_post:
138 ; CHECK-LE: @ %bb.0: @ %entry
139 ; CHECK-LE-NEXT: vldr d1, [sp]
140 ; CHECK-LE-NEXT: vmov d0, r2, r3
141 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
142 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
143 ; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4
144 ; CHECK-LE-NEXT: bx lr
145 ;
146 ; CHECK-BE-LABEL: masked_v4i32_post:
147 ; CHECK-BE: @ %bb.0: @ %entry
148 ; CHECK-BE-NEXT: vldr d1, [sp]
149 ; CHECK-BE-NEXT: vmov d0, r3, r2
150 ; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
151 ; CHECK-BE-NEXT: vrev64.32 q2, q0
152 ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
153 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4
154 ; CHECK-BE-NEXT: bx lr
155 entry:
156 %z = getelementptr inbounds i8, i8* %y, i32 4
157 %0 = bitcast i8* %x to <4 x i32>*
158 %1 = load <4 x i32>, <4 x i32>* %0, align 4
159 %2 = bitcast i8* %y to <4 x i32>*
160 %c = icmp sgt <4 x i32> %a, zeroinitializer
161 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %1, <4 x i32>* %2, i32 4, <4 x i1> %c)
162 ret i8* %z
163 }
166 define arm_aapcs_vfpcc void @masked_v8i16(<8 x i16> *%dest, <8 x i16> %a) {
167 ; CHECK-LE-LABEL: masked_v8i16:
168 ; CHECK-LE: @ %bb.0: @ %entry
169 ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
170 ; CHECK-LE-NEXT: vstrht.16 q0, [r0]
171 ; CHECK-LE-NEXT: bx lr
172 ;
173 ; CHECK-BE-LABEL: masked_v8i16:
174 ; CHECK-BE: @ %bb.0: @ %entry
175 ; CHECK-BE-NEXT: vrev64.16 q1, q0
176 ; CHECK-BE-NEXT: vpt.s16 gt, q1, zr
177 ; CHECK-BE-NEXT: vstrht.16 q1, [r0]
178 ; CHECK-BE-NEXT: bx lr
179 entry:
180 %c = icmp sgt <8 x i16> %a, zeroinitializer
181 call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %a, <8 x i16>* %dest, i32 2, <8 x i1> %c)
182 ret void
183 }
185 define arm_aapcs_vfpcc void @masked_v8i16_align1(<8 x i16> *%dest, <8 x i16> %a) {
186 ; CHECK-LE-LABEL: masked_v8i16_align1:
187 ; CHECK-LE: @ %bb.0: @ %entry
188 ; CHECK-LE-NEXT: .pad #4
189 ; CHECK-LE-NEXT: sub sp, #4
190 ; CHECK-LE-NEXT: vcmp.s16 gt, q0, zr
191 ; CHECK-LE-NEXT: vmrs r1, p0
192 ; CHECK-LE-NEXT: and r2, r1, #1
193 ; CHECK-LE-NEXT: rsbs r3, r2, #0
194 ; CHECK-LE-NEXT: movs r2, #0
195 ; CHECK-LE-NEXT: bfi r2, r3, #0, #1
196 ; CHECK-LE-NEXT: ubfx r3, r1, #2, #1
197 ; CHECK-LE-NEXT: rsbs r3, r3, #0
198 ; CHECK-LE-NEXT: bfi r2, r3, #1, #1
199 ; CHECK-LE-NEXT: ubfx r3, r1, #4, #1
200 ; CHECK-LE-NEXT: rsbs r3, r3, #0
201 ; CHECK-LE-NEXT: bfi r2, r3, #2, #1
202 ; CHECK-LE-NEXT: ubfx r3, r1, #6, #1
203 ; CHECK-LE-NEXT: rsbs r3, r3, #0
204 ; CHECK-LE-NEXT: bfi r2, r3, #3, #1
205 ; CHECK-LE-NEXT: ubfx r3, r1, #8, #1
206 ; CHECK-LE-NEXT: rsbs r3, r3, #0
207 ; CHECK-LE-NEXT: bfi r2, r3, #4, #1
208 ; CHECK-LE-NEXT: ubfx r3, r1, #10, #1
209 ; CHECK-LE-NEXT: rsbs r3, r3, #0
210 ; CHECK-LE-NEXT: bfi r2, r3, #5, #1
211 ; CHECK-LE-NEXT: ubfx r3, r1, #12, #1
212 ; CHECK-LE-NEXT: ubfx r1, r1, #14, #1
213 ; CHECK-LE-NEXT: rsbs r3, r3, #0
214 ; CHECK-LE-NEXT: bfi r2, r3, #6, #1
215 ; CHECK-LE-NEXT: rsbs r1, r1, #0
216 ; CHECK-LE-NEXT: bfi r2, r1, #7, #1
217 ; CHECK-LE-NEXT: uxtb r1, r2
218 ; CHECK-LE-NEXT: lsls r2, r2, #31
219 ; CHECK-LE-NEXT: itt ne
220 ; CHECK-LE-NEXT: vmovne.u16 r2, q0[0]
221 ; CHECK-LE-NEXT: strhne r2, [r0]
222 ; CHECK-LE-NEXT: lsls r2, r1, #30
223 ; CHECK-LE-NEXT: itt mi
224 ; CHECK-LE-NEXT: vmovmi.u16 r2, q0[1]
225 ; CHECK-LE-NEXT: strhmi r2, [r0, #2]
226 ; CHECK-LE-NEXT: lsls r2, r1, #29
227 ; CHECK-LE-NEXT: itt mi
228 ; CHECK-LE-NEXT: vmovmi.u16 r2, q0[2]
229 ; CHECK-LE-NEXT: strhmi r2, [r0, #4]
230 ; CHECK-LE-NEXT: lsls r2, r1, #28
231 ; CHECK-LE-NEXT: itt mi
232 ; CHECK-LE-NEXT: vmovmi.u16 r2, q0[3]
233 ; CHECK-LE-NEXT: strhmi r2, [r0, #6]
234 ; CHECK-LE-NEXT: lsls r2, r1, #27
235 ; CHECK-LE-NEXT: itt mi
236 ; CHECK-LE-NEXT: vmovmi.u16 r2, q0[4]
237 ; CHECK-LE-NEXT: strhmi r2, [r0, #8]
238 ; CHECK-LE-NEXT: lsls r2, r1, #26
239 ; CHECK-LE-NEXT: itt mi
240 ; CHECK-LE-NEXT: vmovmi.u16 r2, q0[5]
241 ; CHECK-LE-NEXT: strhmi r2, [r0, #10]
242 ; CHECK-LE-NEXT: lsls r2, r1, #25
243 ; CHECK-LE-NEXT: itt mi
244 ; CHECK-LE-NEXT: vmovmi.u16 r2, q0[6]
245 ; CHECK-LE-NEXT: strhmi r2, [r0, #12]
246 ; CHECK-LE-NEXT: lsls r1, r1, #24
247 ; CHECK-LE-NEXT: itt mi
248 ; CHECK-LE-NEXT: vmovmi.u16 r1, q0[7]
249 ; CHECK-LE-NEXT: strhmi r1, [r0, #14]
250 ; CHECK-LE-NEXT: add sp, #4
251 ; CHECK-LE-NEXT: bx lr
252 ;
253 ; CHECK-BE-LABEL: masked_v8i16_align1:
254 ; CHECK-BE: @ %bb.0: @ %entry
255 ; CHECK-BE-NEXT: .pad #4
256 ; CHECK-BE-NEXT: sub sp, #4
257 ; CHECK-BE-NEXT: vrev64.16 q1, q0
258 ; CHECK-BE-NEXT: vcmp.s16 gt, q1, zr
259 ; CHECK-BE-NEXT: vmrs r1, p0
260 ; CHECK-BE-NEXT: ubfx r2, r1, #14, #1
261 ; CHECK-BE-NEXT: rsbs r3, r2, #0
262 ; CHECK-BE-NEXT: movs r2, #0
263 ; CHECK-BE-NEXT: bfi r2, r3, #0, #1
264 ; CHECK-BE-NEXT: ubfx r3, r1, #12, #1
265 ; CHECK-BE-NEXT: rsbs r3, r3, #0
266 ; CHECK-BE-NEXT: bfi r2, r3, #1, #1
267 ; CHECK-BE-NEXT: ubfx r3, r1, #10, #1
268 ; CHECK-BE-NEXT: rsbs r3, r3, #0
269 ; CHECK-BE-NEXT: bfi r2, r3, #2, #1
270 ; CHECK-BE-NEXT: ubfx r3, r1, #8, #1
271 ; CHECK-BE-NEXT: rsbs r3, r3, #0
272 ; CHECK-BE-NEXT: bfi r2, r3, #3, #1
273 ; CHECK-BE-NEXT: ubfx r3, r1, #6, #1
274 ; CHECK-BE-NEXT: rsbs r3, r3, #0
275 ; CHECK-BE-NEXT: bfi r2, r3, #4, #1
276 ; CHECK-BE-NEXT: ubfx r3, r1, #4, #1
277 ; CHECK-BE-NEXT: rsbs r3, r3, #0
278 ; CHECK-BE-NEXT: bfi r2, r3, #5, #1
279 ; CHECK-BE-NEXT: ubfx r3, r1, #2, #1
280 ; CHECK-BE-NEXT: and r1, r1, #1
281 ; CHECK-BE-NEXT: rsbs r3, r3, #0
282 ; CHECK-BE-NEXT: bfi r2, r3, #6, #1
283 ; CHECK-BE-NEXT: rsbs r1, r1, #0
284 ; CHECK-BE-NEXT: bfi r2, r1, #7, #1
285 ; CHECK-BE-NEXT: uxtb r1, r2
286 ; CHECK-BE-NEXT: lsls r2, r2, #24
287 ; CHECK-BE-NEXT: itt mi
288 ; CHECK-BE-NEXT: vmovmi.u16 r2, q1[0]
289 ; CHECK-BE-NEXT: strhmi r2, [r0]
290 ; CHECK-BE-NEXT: lsls r2, r1, #25
291 ; CHECK-BE-NEXT: itt mi
292 ; CHECK-BE-NEXT: vmovmi.u16 r2, q1[1]
293 ; CHECK-BE-NEXT: strhmi r2, [r0, #2]
294 ; CHECK-BE-NEXT: lsls r2, r1, #26
295 ; CHECK-BE-NEXT: itt mi
296 ; CHECK-BE-NEXT: vmovmi.u16 r2, q1[2]
297 ; CHECK-BE-NEXT: strhmi r2, [r0, #4]
298 ; CHECK-BE-NEXT: lsls r2, r1, #27
299 ; CHECK-BE-NEXT: itt mi
300 ; CHECK-BE-NEXT: vmovmi.u16 r2, q1[3]
301 ; CHECK-BE-NEXT: strhmi r2, [r0, #6]
302 ; CHECK-BE-NEXT: lsls r2, r1, #28
303 ; CHECK-BE-NEXT: itt mi
304 ; CHECK-BE-NEXT: vmovmi.u16 r2, q1[4]
305 ; CHECK-BE-NEXT: strhmi r2, [r0, #8]
306 ; CHECK-BE-NEXT: lsls r2, r1, #29
307 ; CHECK-BE-NEXT: itt mi
308 ; CHECK-BE-NEXT: vmovmi.u16 r2, q1[5]
309 ; CHECK-BE-NEXT: strhmi r2, [r0, #10]
310 ; CHECK-BE-NEXT: lsls r2, r1, #30
311 ; CHECK-BE-NEXT: itt mi
312 ; CHECK-BE-NEXT: vmovmi.u16 r2, q1[6]
313 ; CHECK-BE-NEXT: strhmi r2, [r0, #12]
314 ; CHECK-BE-NEXT: lsls r1, r1, #31
315 ; CHECK-BE-NEXT: itt ne
316 ; CHECK-BE-NEXT: vmovne.u16 r1, q1[7]
317 ; CHECK-BE-NEXT: strhne r1, [r0, #14]
318 ; CHECK-BE-NEXT: add sp, #4
319 ; CHECK-BE-NEXT: bx lr
320 entry:
321 %c = icmp sgt <8 x i16> %a, zeroinitializer
322 call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %a, <8 x i16>* %dest, i32 1, <8 x i1> %c)
323 ret void
324 }
326 define i8* @masked_v8i16_pre(i8* %y, i8* %x, <8 x i16> %a) {
327 ; CHECK-LE-LABEL: masked_v8i16_pre:
328 ; CHECK-LE: @ %bb.0: @ %entry
329 ; CHECK-LE-NEXT: vldr d1, [sp]
330 ; CHECK-LE-NEXT: vmov d0, r2, r3
331 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
332 ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
333 ; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]!
334 ; CHECK-LE-NEXT: bx lr
335 ;
336 ; CHECK-BE-LABEL: masked_v8i16_pre:
337 ; CHECK-BE: @ %bb.0: @ %entry
338 ; CHECK-BE-NEXT: vldr d1, [sp]
339 ; CHECK-BE-NEXT: vmov d0, r3, r2
340 ; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
341 ; CHECK-BE-NEXT: vrev64.16 q2, q0
342 ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
343 ; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]!
344 ; CHECK-BE-NEXT: bx lr
345 entry:
346 %z = getelementptr inbounds i8, i8* %y, i32 4
347 %0 = bitcast i8* %x to <8 x i16>*
348 %1 = load <8 x i16>, <8 x i16>* %0, align 4
349 %2 = bitcast i8* %z to <8 x i16>*
350 %c = icmp sgt <8 x i16> %a, zeroinitializer
351 call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %1, <8 x i16>* %2, i32 2, <8 x i1> %c)
352 ret i8* %z
353 }
355 define i8* @masked_v8i16_post(i8* %y, i8* %x, <8 x i16> %a) {
356 ; CHECK-LE-LABEL: masked_v8i16_post:
357 ; CHECK-LE: @ %bb.0: @ %entry
358 ; CHECK-LE-NEXT: vldr d1, [sp]
359 ; CHECK-LE-NEXT: vmov d0, r2, r3
360 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
361 ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
362 ; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4
363 ; CHECK-LE-NEXT: bx lr
364 ;
365 ; CHECK-BE-LABEL: masked_v8i16_post:
366 ; CHECK-BE: @ %bb.0: @ %entry
367 ; CHECK-BE-NEXT: vldr d1, [sp]
368 ; CHECK-BE-NEXT: vmov d0, r3, r2
369 ; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
370 ; CHECK-BE-NEXT: vrev64.16 q2, q0
371 ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
372 ; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4
373 ; CHECK-BE-NEXT: bx lr
374 entry:
375 %z = getelementptr inbounds i8, i8* %y, i32 4
376 %0 = bitcast i8* %x to <8 x i16>*
377 %1 = load <8 x i16>, <8 x i16>* %0, align 4
378 %2 = bitcast i8* %y to <8 x i16>*
379 %c = icmp sgt <8 x i16> %a, zeroinitializer
380 call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %1, <8 x i16>* %2, i32 2, <8 x i1> %c)
381 ret i8* %z
382 }
385 define arm_aapcs_vfpcc void @masked_v16i8(<16 x i8> *%dest, <16 x i8> %a) {
386 ; CHECK-LE-LABEL: masked_v16i8:
387 ; CHECK-LE: @ %bb.0: @ %entry
388 ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr
389 ; CHECK-LE-NEXT: vstrbt.8 q0, [r0]
390 ; CHECK-LE-NEXT: bx lr
391 ;
392 ; CHECK-BE-LABEL: masked_v16i8:
393 ; CHECK-BE: @ %bb.0: @ %entry
394 ; CHECK-BE-NEXT: vrev64.8 q1, q0
395 ; CHECK-BE-NEXT: vpt.s8 gt, q1, zr
396 ; CHECK-BE-NEXT: vstrbt.8 q1, [r0]
397 ; CHECK-BE-NEXT: bx lr
398 entry:
399 %c = icmp sgt <16 x i8> %a, zeroinitializer
400 call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %a, <16 x i8>* %dest, i32 1, <16 x i1> %c)
401 ret void
402 }
404 define i8* @masked_v16i8_pre(i8* %y, i8* %x, <16 x i8> %a) {
405 ; CHECK-LE-LABEL: masked_v16i8_pre:
406 ; CHECK-LE: @ %bb.0: @ %entry
407 ; CHECK-LE-NEXT: vldr d1, [sp]
408 ; CHECK-LE-NEXT: vmov d0, r2, r3
409 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
410 ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr
411 ; CHECK-LE-NEXT: vstrbt.8 q1, [r0, #4]!
412 ; CHECK-LE-NEXT: bx lr
413 ;
414 ; CHECK-BE-LABEL: masked_v16i8_pre:
415 ; CHECK-BE: @ %bb.0: @ %entry
416 ; CHECK-BE-NEXT: vldr d1, [sp]
417 ; CHECK-BE-NEXT: vmov d0, r3, r2
418 ; CHECK-BE-NEXT: vldrb.u8 q1, [r1]
419 ; CHECK-BE-NEXT: vrev64.8 q2, q0
420 ; CHECK-BE-NEXT: vpt.s8 gt, q2, zr
421 ; CHECK-BE-NEXT: vstrbt.8 q1, [r0, #4]!
422 ; CHECK-BE-NEXT: bx lr
423 entry:
424 %z = getelementptr inbounds i8, i8* %y, i32 4
425 %0 = bitcast i8* %x to <16 x i8>*
426 %1 = load <16 x i8>, <16 x i8>* %0, align 4
427 %2 = bitcast i8* %z to <16 x i8>*
428 %c = icmp sgt <16 x i8> %a, zeroinitializer
429 call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %1, <16 x i8>* %2, i32 1, <16 x i1> %c)
430 ret i8* %z
431 }
433 define i8* @masked_v16i8_post(i8* %y, i8* %x, <16 x i8> %a) {
434 ; CHECK-LE-LABEL: masked_v16i8_post:
435 ; CHECK-LE: @ %bb.0: @ %entry
436 ; CHECK-LE-NEXT: vldr d1, [sp]
437 ; CHECK-LE-NEXT: vmov d0, r2, r3
438 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
439 ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr
440 ; CHECK-LE-NEXT: vstrbt.8 q1, [r0], #4
441 ; CHECK-LE-NEXT: bx lr
442 ;
443 ; CHECK-BE-LABEL: masked_v16i8_post:
444 ; CHECK-BE: @ %bb.0: @ %entry
445 ; CHECK-BE-NEXT: vldr d1, [sp]
446 ; CHECK-BE-NEXT: vmov d0, r3, r2
447 ; CHECK-BE-NEXT: vldrb.u8 q1, [r1]
448 ; CHECK-BE-NEXT: vrev64.8 q2, q0
449 ; CHECK-BE-NEXT: vpt.s8 gt, q2, zr
450 ; CHECK-BE-NEXT: vstrbt.8 q1, [r0], #4
451 ; CHECK-BE-NEXT: bx lr
452 entry:
453 %z = getelementptr inbounds i8, i8* %y, i32 4
454 %0 = bitcast i8* %x to <16 x i8>*
455 %1 = load <16 x i8>, <16 x i8>* %0, align 4
456 %2 = bitcast i8* %y to <16 x i8>*
457 %c = icmp sgt <16 x i8> %a, zeroinitializer
458 call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %1, <16 x i8>* %2, i32 1, <16 x i1> %c)
459 ret i8* %z
460 }
463 define arm_aapcs_vfpcc void @masked_v4f32(<4 x float> *%dest, <4 x float> %a, <4 x i32> %b) {
464 ; CHECK-LE-LABEL: masked_v4f32:
465 ; CHECK-LE: @ %bb.0: @ %entry
466 ; CHECK-LE-NEXT: vpt.i32 ne, q1, zr
467 ; CHECK-LE-NEXT: vstrwt.32 q0, [r0]
468 ; CHECK-LE-NEXT: bx lr
469 ;
470 ; CHECK-BE-LABEL: masked_v4f32:
471 ; CHECK-BE: @ %bb.0: @ %entry
472 ; CHECK-BE-NEXT: vrev64.32 q2, q1
473 ; CHECK-BE-NEXT: vrev64.32 q1, q0
474 ; CHECK-BE-NEXT: vpt.i32 ne, q2, zr
475 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0]
476 ; CHECK-BE-NEXT: bx lr
477 entry:
478 %c = icmp ugt <4 x i32> %b, zeroinitializer
479 call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %a, <4 x float>* %dest, i32 4, <4 x i1> %c)
480 ret void
481 }
483 define arm_aapcs_vfpcc void @masked_v4f32_align1(<4 x float> *%dest, <4 x float> %a, <4 x i32> %b) {
484 ; CHECK-LE-LABEL: masked_v4f32_align1:
485 ; CHECK-LE: @ %bb.0: @ %entry
486 ; CHECK-LE-NEXT: .pad #4
487 ; CHECK-LE-NEXT: sub sp, #4
488 ; CHECK-LE-NEXT: vcmp.i32 ne, q1, zr
489 ; CHECK-LE-NEXT: movs r1, #0
490 ; CHECK-LE-NEXT: vmrs r2, p0
491 ; CHECK-LE-NEXT: and r3, r2, #1
492 ; CHECK-LE-NEXT: rsbs r3, r3, #0
493 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
494 ; CHECK-LE-NEXT: ubfx r3, r2, #4, #1
495 ; CHECK-LE-NEXT: rsbs r3, r3, #0
496 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
497 ; CHECK-LE-NEXT: ubfx r3, r2, #8, #1
498 ; CHECK-LE-NEXT: ubfx r2, r2, #12, #1
499 ; CHECK-LE-NEXT: rsbs r3, r3, #0
500 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
501 ; CHECK-LE-NEXT: rsbs r2, r2, #0
502 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
503 ; CHECK-LE-NEXT: lsls r2, r1, #31
504 ; CHECK-LE-NEXT: itt ne
505 ; CHECK-LE-NEXT: vmovne r2, s0
506 ; CHECK-LE-NEXT: strne r2, [r0]
507 ; CHECK-LE-NEXT: lsls r2, r1, #30
508 ; CHECK-LE-NEXT: itt mi
509 ; CHECK-LE-NEXT: vmovmi r2, s1
510 ; CHECK-LE-NEXT: strmi r2, [r0, #4]
511 ; CHECK-LE-NEXT: lsls r2, r1, #29
512 ; CHECK-LE-NEXT: itt mi
513 ; CHECK-LE-NEXT: vmovmi r2, s2
514 ; CHECK-LE-NEXT: strmi r2, [r0, #8]
515 ; CHECK-LE-NEXT: lsls r1, r1, #28
516 ; CHECK-LE-NEXT: itt mi
517 ; CHECK-LE-NEXT: vmovmi r1, s3
518 ; CHECK-LE-NEXT: strmi r1, [r0, #12]
519 ; CHECK-LE-NEXT: add sp, #4
520 ; CHECK-LE-NEXT: bx lr
521 ;
522 ; CHECK-BE-LABEL: masked_v4f32_align1:
523 ; CHECK-BE: @ %bb.0: @ %entry
524 ; CHECK-BE-NEXT: .pad #4
525 ; CHECK-BE-NEXT: sub sp, #4
526 ; CHECK-BE-NEXT: vrev64.32 q2, q1
527 ; CHECK-BE-NEXT: movs r1, #0
528 ; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr
529 ; CHECK-BE-NEXT: vrev64.32 q1, q0
530 ; CHECK-BE-NEXT: vmrs r2, p0
531 ; CHECK-BE-NEXT: ubfx r3, r2, #12, #1
532 ; CHECK-BE-NEXT: rsbs r3, r3, #0
533 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
534 ; CHECK-BE-NEXT: ubfx r3, r2, #8, #1
535 ; CHECK-BE-NEXT: rsbs r3, r3, #0
536 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
537 ; CHECK-BE-NEXT: ubfx r3, r2, #4, #1
538 ; CHECK-BE-NEXT: and r2, r2, #1
539 ; CHECK-BE-NEXT: rsbs r3, r3, #0
540 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
541 ; CHECK-BE-NEXT: rsbs r2, r2, #0
542 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
543 ; CHECK-BE-NEXT: lsls r2, r1, #28
544 ; CHECK-BE-NEXT: itt mi
545 ; CHECK-BE-NEXT: vmovmi r2, s4
546 ; CHECK-BE-NEXT: strmi r2, [r0]
547 ; CHECK-BE-NEXT: lsls r2, r1, #29
548 ; CHECK-BE-NEXT: itt mi
549 ; CHECK-BE-NEXT: vmovmi r2, s5
550 ; CHECK-BE-NEXT: strmi r2, [r0, #4]
551 ; CHECK-BE-NEXT: lsls r2, r1, #30
552 ; CHECK-BE-NEXT: itt mi
553 ; CHECK-BE-NEXT: vmovmi r2, s6
554 ; CHECK-BE-NEXT: strmi r2, [r0, #8]
555 ; CHECK-BE-NEXT: lsls r1, r1, #31
556 ; CHECK-BE-NEXT: itt ne
557 ; CHECK-BE-NEXT: vmovne r1, s7
558 ; CHECK-BE-NEXT: strne r1, [r0, #12]
559 ; CHECK-BE-NEXT: add sp, #4
560 ; CHECK-BE-NEXT: bx lr
561 entry:
562 %c = icmp ugt <4 x i32> %b, zeroinitializer
563 call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %a, <4 x float>* %dest, i32 1, <4 x i1> %c)
564 ret void
565 }
567 define i8* @masked_v4f32_pre(i8* %y, i8* %x, <4 x i32> %a) {
568 ; CHECK-LE-LABEL: masked_v4f32_pre:
569 ; CHECK-LE: @ %bb.0: @ %entry
570 ; CHECK-LE-NEXT: vldr d1, [sp]
571 ; CHECK-LE-NEXT: vmov d0, r2, r3
572 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
573 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
574 ; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]!
575 ; CHECK-LE-NEXT: bx lr
576 ;
577 ; CHECK-BE-LABEL: masked_v4f32_pre:
578 ; CHECK-BE: @ %bb.0: @ %entry
579 ; CHECK-BE-NEXT: vldr d1, [sp]
580 ; CHECK-BE-NEXT: vmov d0, r3, r2
581 ; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
582 ; CHECK-BE-NEXT: vrev64.32 q2, q0
583 ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
584 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]!
585 ; CHECK-BE-NEXT: bx lr
586 entry:
587 %z = getelementptr inbounds i8, i8* %y, i32 4
588 %0 = bitcast i8* %x to <4 x float>*
589 %1 = load <4 x float>, <4 x float>* %0, align 4
590 %2 = bitcast i8* %z to <4 x float>*
591 %c = icmp sgt <4 x i32> %a, zeroinitializer
592 call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %c)
593 ret i8* %z
594 }
596 define i8* @masked_v4f32_post(i8* %y, i8* %x, <4 x i32> %a) {
597 ; CHECK-LE-LABEL: masked_v4f32_post:
598 ; CHECK-LE: @ %bb.0: @ %entry
599 ; CHECK-LE-NEXT: vldr d1, [sp]
600 ; CHECK-LE-NEXT: vmov d0, r2, r3
601 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
602 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
603 ; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4
604 ; CHECK-LE-NEXT: bx lr
605 ;
606 ; CHECK-BE-LABEL: masked_v4f32_post:
607 ; CHECK-BE: @ %bb.0: @ %entry
608 ; CHECK-BE-NEXT: vldr d1, [sp]
609 ; CHECK-BE-NEXT: vmov d0, r3, r2
610 ; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
611 ; CHECK-BE-NEXT: vrev64.32 q2, q0
612 ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
613 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4
614 ; CHECK-BE-NEXT: bx lr
615 entry:
616 %z = getelementptr inbounds i8, i8* %y, i32 4
617 %0 = bitcast i8* %x to <4 x float>*
618 %1 = load <4 x float>, <4 x float>* %0, align 4
619 %2 = bitcast i8* %y to <4 x float>*
620 %c = icmp sgt <4 x i32> %a, zeroinitializer
621 call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %c)
622 ret i8* %z
623 }
626 define arm_aapcs_vfpcc void @masked_v8f16(<8 x half> *%dest, <8 x half> %a, <8 x i16> %b) {
627 ; CHECK-LE-LABEL: masked_v8f16:
628 ; CHECK-LE: @ %bb.0: @ %entry
629 ; CHECK-LE-NEXT: vpt.i16 ne, q1, zr
630 ; CHECK-LE-NEXT: vstrht.16 q0, [r0]
631 ; CHECK-LE-NEXT: bx lr
632 ;
633 ; CHECK-BE-LABEL: masked_v8f16:
634 ; CHECK-BE: @ %bb.0: @ %entry
635 ; CHECK-BE-NEXT: vrev64.16 q2, q1
636 ; CHECK-BE-NEXT: vrev64.16 q1, q0
637 ; CHECK-BE-NEXT: vpt.i16 ne, q2, zr
638 ; CHECK-BE-NEXT: vstrht.16 q1, [r0]
639 ; CHECK-BE-NEXT: bx lr
640 entry:
641 %c = icmp ugt <8 x i16> %b, zeroinitializer
642 call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %a, <8 x half>* %dest, i32 2, <8 x i1> %c)
643 ret void
644 }
646 define arm_aapcs_vfpcc void @masked_v8f16_align1(<8 x half> *%dest, <8 x half> %a, <8 x i16> %b) {
647 ; CHECK-LE-LABEL: masked_v8f16_align1:
648 ; CHECK-LE: @ %bb.0: @ %entry
649 ; CHECK-LE-NEXT: .pad #36
650 ; CHECK-LE-NEXT: sub sp, #36
651 ; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr
652 ; CHECK-LE-NEXT: movs r2, #0
653 ; CHECK-LE-NEXT: vmrs r1, p0
654 ; CHECK-LE-NEXT: and r3, r1, #1
655 ; CHECK-LE-NEXT: rsbs r3, r3, #0
656 ; CHECK-LE-NEXT: bfi r2, r3, #0, #1
657 ; CHECK-LE-NEXT: ubfx r3, r1, #2, #1
658 ; CHECK-LE-NEXT: rsbs r3, r3, #0
659 ; CHECK-LE-NEXT: bfi r2, r3, #1, #1
660 ; CHECK-LE-NEXT: ubfx r3, r1, #4, #1
661 ; CHECK-LE-NEXT: rsbs r3, r3, #0
662 ; CHECK-LE-NEXT: bfi r2, r3, #2, #1
663 ; CHECK-LE-NEXT: ubfx r3, r1, #6, #1
664 ; CHECK-LE-NEXT: rsbs r3, r3, #0
665 ; CHECK-LE-NEXT: bfi r2, r3, #3, #1
666 ; CHECK-LE-NEXT: ubfx r3, r1, #8, #1
667 ; CHECK-LE-NEXT: rsbs r3, r3, #0
668 ; CHECK-LE-NEXT: bfi r2, r3, #4, #1
669 ; CHECK-LE-NEXT: ubfx r3, r1, #10, #1
670 ; CHECK-LE-NEXT: rsbs r3, r3, #0
671 ; CHECK-LE-NEXT: bfi r2, r3, #5, #1
672 ; CHECK-LE-NEXT: ubfx r3, r1, #12, #1
673 ; CHECK-LE-NEXT: ubfx r1, r1, #14, #1
674 ; CHECK-LE-NEXT: rsbs r3, r3, #0
675 ; CHECK-LE-NEXT: bfi r2, r3, #6, #1
676 ; CHECK-LE-NEXT: rsbs r1, r1, #0
677 ; CHECK-LE-NEXT: bfi r2, r1, #7, #1
678 ; CHECK-LE-NEXT: uxtb r1, r2
679 ; CHECK-LE-NEXT: lsls r2, r2, #31
680 ; CHECK-LE-NEXT: bne .LBB16_9
681 ; CHECK-LE-NEXT: @ %bb.1: @ %else
682 ; CHECK-LE-NEXT: lsls r2, r1, #30
683 ; CHECK-LE-NEXT: bmi .LBB16_10
684 ; CHECK-LE-NEXT: .LBB16_2: @ %else2
685 ; CHECK-LE-NEXT: lsls r2, r1, #29
686 ; CHECK-LE-NEXT: bmi .LBB16_11
687 ; CHECK-LE-NEXT: .LBB16_3: @ %else4
688 ; CHECK-LE-NEXT: lsls r2, r1, #28
689 ; CHECK-LE-NEXT: bmi .LBB16_12
690 ; CHECK-LE-NEXT: .LBB16_4: @ %else6
691 ; CHECK-LE-NEXT: lsls r2, r1, #27
692 ; CHECK-LE-NEXT: bmi .LBB16_13
693 ; CHECK-LE-NEXT: .LBB16_5: @ %else8
694 ; CHECK-LE-NEXT: lsls r2, r1, #26
695 ; CHECK-LE-NEXT: bmi .LBB16_14
696 ; CHECK-LE-NEXT: .LBB16_6: @ %else10
697 ; CHECK-LE-NEXT: lsls r2, r1, #25
698 ; CHECK-LE-NEXT: bmi .LBB16_15
699 ; CHECK-LE-NEXT: .LBB16_7: @ %else12
700 ; CHECK-LE-NEXT: lsls r1, r1, #24
701 ; CHECK-LE-NEXT: bmi .LBB16_16
702 ; CHECK-LE-NEXT: .LBB16_8: @ %else14
703 ; CHECK-LE-NEXT: add sp, #36
704 ; CHECK-LE-NEXT: bx lr
705 ; CHECK-LE-NEXT: .LBB16_9: @ %cond.store
706 ; CHECK-LE-NEXT: vstr.16 s0, [sp, #28]
707 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #28]
708 ; CHECK-LE-NEXT: strh r2, [r0]
709 ; CHECK-LE-NEXT: lsls r2, r1, #30
710 ; CHECK-LE-NEXT: bpl .LBB16_2
711 ; CHECK-LE-NEXT: .LBB16_10: @ %cond.store1
712 ; CHECK-LE-NEXT: vmovx.f16 s0, s0
713 ; CHECK-LE-NEXT: vstr.16 s0, [sp, #24]
714 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #24]
715 ; CHECK-LE-NEXT: strh r2, [r0, #2]
716 ; CHECK-LE-NEXT: lsls r2, r1, #29
717 ; CHECK-LE-NEXT: bpl .LBB16_3
718 ; CHECK-LE-NEXT: .LBB16_11: @ %cond.store3
719 ; CHECK-LE-NEXT: vstr.16 s1, [sp, #20]
720 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #20]
721 ; CHECK-LE-NEXT: strh r2, [r0, #4]
722 ; CHECK-LE-NEXT: lsls r2, r1, #28
723 ; CHECK-LE-NEXT: bpl .LBB16_4
724 ; CHECK-LE-NEXT: .LBB16_12: @ %cond.store5
725 ; CHECK-LE-NEXT: vmovx.f16 s0, s1
726 ; CHECK-LE-NEXT: vstr.16 s0, [sp, #16]
727 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #16]
728 ; CHECK-LE-NEXT: strh r2, [r0, #6]
729 ; CHECK-LE-NEXT: lsls r2, r1, #27
730 ; CHECK-LE-NEXT: bpl .LBB16_5
731 ; CHECK-LE-NEXT: .LBB16_13: @ %cond.store7
732 ; CHECK-LE-NEXT: vstr.16 s2, [sp, #12]
733 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #12]
734 ; CHECK-LE-NEXT: strh r2, [r0, #8]
735 ; CHECK-LE-NEXT: lsls r2, r1, #26
736 ; CHECK-LE-NEXT: bpl .LBB16_6
737 ; CHECK-LE-NEXT: .LBB16_14: @ %cond.store9
738 ; CHECK-LE-NEXT: vmovx.f16 s0, s2
739 ; CHECK-LE-NEXT: vstr.16 s0, [sp, #8]
740 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #8]
741 ; CHECK-LE-NEXT: strh r2, [r0, #10]
742 ; CHECK-LE-NEXT: lsls r2, r1, #25
743 ; CHECK-LE-NEXT: bpl .LBB16_7
744 ; CHECK-LE-NEXT: .LBB16_15: @ %cond.store11
745 ; CHECK-LE-NEXT: vstr.16 s3, [sp, #4]
746 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #4]
747 ; CHECK-LE-NEXT: strh r2, [r0, #12]
748 ; CHECK-LE-NEXT: lsls r1, r1, #24
749 ; CHECK-LE-NEXT: bpl .LBB16_8
750 ; CHECK-LE-NEXT: .LBB16_16: @ %cond.store13
751 ; CHECK-LE-NEXT: vmovx.f16 s0, s3
752 ; CHECK-LE-NEXT: vstr.16 s0, [sp]
753 ; CHECK-LE-NEXT: ldrh.w r1, [sp]
754 ; CHECK-LE-NEXT: strh r1, [r0, #14]
755 ; CHECK-LE-NEXT: add sp, #36
756 ; CHECK-LE-NEXT: bx lr
757 ;
758 ; CHECK-BE-LABEL: masked_v8f16_align1:
759 ; CHECK-BE: @ %bb.0: @ %entry
760 ; CHECK-BE-NEXT: .pad #36
761 ; CHECK-BE-NEXT: sub sp, #36
762 ; CHECK-BE-NEXT: vrev64.16 q2, q1
763 ; CHECK-BE-NEXT: vrev64.16 q1, q0
764 ; CHECK-BE-NEXT: vcmp.i16 ne, q2, zr
765 ; CHECK-BE-NEXT: vmrs r1, p0
766 ; CHECK-BE-NEXT: ubfx r2, r1, #14, #1
767 ; CHECK-BE-NEXT: rsbs r3, r2, #0
768 ; CHECK-BE-NEXT: movs r2, #0
769 ; CHECK-BE-NEXT: bfi r2, r3, #0, #1
770 ; CHECK-BE-NEXT: ubfx r3, r1, #12, #1
771 ; CHECK-BE-NEXT: rsbs r3, r3, #0
772 ; CHECK-BE-NEXT: bfi r2, r3, #1, #1
773 ; CHECK-BE-NEXT: ubfx r3, r1, #10, #1
774 ; CHECK-BE-NEXT: rsbs r3, r3, #0
775 ; CHECK-BE-NEXT: bfi r2, r3, #2, #1
776 ; CHECK-BE-NEXT: ubfx r3, r1, #8, #1
777 ; CHECK-BE-NEXT: rsbs r3, r3, #0
778 ; CHECK-BE-NEXT: bfi r2, r3, #3, #1
779 ; CHECK-BE-NEXT: ubfx r3, r1, #6, #1
780 ; CHECK-BE-NEXT: rsbs r3, r3, #0
781 ; CHECK-BE-NEXT: bfi r2, r3, #4, #1
782 ; CHECK-BE-NEXT: ubfx r3, r1, #4, #1
783 ; CHECK-BE-NEXT: rsbs r3, r3, #0
784 ; CHECK-BE-NEXT: bfi r2, r3, #5, #1
785 ; CHECK-BE-NEXT: ubfx r3, r1, #2, #1
786 ; CHECK-BE-NEXT: and r1, r1, #1
787 ; CHECK-BE-NEXT: rsbs r3, r3, #0
788 ; CHECK-BE-NEXT: bfi r2, r3, #6, #1
789 ; CHECK-BE-NEXT: rsbs r1, r1, #0
790 ; CHECK-BE-NEXT: bfi r2, r1, #7, #1
791 ; CHECK-BE-NEXT: uxtb r1, r2
792 ; CHECK-BE-NEXT: lsls r2, r2, #24
793 ; CHECK-BE-NEXT: bmi .LBB16_9
794 ; CHECK-BE-NEXT: @ %bb.1: @ %else
795 ; CHECK-BE-NEXT: lsls r2, r1, #25
796 ; CHECK-BE-NEXT: bmi .LBB16_10
797 ; CHECK-BE-NEXT: .LBB16_2: @ %else2
798 ; CHECK-BE-NEXT: lsls r2, r1, #26
799 ; CHECK-BE-NEXT: bmi .LBB16_11
800 ; CHECK-BE-NEXT: .LBB16_3: @ %else4
801 ; CHECK-BE-NEXT: lsls r2, r1, #27
802 ; CHECK-BE-NEXT: bmi .LBB16_12
803 ; CHECK-BE-NEXT: .LBB16_4: @ %else6
804 ; CHECK-BE-NEXT: lsls r2, r1, #28
805 ; CHECK-BE-NEXT: bmi .LBB16_13
806 ; CHECK-BE-NEXT: .LBB16_5: @ %else8
807 ; CHECK-BE-NEXT: lsls r2, r1, #29
808 ; CHECK-BE-NEXT: bmi .LBB16_14
809 ; CHECK-BE-NEXT: .LBB16_6: @ %else10
810 ; CHECK-BE-NEXT: lsls r2, r1, #30
811 ; CHECK-BE-NEXT: bmi .LBB16_15
812 ; CHECK-BE-NEXT: .LBB16_7: @ %else12
813 ; CHECK-BE-NEXT: lsls r1, r1, #31
814 ; CHECK-BE-NEXT: bne .LBB16_16
815 ; CHECK-BE-NEXT: .LBB16_8: @ %else14
816 ; CHECK-BE-NEXT: add sp, #36
817 ; CHECK-BE-NEXT: bx lr
818 ; CHECK-BE-NEXT: .LBB16_9: @ %cond.store
819 ; CHECK-BE-NEXT: vstr.16 s4, [sp, #28]
820 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #28]
821 ; CHECK-BE-NEXT: strh r2, [r0]
822 ; CHECK-BE-NEXT: lsls r2, r1, #25
823 ; CHECK-BE-NEXT: bpl .LBB16_2
824 ; CHECK-BE-NEXT: .LBB16_10: @ %cond.store1
825 ; CHECK-BE-NEXT: vmovx.f16 s0, s4
826 ; CHECK-BE-NEXT: vstr.16 s0, [sp, #24]
827 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #24]
828 ; CHECK-BE-NEXT: strh r2, [r0, #2]
829 ; CHECK-BE-NEXT: lsls r2, r1, #26
830 ; CHECK-BE-NEXT: bpl .LBB16_3
831 ; CHECK-BE-NEXT: .LBB16_11: @ %cond.store3
832 ; CHECK-BE-NEXT: vstr.16 s5, [sp, #20]
833 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #20]
834 ; CHECK-BE-NEXT: strh r2, [r0, #4]
835 ; CHECK-BE-NEXT: lsls r2, r1, #27
836 ; CHECK-BE-NEXT: bpl .LBB16_4
837 ; CHECK-BE-NEXT: .LBB16_12: @ %cond.store5
838 ; CHECK-BE-NEXT: vmovx.f16 s0, s5
839 ; CHECK-BE-NEXT: vstr.16 s0, [sp, #16]
840 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #16]
841 ; CHECK-BE-NEXT: strh r2, [r0, #6]
842 ; CHECK-BE-NEXT: lsls r2, r1, #28
843 ; CHECK-BE-NEXT: bpl .LBB16_5
844 ; CHECK-BE-NEXT: .LBB16_13: @ %cond.store7
845 ; CHECK-BE-NEXT: vstr.16 s6, [sp, #12]
846 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #12]
847 ; CHECK-BE-NEXT: strh r2, [r0, #8]
848 ; CHECK-BE-NEXT: lsls r2, r1, #29
849 ; CHECK-BE-NEXT: bpl .LBB16_6
850 ; CHECK-BE-NEXT: .LBB16_14: @ %cond.store9
851 ; CHECK-BE-NEXT: vmovx.f16 s0, s6
852 ; CHECK-BE-NEXT: vstr.16 s0, [sp, #8]
853 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #8]
854 ; CHECK-BE-NEXT: strh r2, [r0, #10]
855 ; CHECK-BE-NEXT: lsls r2, r1, #30
856 ; CHECK-BE-NEXT: bpl .LBB16_7
857 ; CHECK-BE-NEXT: .LBB16_15: @ %cond.store11
858 ; CHECK-BE-NEXT: vstr.16 s7, [sp, #4]
859 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #4]
860 ; CHECK-BE-NEXT: strh r2, [r0, #12]
861 ; CHECK-BE-NEXT: lsls r1, r1, #31
862 ; CHECK-BE-NEXT: beq .LBB16_8
863 ; CHECK-BE-NEXT: .LBB16_16: @ %cond.store13
864 ; CHECK-BE-NEXT: vmovx.f16 s0, s7
865 ; CHECK-BE-NEXT: vstr.16 s0, [sp]
866 ; CHECK-BE-NEXT: ldrh.w r1, [sp]
867 ; CHECK-BE-NEXT: strh r1, [r0, #14]
868 ; CHECK-BE-NEXT: add sp, #36
869 ; CHECK-BE-NEXT: bx lr
870 entry:
871 %c = icmp ugt <8 x i16> %b, zeroinitializer
872 call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %a, <8 x half>* %dest, i32 1, <8 x i1> %c)
873 ret void
874 }
876 define i8* @masked_v8f16_pre(i8* %y, i8* %x, <8 x i16> %a) {
877 ; CHECK-LE-LABEL: masked_v8f16_pre:
878 ; CHECK-LE: @ %bb.0: @ %entry
879 ; CHECK-LE-NEXT: vldr d1, [sp]
880 ; CHECK-LE-NEXT: vmov d0, r2, r3
881 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
882 ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
883 ; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]!
884 ; CHECK-LE-NEXT: bx lr
885 ;
886 ; CHECK-BE-LABEL: masked_v8f16_pre:
887 ; CHECK-BE: @ %bb.0: @ %entry
888 ; CHECK-BE-NEXT: vldr d1, [sp]
889 ; CHECK-BE-NEXT: vmov d0, r3, r2
890 ; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
891 ; CHECK-BE-NEXT: vrev64.16 q2, q0
892 ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
893 ; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]!
894 ; CHECK-BE-NEXT: bx lr
895 entry:
896 %z = getelementptr inbounds i8, i8* %y, i32 4
897 %0 = bitcast i8* %x to <8 x half>*
898 %1 = load <8 x half>, <8 x half>* %0, align 4
899 %2 = bitcast i8* %z to <8 x half>*
900 %c = icmp sgt <8 x i16> %a, zeroinitializer
901 call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %1, <8 x half>* %2, i32 2, <8 x i1> %c)
902 ret i8* %z
903 }
905 define i8* @masked_v8f16_post(i8* %y, i8* %x, <8 x i16> %a) {
906 ; CHECK-LE-LABEL: masked_v8f16_post:
907 ; CHECK-LE: @ %bb.0: @ %entry
908 ; CHECK-LE-NEXT: vldr d1, [sp]
909 ; CHECK-LE-NEXT: vmov d0, r2, r3
910 ; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
911 ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
912 ; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4
913 ; CHECK-LE-NEXT: bx lr
914 ;
915 ; CHECK-BE-LABEL: masked_v8f16_post:
916 ; CHECK-BE: @ %bb.0: @ %entry
917 ; CHECK-BE-NEXT: vldr d1, [sp]
918 ; CHECK-BE-NEXT: vmov d0, r3, r2
919 ; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
920 ; CHECK-BE-NEXT: vrev64.16 q2, q0
921 ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
922 ; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4
923 ; CHECK-BE-NEXT: bx lr
924 entry:
925 %z = getelementptr inbounds i8, i8* %y, i32 4
926 %0 = bitcast i8* %x to <8 x half>*
927 %1 = load <8 x half>, <8 x half>* %0, align 4
928 %2 = bitcast i8* %y to <8 x half>*
929 %c = icmp sgt <8 x i16> %a, zeroinitializer
930 call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %1, <8 x half>* %2, i32 2, <8 x i1> %c)
931 ret i8* %z
932 }
935 define arm_aapcs_vfpcc void @masked_v2i64(<2 x i64> *%dest, <2 x i64> %a) {
936 ; CHECK-LE-LABEL: masked_v2i64:
937 ; CHECK-LE: @ %bb.0: @ %entry
938 ; CHECK-LE-NEXT: .save {r7, lr}
939 ; CHECK-LE-NEXT: push {r7, lr}
940 ; CHECK-LE-NEXT: .pad #4
941 ; CHECK-LE-NEXT: sub sp, #4
942 ; CHECK-LE-NEXT: vmov r1, r2, d0
943 ; CHECK-LE-NEXT: movs r3, #0
944 ; CHECK-LE-NEXT: vmov lr, r12, d1
945 ; CHECK-LE-NEXT: rsbs r1, r1, #0
946 ; CHECK-LE-NEXT: sbcs.w r1, r3, r2
947 ; CHECK-LE-NEXT: mov.w r1, #0
948 ; CHECK-LE-NEXT: it lt
949 ; CHECK-LE-NEXT: movlt r1, #1
950 ; CHECK-LE-NEXT: rsbs.w r2, lr, #0
951 ; CHECK-LE-NEXT: sbcs.w r2, r3, r12
952 ; CHECK-LE-NEXT: it lt
953 ; CHECK-LE-NEXT: movlt r3, #1
954 ; CHECK-LE-NEXT: cmp r3, #0
955 ; CHECK-LE-NEXT: it ne
956 ; CHECK-LE-NEXT: mvnne r3, #1
957 ; CHECK-LE-NEXT: bfi r3, r1, #0, #1
958 ; CHECK-LE-NEXT: and r1, r3, #3
959 ; CHECK-LE-NEXT: lsls r2, r3, #31
960 ; CHECK-LE-NEXT: it ne
961 ; CHECK-LE-NEXT: vstrne d0, [r0]
962 ; CHECK-LE-NEXT: lsls r1, r1, #30
963 ; CHECK-LE-NEXT: it mi
964 ; CHECK-LE-NEXT: vstrmi d1, [r0, #8]
965 ; CHECK-LE-NEXT: add sp, #4
966 ; CHECK-LE-NEXT: pop {r7, pc}
967 ;
968 ; CHECK-BE-LABEL: masked_v2i64:
969 ; CHECK-BE: @ %bb.0: @ %entry
970 ; CHECK-BE-NEXT: .save {r7, lr}
971 ; CHECK-BE-NEXT: push {r7, lr}
972 ; CHECK-BE-NEXT: .pad #4
973 ; CHECK-BE-NEXT: sub sp, #4
974 ; CHECK-BE-NEXT: vrev64.32 q1, q0
975 ; CHECK-BE-NEXT: movs r3, #0
976 ; CHECK-BE-NEXT: vmov r1, r2, d3
977 ; CHECK-BE-NEXT: vmov r12, lr, d2
978 ; CHECK-BE-NEXT: rsbs r2, r2, #0
979 ; CHECK-BE-NEXT: sbcs.w r1, r3, r1
980 ; CHECK-BE-NEXT: mov.w r1, #0
981 ; CHECK-BE-NEXT: it lt
982 ; CHECK-BE-NEXT: movlt r1, #1
983 ; CHECK-BE-NEXT: rsbs.w r2, lr, #0
984 ; CHECK-BE-NEXT: sbcs.w r2, r3, r12
985 ; CHECK-BE-NEXT: it lt
986 ; CHECK-BE-NEXT: movlt r3, #1
987 ; CHECK-BE-NEXT: cmp r3, #0
988 ; CHECK-BE-NEXT: it ne
989 ; CHECK-BE-NEXT: mvnne r3, #1
990 ; CHECK-BE-NEXT: bfi r3, r1, #0, #1
991 ; CHECK-BE-NEXT: and r1, r3, #3
992 ; CHECK-BE-NEXT: lsls r2, r3, #30
993 ; CHECK-BE-NEXT: it mi
994 ; CHECK-BE-NEXT: vstrmi d0, [r0]
995 ; CHECK-BE-NEXT: lsls r1, r1, #31
996 ; CHECK-BE-NEXT: it ne
997 ; CHECK-BE-NEXT: vstrne d1, [r0, #8]
998 ; CHECK-BE-NEXT: add sp, #4
999 ; CHECK-BE-NEXT: pop {r7, pc}
1000 entry:
1001 %c = icmp sgt <2 x i64> %a, zeroinitializer
1002 call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %a, <2 x i64>* %dest, i32 8, <2 x i1> %c)
1003 ret void
1004 }
1006 define arm_aapcs_vfpcc void @masked_v2f64(<2 x double> *%dest, <2 x double> %a, <2 x i64> %b) {
1007 ; CHECK-LE-LABEL: masked_v2f64:
1008 ; CHECK-LE: @ %bb.0: @ %entry
1009 ; CHECK-LE-NEXT: .save {r7, lr}
1010 ; CHECK-LE-NEXT: push {r7, lr}
1011 ; CHECK-LE-NEXT: .pad #4
1012 ; CHECK-LE-NEXT: sub sp, #4
1013 ; CHECK-LE-NEXT: vmov r1, r2, d2
1014 ; CHECK-LE-NEXT: movs r3, #0
1015 ; CHECK-LE-NEXT: vmov lr, r12, d3
1016 ; CHECK-LE-NEXT: rsbs r1, r1, #0
1017 ; CHECK-LE-NEXT: sbcs.w r1, r3, r2
1018 ; CHECK-LE-NEXT: mov.w r1, #0
1019 ; CHECK-LE-NEXT: it lt
1020 ; CHECK-LE-NEXT: movlt r1, #1
1021 ; CHECK-LE-NEXT: rsbs.w r2, lr, #0
1022 ; CHECK-LE-NEXT: sbcs.w r2, r3, r12
1023 ; CHECK-LE-NEXT: it lt
1024 ; CHECK-LE-NEXT: movlt r3, #1
1025 ; CHECK-LE-NEXT: cmp r3, #0
1026 ; CHECK-LE-NEXT: it ne
1027 ; CHECK-LE-NEXT: mvnne r3, #1
1028 ; CHECK-LE-NEXT: bfi r3, r1, #0, #1
1029 ; CHECK-LE-NEXT: and r1, r3, #3
1030 ; CHECK-LE-NEXT: lsls r2, r3, #31
1031 ; CHECK-LE-NEXT: it ne
1032 ; CHECK-LE-NEXT: vstrne d0, [r0]
1033 ; CHECK-LE-NEXT: lsls r1, r1, #30
1034 ; CHECK-LE-NEXT: it mi
1035 ; CHECK-LE-NEXT: vstrmi d1, [r0, #8]
1036 ; CHECK-LE-NEXT: add sp, #4
1037 ; CHECK-LE-NEXT: pop {r7, pc}
1038 ;
1039 ; CHECK-BE-LABEL: masked_v2f64:
1040 ; CHECK-BE: @ %bb.0: @ %entry
1041 ; CHECK-BE-NEXT: .save {r7, lr}
1042 ; CHECK-BE-NEXT: push {r7, lr}
1043 ; CHECK-BE-NEXT: .pad #4
1044 ; CHECK-BE-NEXT: sub sp, #4
1045 ; CHECK-BE-NEXT: vrev64.32 q2, q1
1046 ; CHECK-BE-NEXT: movs r3, #0
1047 ; CHECK-BE-NEXT: vmov r1, r2, d5
1048 ; CHECK-BE-NEXT: vmov r12, lr, d4
1049 ; CHECK-BE-NEXT: rsbs r2, r2, #0
1050 ; CHECK-BE-NEXT: sbcs.w r1, r3, r1
1051 ; CHECK-BE-NEXT: mov.w r1, #0
1052 ; CHECK-BE-NEXT: it lt
1053 ; CHECK-BE-NEXT: movlt r1, #1
1054 ; CHECK-BE-NEXT: rsbs.w r2, lr, #0
1055 ; CHECK-BE-NEXT: sbcs.w r2, r3, r12
1056 ; CHECK-BE-NEXT: it lt
1057 ; CHECK-BE-NEXT: movlt r3, #1
1058 ; CHECK-BE-NEXT: cmp r3, #0
1059 ; CHECK-BE-NEXT: it ne
1060 ; CHECK-BE-NEXT: mvnne r3, #1
1061 ; CHECK-BE-NEXT: bfi r3, r1, #0, #1
1062 ; CHECK-BE-NEXT: and r1, r3, #3
1063 ; CHECK-BE-NEXT: lsls r2, r3, #30
1064 ; CHECK-BE-NEXT: it mi
1065 ; CHECK-BE-NEXT: vstrmi d0, [r0]
1066 ; CHECK-BE-NEXT: lsls r1, r1, #31
1067 ; CHECK-BE-NEXT: it ne
1068 ; CHECK-BE-NEXT: vstrne d1, [r0, #8]
1069 ; CHECK-BE-NEXT: add sp, #4
1070 ; CHECK-BE-NEXT: pop {r7, pc}
1071 entry:
1072 %c = icmp sgt <2 x i64> %b, zeroinitializer
1073 call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %a, <2 x double>* %dest, i32 8, <2 x i1> %c)
1074 ret void
1075 }
1077 define arm_aapcs_vfpcc void @masked_v4i16(<4 x i16> *%dest, <4 x i32> %a) {
1078 ; CHECK-LE-LABEL: masked_v4i16:
1079 ; CHECK-LE: @ %bb.0: @ %entry
1080 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
1081 ; CHECK-LE-NEXT: vstrht.32 q0, [r0]
1082 ; CHECK-LE-NEXT: bx lr
1083 ;
1084 ; CHECK-BE-LABEL: masked_v4i16:
1085 ; CHECK-BE: @ %bb.0: @ %entry
1086 ; CHECK-BE-NEXT: vrev64.32 q1, q0
1087 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
1088 ; CHECK-BE-NEXT: vstrht.32 q1, [r0]
1089 ; CHECK-BE-NEXT: bx lr
1090 entry:
1091 %c = icmp sgt <4 x i32> %a, zeroinitializer
1092 %trunc = trunc <4 x i32> %a to <4 x i16>
1093 call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> %trunc, <4 x i16>* %dest, i32 2, <4 x i1> %c)
1094 ret void
1095 }
1097 define arm_aapcs_vfpcc void @masked_v4i8(<4 x i8> *%dest, <4 x i32> %a) {
1098 ; CHECK-LE-LABEL: masked_v4i8:
1099 ; CHECK-LE: @ %bb.0: @ %entry
1100 ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
1101 ; CHECK-LE-NEXT: vstrbt.32 q0, [r0]
1102 ; CHECK-LE-NEXT: bx lr
1103 ;
1104 ; CHECK-BE-LABEL: masked_v4i8:
1105 ; CHECK-BE: @ %bb.0: @ %entry
1106 ; CHECK-BE-NEXT: vrev64.32 q1, q0
1107 ; CHECK-BE-NEXT: vpt.s32 gt, q1, zr
1108 ; CHECK-BE-NEXT: vstrbt.32 q1, [r0]
1109 ; CHECK-BE-NEXT: bx lr
1110 entry:
1111 %c = icmp sgt <4 x i32> %a, zeroinitializer
1112 %trunc = trunc <4 x i32> %a to <4 x i8>
1113 call void @llvm.masked.store.v4i8.p0v4i8(<4 x i8> %trunc, <4 x i8>* %dest, i32 1, <4 x i1> %c)
1114 ret void
1115 }
1117 define arm_aapcs_vfpcc void @masked_v8i8(<8 x i8> *%dest, <8 x i16> %a) {
1118 ; CHECK-LE-LABEL: masked_v8i8:
1119 ; CHECK-LE: @ %bb.0: @ %entry
1120 ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
1121 ; CHECK-LE-NEXT: vstrbt.16 q0, [r0]
1122 ; CHECK-LE-NEXT: bx lr
1123 ;
1124 ; CHECK-BE-LABEL: masked_v8i8:
1125 ; CHECK-BE: @ %bb.0: @ %entry
1126 ; CHECK-BE-NEXT: vrev64.16 q1, q0
1127 ; CHECK-BE-NEXT: vpt.s16 gt, q1, zr
1128 ; CHECK-BE-NEXT: vstrbt.16 q1, [r0]
1129 ; CHECK-BE-NEXT: bx lr
1130 entry:
1131 %c = icmp sgt <8 x i16> %a, zeroinitializer
1132 %trunc = trunc <8 x i16> %a to <8 x i8>
1133 call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> %trunc, <8 x i8>* %dest, i32 1, <8 x i1> %c)
1134 ret void
1135 }
1137 define arm_aapcs_vfpcc void @masked_v4i16_align1(<4 x i16> *%dest, <4 x i32> %a) {
1138 ; CHECK-LE-LABEL: masked_v4i16_align1:
1139 ; CHECK-LE: @ %bb.0: @ %entry
1140 ; CHECK-LE-NEXT: .pad #4
1141 ; CHECK-LE-NEXT: sub sp, #4
1142 ; CHECK-LE-NEXT: vcmp.s32 gt, q0, zr
1143 ; CHECK-LE-NEXT: vmrs r2, p0
1144 ; CHECK-LE-NEXT: and r1, r2, #1
1145 ; CHECK-LE-NEXT: rsbs r3, r1, #0
1146 ; CHECK-LE-NEXT: movs r1, #0
1147 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
1148 ; CHECK-LE-NEXT: ubfx r3, r2, #4, #1
1149 ; CHECK-LE-NEXT: rsbs r3, r3, #0
1150 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
1151 ; CHECK-LE-NEXT: ubfx r3, r2, #8, #1
1152 ; CHECK-LE-NEXT: ubfx r2, r2, #12, #1
1153 ; CHECK-LE-NEXT: rsbs r3, r3, #0
1154 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
1155 ; CHECK-LE-NEXT: rsbs r2, r2, #0
1156 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
1157 ; CHECK-LE-NEXT: lsls r2, r1, #31
1158 ; CHECK-LE-NEXT: itt ne
1159 ; CHECK-LE-NEXT: vmovne r2, s0
1160 ; CHECK-LE-NEXT: strhne r2, [r0]
1161 ; CHECK-LE-NEXT: lsls r2, r1, #30
1162 ; CHECK-LE-NEXT: itt mi
1163 ; CHECK-LE-NEXT: vmovmi r2, s1
1164 ; CHECK-LE-NEXT: strhmi r2, [r0, #2]
1165 ; CHECK-LE-NEXT: lsls r2, r1, #29
1166 ; CHECK-LE-NEXT: itt mi
1167 ; CHECK-LE-NEXT: vmovmi r2, s2
1168 ; CHECK-LE-NEXT: strhmi r2, [r0, #4]
1169 ; CHECK-LE-NEXT: lsls r1, r1, #28
1170 ; CHECK-LE-NEXT: itt mi
1171 ; CHECK-LE-NEXT: vmovmi r1, s3
1172 ; CHECK-LE-NEXT: strhmi r1, [r0, #6]
1173 ; CHECK-LE-NEXT: add sp, #4
1174 ; CHECK-LE-NEXT: bx lr
1175 ;
1176 ; CHECK-BE-LABEL: masked_v4i16_align1:
1177 ; CHECK-BE: @ %bb.0: @ %entry
1178 ; CHECK-BE-NEXT: .pad #4
1179 ; CHECK-BE-NEXT: sub sp, #4
1180 ; CHECK-BE-NEXT: vrev64.32 q1, q0
1181 ; CHECK-BE-NEXT: vcmp.s32 gt, q1, zr
1182 ; CHECK-BE-NEXT: vmrs r2, p0
1183 ; CHECK-BE-NEXT: ubfx r1, r2, #12, #1
1184 ; CHECK-BE-NEXT: rsbs r3, r1, #0
1185 ; CHECK-BE-NEXT: movs r1, #0
1186 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
1187 ; CHECK-BE-NEXT: ubfx r3, r2, #8, #1
1188 ; CHECK-BE-NEXT: rsbs r3, r3, #0
1189 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
1190 ; CHECK-BE-NEXT: ubfx r3, r2, #4, #1
1191 ; CHECK-BE-NEXT: and r2, r2, #1
1192 ; CHECK-BE-NEXT: rsbs r3, r3, #0
1193 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
1194 ; CHECK-BE-NEXT: rsbs r2, r2, #0
1195 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
1196 ; CHECK-BE-NEXT: lsls r2, r1, #28
1197 ; CHECK-BE-NEXT: itt mi
1198 ; CHECK-BE-NEXT: vmovmi r2, s4
1199 ; CHECK-BE-NEXT: strhmi r2, [r0]
1200 ; CHECK-BE-NEXT: lsls r2, r1, #29
1201 ; CHECK-BE-NEXT: itt mi
1202 ; CHECK-BE-NEXT: vmovmi r2, s5
1203 ; CHECK-BE-NEXT: strhmi r2, [r0, #2]
1204 ; CHECK-BE-NEXT: lsls r2, r1, #30
1205 ; CHECK-BE-NEXT: itt mi
1206 ; CHECK-BE-NEXT: vmovmi r2, s6
1207 ; CHECK-BE-NEXT: strhmi r2, [r0, #4]
1208 ; CHECK-BE-NEXT: lsls r1, r1, #31
1209 ; CHECK-BE-NEXT: itt ne
1210 ; CHECK-BE-NEXT: vmovne r1, s7
1211 ; CHECK-BE-NEXT: strhne r1, [r0, #6]
1212 ; CHECK-BE-NEXT: add sp, #4
1213 ; CHECK-BE-NEXT: bx lr
1214 entry:
1215 %c = icmp sgt <4 x i32> %a, zeroinitializer
1216 %trunc = trunc <4 x i32> %a to <4 x i16>
1217 call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> %trunc, <4 x i16>* %dest, i32 1, <4 x i1> %c)
1218 ret void
1219 }
1221 define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float> %a) {
1222 ; CHECK-LE-LABEL: masked_v4f16_align4:
1223 ; CHECK-LE: @ %bb.0: @ %entry
1224 ; CHECK-LE-NEXT: .pad #4
1225 ; CHECK-LE-NEXT: sub sp, #4
1226 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
1227 ; CHECK-LE-NEXT: movs r1, #0
1228 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1229 ; CHECK-LE-NEXT: it gt
1230 ; CHECK-LE-NEXT: movgt r1, #1
1231 ; CHECK-LE-NEXT: cmp r1, #0
1232 ; CHECK-LE-NEXT: mov.w r1, #0
1233 ; CHECK-LE-NEXT: csetm r3, ne
1234 ; CHECK-LE-NEXT: vcmp.f32 s1, #0
1235 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
1236 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1237 ; CHECK-LE-NEXT: mov.w r3, #0
1238 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
1239 ; CHECK-LE-NEXT: it gt
1240 ; CHECK-LE-NEXT: movgt r3, #1
1241 ; CHECK-LE-NEXT: cmp r3, #0
1242 ; CHECK-LE-NEXT: csetm r3, ne
1243 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1244 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
1245 ; CHECK-LE-NEXT: mov.w r3, #0
1246 ; CHECK-LE-NEXT: it gt
1247 ; CHECK-LE-NEXT: movgt r3, #1
1248 ; CHECK-LE-NEXT: cmp r3, #0
1249 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
1250 ; CHECK-LE-NEXT: csetm r3, ne
1251 ; CHECK-LE-NEXT: movs r2, #0
1252 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1253 ; CHECK-LE-NEXT: it gt
1254 ; CHECK-LE-NEXT: movgt r2, #1
1255 ; CHECK-LE-NEXT: cmp r2, #0
1256 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
1257 ; CHECK-LE-NEXT: csetm r2, ne
1258 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
1259 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
1260 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
1261 ; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
1262 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
1263 ; CHECK-LE-NEXT: lsls r2, r1, #31
1264 ; CHECK-LE-NEXT: bne .LBB25_5
1265 ; CHECK-LE-NEXT: @ %bb.1: @ %else
1266 ; CHECK-LE-NEXT: lsls r2, r1, #30
1267 ; CHECK-LE-NEXT: bmi .LBB25_6
1268 ; CHECK-LE-NEXT: .LBB25_2: @ %else2
1269 ; CHECK-LE-NEXT: lsls r2, r1, #29
1270 ; CHECK-LE-NEXT: bmi .LBB25_7
1271 ; CHECK-LE-NEXT: .LBB25_3: @ %else4
1272 ; CHECK-LE-NEXT: lsls r1, r1, #28
1273 ; CHECK-LE-NEXT: bmi .LBB25_8
1274 ; CHECK-LE-NEXT: .LBB25_4: @ %else6
1275 ; CHECK-LE-NEXT: add sp, #4
1276 ; CHECK-LE-NEXT: bx lr
1277 ; CHECK-LE-NEXT: .LBB25_5: @ %cond.store
1278 ; CHECK-LE-NEXT: vstr.16 s4, [r0]
1279 ; CHECK-LE-NEXT: lsls r2, r1, #30
1280 ; CHECK-LE-NEXT: bpl .LBB25_2
1281 ; CHECK-LE-NEXT: .LBB25_6: @ %cond.store1
1282 ; CHECK-LE-NEXT: vmovx.f16 s0, s4
1283 ; CHECK-LE-NEXT: vstr.16 s0, [r0, #2]
1284 ; CHECK-LE-NEXT: lsls r2, r1, #29
1285 ; CHECK-LE-NEXT: bpl .LBB25_3
1286 ; CHECK-LE-NEXT: .LBB25_7: @ %cond.store3
1287 ; CHECK-LE-NEXT: vstr.16 s5, [r0, #4]
1288 ; CHECK-LE-NEXT: lsls r1, r1, #28
1289 ; CHECK-LE-NEXT: bpl .LBB25_4
1290 ; CHECK-LE-NEXT: .LBB25_8: @ %cond.store5
1291 ; CHECK-LE-NEXT: vmovx.f16 s0, s5
1292 ; CHECK-LE-NEXT: vstr.16 s0, [r0, #6]
1293 ; CHECK-LE-NEXT: add sp, #4
1294 ; CHECK-LE-NEXT: bx lr
1295 ;
1296 ; CHECK-BE-LABEL: masked_v4f16_align4:
1297 ; CHECK-BE: @ %bb.0: @ %entry
1298 ; CHECK-BE-NEXT: .pad #4
1299 ; CHECK-BE-NEXT: sub sp, #4
1300 ; CHECK-BE-NEXT: vrev64.32 q1, q0
1301 ; CHECK-BE-NEXT: movs r1, #0
1302 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
1303 ; CHECK-BE-NEXT: movs r2, #0
1304 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1305 ; CHECK-BE-NEXT: it gt
1306 ; CHECK-BE-NEXT: movgt r1, #1
1307 ; CHECK-BE-NEXT: cmp r1, #0
1308 ; CHECK-BE-NEXT: mov.w r1, #0
1309 ; CHECK-BE-NEXT: csetm r3, ne
1310 ; CHECK-BE-NEXT: vcmp.f32 s6, #0
1311 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
1312 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1313 ; CHECK-BE-NEXT: mov.w r3, #0
1314 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
1315 ; CHECK-BE-NEXT: it gt
1316 ; CHECK-BE-NEXT: movgt r3, #1
1317 ; CHECK-BE-NEXT: cmp r3, #0
1318 ; CHECK-BE-NEXT: csetm r3, ne
1319 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1320 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
1321 ; CHECK-BE-NEXT: mov.w r3, #0
1322 ; CHECK-BE-NEXT: it gt
1323 ; CHECK-BE-NEXT: movgt r3, #1
1324 ; CHECK-BE-NEXT: cmp r3, #0
1325 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
1326 ; CHECK-BE-NEXT: csetm r3, ne
1327 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1328 ; CHECK-BE-NEXT: it gt
1329 ; CHECK-BE-NEXT: movgt r2, #1
1330 ; CHECK-BE-NEXT: cmp r2, #0
1331 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
1332 ; CHECK-BE-NEXT: csetm r2, ne
1333 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
1334 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
1335 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
1336 ; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
1337 ; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
1338 ; CHECK-BE-NEXT: lsls r2, r1, #28
1339 ; CHECK-BE-NEXT: bmi .LBB25_5
1340 ; CHECK-BE-NEXT: @ %bb.1: @ %else
1341 ; CHECK-BE-NEXT: lsls r2, r1, #29
1342 ; CHECK-BE-NEXT: bmi .LBB25_6
1343 ; CHECK-BE-NEXT: .LBB25_2: @ %else2
1344 ; CHECK-BE-NEXT: lsls r2, r1, #30
1345 ; CHECK-BE-NEXT: bmi .LBB25_7
1346 ; CHECK-BE-NEXT: .LBB25_3: @ %else4
1347 ; CHECK-BE-NEXT: lsls r1, r1, #31
1348 ; CHECK-BE-NEXT: bne .LBB25_8
1349 ; CHECK-BE-NEXT: .LBB25_4: @ %else6
1350 ; CHECK-BE-NEXT: add sp, #4
1351 ; CHECK-BE-NEXT: bx lr
1352 ; CHECK-BE-NEXT: .LBB25_5: @ %cond.store
1353 ; CHECK-BE-NEXT: vstr.16 s0, [r0]
1354 ; CHECK-BE-NEXT: lsls r2, r1, #29
1355 ; CHECK-BE-NEXT: bpl .LBB25_2
1356 ; CHECK-BE-NEXT: .LBB25_6: @ %cond.store1
1357 ; CHECK-BE-NEXT: vmovx.f16 s0, s0
1358 ; CHECK-BE-NEXT: vstr.16 s0, [r0, #2]
1359 ; CHECK-BE-NEXT: lsls r2, r1, #30
1360 ; CHECK-BE-NEXT: bpl .LBB25_3
1361 ; CHECK-BE-NEXT: .LBB25_7: @ %cond.store3
1362 ; CHECK-BE-NEXT: vstr.16 s1, [r0, #4]
1363 ; CHECK-BE-NEXT: lsls r1, r1, #31
1364 ; CHECK-BE-NEXT: beq .LBB25_4
1365 ; CHECK-BE-NEXT: .LBB25_8: @ %cond.store5
1366 ; CHECK-BE-NEXT: vmovx.f16 s0, s1
1367 ; CHECK-BE-NEXT: vstr.16 s0, [r0, #6]
1368 ; CHECK-BE-NEXT: add sp, #4
1369 ; CHECK-BE-NEXT: bx lr
1370 entry:
1371 %c = fcmp ogt <4 x float> %a, zeroinitializer
1372 %trunc = fptrunc <4 x float> %a to <4 x half>
1373 call void @llvm.masked.store.v4f16.p0v4f16(<4 x half> %trunc, <4 x half>* %dest, i32 4, <4 x i1> %c)
1374 ret void
1375 }
1377 define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float> %a) {
1378 ; CHECK-LE-LABEL: masked_v4f16_align2:
1379 ; CHECK-LE: @ %bb.0: @ %entry
1380 ; CHECK-LE-NEXT: .pad #4
1381 ; CHECK-LE-NEXT: sub sp, #4
1382 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
1383 ; CHECK-LE-NEXT: movs r1, #0
1384 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1385 ; CHECK-LE-NEXT: it gt
1386 ; CHECK-LE-NEXT: movgt r1, #1
1387 ; CHECK-LE-NEXT: cmp r1, #0
1388 ; CHECK-LE-NEXT: mov.w r1, #0
1389 ; CHECK-LE-NEXT: csetm r3, ne
1390 ; CHECK-LE-NEXT: vcmp.f32 s1, #0
1391 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
1392 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1393 ; CHECK-LE-NEXT: mov.w r3, #0
1394 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
1395 ; CHECK-LE-NEXT: it gt
1396 ; CHECK-LE-NEXT: movgt r3, #1
1397 ; CHECK-LE-NEXT: cmp r3, #0
1398 ; CHECK-LE-NEXT: csetm r3, ne
1399 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1400 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
1401 ; CHECK-LE-NEXT: mov.w r3, #0
1402 ; CHECK-LE-NEXT: it gt
1403 ; CHECK-LE-NEXT: movgt r3, #1
1404 ; CHECK-LE-NEXT: cmp r3, #0
1405 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
1406 ; CHECK-LE-NEXT: csetm r3, ne
1407 ; CHECK-LE-NEXT: movs r2, #0
1408 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1409 ; CHECK-LE-NEXT: it gt
1410 ; CHECK-LE-NEXT: movgt r2, #1
1411 ; CHECK-LE-NEXT: cmp r2, #0
1412 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
1413 ; CHECK-LE-NEXT: csetm r2, ne
1414 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
1415 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
1416 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
1417 ; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
1418 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
1419 ; CHECK-LE-NEXT: lsls r2, r1, #31
1420 ; CHECK-LE-NEXT: bne .LBB26_5
1421 ; CHECK-LE-NEXT: @ %bb.1: @ %else
1422 ; CHECK-LE-NEXT: lsls r2, r1, #30
1423 ; CHECK-LE-NEXT: bmi .LBB26_6
1424 ; CHECK-LE-NEXT: .LBB26_2: @ %else2
1425 ; CHECK-LE-NEXT: lsls r2, r1, #29
1426 ; CHECK-LE-NEXT: bmi .LBB26_7
1427 ; CHECK-LE-NEXT: .LBB26_3: @ %else4
1428 ; CHECK-LE-NEXT: lsls r1, r1, #28
1429 ; CHECK-LE-NEXT: bmi .LBB26_8
1430 ; CHECK-LE-NEXT: .LBB26_4: @ %else6
1431 ; CHECK-LE-NEXT: add sp, #4
1432 ; CHECK-LE-NEXT: bx lr
1433 ; CHECK-LE-NEXT: .LBB26_5: @ %cond.store
1434 ; CHECK-LE-NEXT: vstr.16 s4, [r0]
1435 ; CHECK-LE-NEXT: lsls r2, r1, #30
1436 ; CHECK-LE-NEXT: bpl .LBB26_2
1437 ; CHECK-LE-NEXT: .LBB26_6: @ %cond.store1
1438 ; CHECK-LE-NEXT: vmovx.f16 s0, s4
1439 ; CHECK-LE-NEXT: vstr.16 s0, [r0, #2]
1440 ; CHECK-LE-NEXT: lsls r2, r1, #29
1441 ; CHECK-LE-NEXT: bpl .LBB26_3
1442 ; CHECK-LE-NEXT: .LBB26_7: @ %cond.store3
1443 ; CHECK-LE-NEXT: vstr.16 s5, [r0, #4]
1444 ; CHECK-LE-NEXT: lsls r1, r1, #28
1445 ; CHECK-LE-NEXT: bpl .LBB26_4
1446 ; CHECK-LE-NEXT: .LBB26_8: @ %cond.store5
1447 ; CHECK-LE-NEXT: vmovx.f16 s0, s5
1448 ; CHECK-LE-NEXT: vstr.16 s0, [r0, #6]
1449 ; CHECK-LE-NEXT: add sp, #4
1450 ; CHECK-LE-NEXT: bx lr
1451 ;
1452 ; CHECK-BE-LABEL: masked_v4f16_align2:
1453 ; CHECK-BE: @ %bb.0: @ %entry
1454 ; CHECK-BE-NEXT: .pad #4
1455 ; CHECK-BE-NEXT: sub sp, #4
1456 ; CHECK-BE-NEXT: vrev64.32 q1, q0
1457 ; CHECK-BE-NEXT: movs r1, #0
1458 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
1459 ; CHECK-BE-NEXT: movs r2, #0
1460 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1461 ; CHECK-BE-NEXT: it gt
1462 ; CHECK-BE-NEXT: movgt r1, #1
1463 ; CHECK-BE-NEXT: cmp r1, #0
1464 ; CHECK-BE-NEXT: mov.w r1, #0
1465 ; CHECK-BE-NEXT: csetm r3, ne
1466 ; CHECK-BE-NEXT: vcmp.f32 s6, #0
1467 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
1468 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1469 ; CHECK-BE-NEXT: mov.w r3, #0
1470 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
1471 ; CHECK-BE-NEXT: it gt
1472 ; CHECK-BE-NEXT: movgt r3, #1
1473 ; CHECK-BE-NEXT: cmp r3, #0
1474 ; CHECK-BE-NEXT: csetm r3, ne
1475 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1476 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
1477 ; CHECK-BE-NEXT: mov.w r3, #0
1478 ; CHECK-BE-NEXT: it gt
1479 ; CHECK-BE-NEXT: movgt r3, #1
1480 ; CHECK-BE-NEXT: cmp r3, #0
1481 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
1482 ; CHECK-BE-NEXT: csetm r3, ne
1483 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1484 ; CHECK-BE-NEXT: it gt
1485 ; CHECK-BE-NEXT: movgt r2, #1
1486 ; CHECK-BE-NEXT: cmp r2, #0
1487 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
1488 ; CHECK-BE-NEXT: csetm r2, ne
1489 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
1490 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
1491 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
1492 ; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
1493 ; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
1494 ; CHECK-BE-NEXT: lsls r2, r1, #28
1495 ; CHECK-BE-NEXT: bmi .LBB26_5
1496 ; CHECK-BE-NEXT: @ %bb.1: @ %else
1497 ; CHECK-BE-NEXT: lsls r2, r1, #29
1498 ; CHECK-BE-NEXT: bmi .LBB26_6
1499 ; CHECK-BE-NEXT: .LBB26_2: @ %else2
1500 ; CHECK-BE-NEXT: lsls r2, r1, #30
1501 ; CHECK-BE-NEXT: bmi .LBB26_7
1502 ; CHECK-BE-NEXT: .LBB26_3: @ %else4
1503 ; CHECK-BE-NEXT: lsls r1, r1, #31
1504 ; CHECK-BE-NEXT: bne .LBB26_8
1505 ; CHECK-BE-NEXT: .LBB26_4: @ %else6
1506 ; CHECK-BE-NEXT: add sp, #4
1507 ; CHECK-BE-NEXT: bx lr
1508 ; CHECK-BE-NEXT: .LBB26_5: @ %cond.store
1509 ; CHECK-BE-NEXT: vstr.16 s0, [r0]
1510 ; CHECK-BE-NEXT: lsls r2, r1, #29
1511 ; CHECK-BE-NEXT: bpl .LBB26_2
1512 ; CHECK-BE-NEXT: .LBB26_6: @ %cond.store1
1513 ; CHECK-BE-NEXT: vmovx.f16 s0, s0
1514 ; CHECK-BE-NEXT: vstr.16 s0, [r0, #2]
1515 ; CHECK-BE-NEXT: lsls r2, r1, #30
1516 ; CHECK-BE-NEXT: bpl .LBB26_3
1517 ; CHECK-BE-NEXT: .LBB26_7: @ %cond.store3
1518 ; CHECK-BE-NEXT: vstr.16 s1, [r0, #4]
1519 ; CHECK-BE-NEXT: lsls r1, r1, #31
1520 ; CHECK-BE-NEXT: beq .LBB26_4
1521 ; CHECK-BE-NEXT: .LBB26_8: @ %cond.store5
1522 ; CHECK-BE-NEXT: vmovx.f16 s0, s1
1523 ; CHECK-BE-NEXT: vstr.16 s0, [r0, #6]
1524 ; CHECK-BE-NEXT: add sp, #4
1525 ; CHECK-BE-NEXT: bx lr
1526 entry:
1527 %c = fcmp ogt <4 x float> %a, zeroinitializer
1528 %trunc = fptrunc <4 x float> %a to <4 x half>
1529 call void @llvm.masked.store.v4f16.p0v4f16(<4 x half> %trunc, <4 x half>* %dest, i32 2, <4 x i1> %c)
1530 ret void
1531 }
1533 define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float> %a) {
1534 ; CHECK-LE-LABEL: masked_v4f16_align1:
1535 ; CHECK-LE: @ %bb.0: @ %entry
1536 ; CHECK-LE-NEXT: .pad #20
1537 ; CHECK-LE-NEXT: sub sp, #20
1538 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
1539 ; CHECK-LE-NEXT: movs r1, #0
1540 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1541 ; CHECK-LE-NEXT: it gt
1542 ; CHECK-LE-NEXT: movgt r1, #1
1543 ; CHECK-LE-NEXT: cmp r1, #0
1544 ; CHECK-LE-NEXT: mov.w r1, #0
1545 ; CHECK-LE-NEXT: csetm r3, ne
1546 ; CHECK-LE-NEXT: vcmp.f32 s1, #0
1547 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
1548 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1549 ; CHECK-LE-NEXT: mov.w r3, #0
1550 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
1551 ; CHECK-LE-NEXT: it gt
1552 ; CHECK-LE-NEXT: movgt r3, #1
1553 ; CHECK-LE-NEXT: cmp r3, #0
1554 ; CHECK-LE-NEXT: csetm r3, ne
1555 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1556 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
1557 ; CHECK-LE-NEXT: mov.w r3, #0
1558 ; CHECK-LE-NEXT: it gt
1559 ; CHECK-LE-NEXT: movgt r3, #1
1560 ; CHECK-LE-NEXT: cmp r3, #0
1561 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
1562 ; CHECK-LE-NEXT: csetm r3, ne
1563 ; CHECK-LE-NEXT: movs r2, #0
1564 ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
1565 ; CHECK-LE-NEXT: it gt
1566 ; CHECK-LE-NEXT: movgt r2, #1
1567 ; CHECK-LE-NEXT: cmp r2, #0
1568 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
1569 ; CHECK-LE-NEXT: csetm r2, ne
1570 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
1571 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
1572 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
1573 ; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
1574 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
1575 ; CHECK-LE-NEXT: lsls r2, r1, #31
1576 ; CHECK-LE-NEXT: bne .LBB27_5
1577 ; CHECK-LE-NEXT: @ %bb.1: @ %else
1578 ; CHECK-LE-NEXT: lsls r2, r1, #30
1579 ; CHECK-LE-NEXT: bmi .LBB27_6
1580 ; CHECK-LE-NEXT: .LBB27_2: @ %else2
1581 ; CHECK-LE-NEXT: lsls r2, r1, #29
1582 ; CHECK-LE-NEXT: bmi .LBB27_7
1583 ; CHECK-LE-NEXT: .LBB27_3: @ %else4
1584 ; CHECK-LE-NEXT: lsls r1, r1, #28
1585 ; CHECK-LE-NEXT: bmi .LBB27_8
1586 ; CHECK-LE-NEXT: .LBB27_4: @ %else6
1587 ; CHECK-LE-NEXT: add sp, #20
1588 ; CHECK-LE-NEXT: bx lr
1589 ; CHECK-LE-NEXT: .LBB27_5: @ %cond.store
1590 ; CHECK-LE-NEXT: vstr.16 s4, [sp, #12]
1591 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #12]
1592 ; CHECK-LE-NEXT: strh r2, [r0]
1593 ; CHECK-LE-NEXT: lsls r2, r1, #30
1594 ; CHECK-LE-NEXT: bpl .LBB27_2
1595 ; CHECK-LE-NEXT: .LBB27_6: @ %cond.store1
1596 ; CHECK-LE-NEXT: vmovx.f16 s0, s4
1597 ; CHECK-LE-NEXT: vstr.16 s0, [sp, #8]
1598 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #8]
1599 ; CHECK-LE-NEXT: strh r2, [r0, #2]
1600 ; CHECK-LE-NEXT: lsls r2, r1, #29
1601 ; CHECK-LE-NEXT: bpl .LBB27_3
1602 ; CHECK-LE-NEXT: .LBB27_7: @ %cond.store3
1603 ; CHECK-LE-NEXT: vstr.16 s5, [sp, #4]
1604 ; CHECK-LE-NEXT: ldrh.w r2, [sp, #4]
1605 ; CHECK-LE-NEXT: strh r2, [r0, #4]
1606 ; CHECK-LE-NEXT: lsls r1, r1, #28
1607 ; CHECK-LE-NEXT: bpl .LBB27_4
1608 ; CHECK-LE-NEXT: .LBB27_8: @ %cond.store5
1609 ; CHECK-LE-NEXT: vmovx.f16 s0, s5
1610 ; CHECK-LE-NEXT: vstr.16 s0, [sp]
1611 ; CHECK-LE-NEXT: ldrh.w r1, [sp]
1612 ; CHECK-LE-NEXT: strh r1, [r0, #6]
1613 ; CHECK-LE-NEXT: add sp, #20
1614 ; CHECK-LE-NEXT: bx lr
1615 ;
1616 ; CHECK-BE-LABEL: masked_v4f16_align1:
1617 ; CHECK-BE: @ %bb.0: @ %entry
1618 ; CHECK-BE-NEXT: .pad #20
1619 ; CHECK-BE-NEXT: sub sp, #20
1620 ; CHECK-BE-NEXT: vrev64.32 q1, q0
1621 ; CHECK-BE-NEXT: movs r1, #0
1622 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
1623 ; CHECK-BE-NEXT: movs r2, #0
1624 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1625 ; CHECK-BE-NEXT: it gt
1626 ; CHECK-BE-NEXT: movgt r1, #1
1627 ; CHECK-BE-NEXT: cmp r1, #0
1628 ; CHECK-BE-NEXT: mov.w r1, #0
1629 ; CHECK-BE-NEXT: csetm r3, ne
1630 ; CHECK-BE-NEXT: vcmp.f32 s6, #0
1631 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
1632 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1633 ; CHECK-BE-NEXT: mov.w r3, #0
1634 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
1635 ; CHECK-BE-NEXT: it gt
1636 ; CHECK-BE-NEXT: movgt r3, #1
1637 ; CHECK-BE-NEXT: cmp r3, #0
1638 ; CHECK-BE-NEXT: csetm r3, ne
1639 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1640 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
1641 ; CHECK-BE-NEXT: mov.w r3, #0
1642 ; CHECK-BE-NEXT: it gt
1643 ; CHECK-BE-NEXT: movgt r3, #1
1644 ; CHECK-BE-NEXT: cmp r3, #0
1645 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
1646 ; CHECK-BE-NEXT: csetm r3, ne
1647 ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
1648 ; CHECK-BE-NEXT: it gt
1649 ; CHECK-BE-NEXT: movgt r2, #1
1650 ; CHECK-BE-NEXT: cmp r2, #0
1651 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
1652 ; CHECK-BE-NEXT: csetm r2, ne
1653 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
1654 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
1655 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
1656 ; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
1657 ; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
1658 ; CHECK-BE-NEXT: lsls r2, r1, #28
1659 ; CHECK-BE-NEXT: bmi .LBB27_5
1660 ; CHECK-BE-NEXT: @ %bb.1: @ %else
1661 ; CHECK-BE-NEXT: lsls r2, r1, #29
1662 ; CHECK-BE-NEXT: bmi .LBB27_6
1663 ; CHECK-BE-NEXT: .LBB27_2: @ %else2
1664 ; CHECK-BE-NEXT: lsls r2, r1, #30
1665 ; CHECK-BE-NEXT: bmi .LBB27_7
1666 ; CHECK-BE-NEXT: .LBB27_3: @ %else4
1667 ; CHECK-BE-NEXT: lsls r1, r1, #31
1668 ; CHECK-BE-NEXT: bne .LBB27_8
1669 ; CHECK-BE-NEXT: .LBB27_4: @ %else6
1670 ; CHECK-BE-NEXT: add sp, #20
1671 ; CHECK-BE-NEXT: bx lr
1672 ; CHECK-BE-NEXT: .LBB27_5: @ %cond.store
1673 ; CHECK-BE-NEXT: vstr.16 s0, [sp, #12]
1674 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #12]
1675 ; CHECK-BE-NEXT: strh r2, [r0]
1676 ; CHECK-BE-NEXT: lsls r2, r1, #29
1677 ; CHECK-BE-NEXT: bpl .LBB27_2
1678 ; CHECK-BE-NEXT: .LBB27_6: @ %cond.store1
1679 ; CHECK-BE-NEXT: vmovx.f16 s0, s0
1680 ; CHECK-BE-NEXT: vstr.16 s0, [sp, #8]
1681 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #8]
1682 ; CHECK-BE-NEXT: strh r2, [r0, #2]
1683 ; CHECK-BE-NEXT: lsls r2, r1, #30
1684 ; CHECK-BE-NEXT: bpl .LBB27_3
1685 ; CHECK-BE-NEXT: .LBB27_7: @ %cond.store3
1686 ; CHECK-BE-NEXT: vstr.16 s1, [sp, #4]
1687 ; CHECK-BE-NEXT: ldrh.w r2, [sp, #4]
1688 ; CHECK-BE-NEXT: strh r2, [r0, #4]
1689 ; CHECK-BE-NEXT: lsls r1, r1, #31
1690 ; CHECK-BE-NEXT: beq .LBB27_4
1691 ; CHECK-BE-NEXT: .LBB27_8: @ %cond.store5
1692 ; CHECK-BE-NEXT: vmovx.f16 s0, s1
1693 ; CHECK-BE-NEXT: vstr.16 s0, [sp]
1694 ; CHECK-BE-NEXT: ldrh.w r1, [sp]
1695 ; CHECK-BE-NEXT: strh r1, [r0, #6]
1696 ; CHECK-BE-NEXT: add sp, #20
1697 ; CHECK-BE-NEXT: bx lr
1698 entry:
1699 %c = fcmp ogt <4 x float> %a, zeroinitializer
1700 %trunc = fptrunc <4 x float> %a to <4 x half>
1701 call void @llvm.masked.store.v4f16.p0v4f16(<4 x half> %trunc, <4 x half>* %dest, i32 1, <4 x i1> %c)
1702 ret void
1703 }
1705 declare void @llvm.masked.store.v4i8.p0v4i8(<4 x i8>, <4 x i8>*, i32, <4 x i1>)
1706 declare void @llvm.masked.store.v8i8.p0v8i8(<8 x i8>, <8 x i8>*, i32, <8 x i1>)
1707 declare void @llvm.masked.store.v4i16.p0v4i16(<4 x i16>, <4 x i16>*, i32, <4 x i1>)
1708 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
1709 declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>)
1710 declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>)
1711 declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>)
1712 declare void @llvm.masked.store.v4f16.p0v4f16(<4 x half>, <4 x half>*, i32, <4 x i1>)
1713 declare void @llvm.masked.store.v8f16.p0v8f16(<8 x half>, <8 x half>*, i32, <8 x i1>)
1714 declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)
1715 declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)